X-Git-Url: https://git.libre-soc.org/?a=blobdiff_plain;f=src%2Fmesa%2Fdrivers%2Fdri%2Fi965%2Fintel_mipmap_tree.c;h=87e0136693257598c56a37d6e35a09c7e3212e56;hb=179fc4aae8f782453f0488e8dd508f9a01117376;hp=31386b996565d08218765f23ceababfe351d4944;hpb=c1151b18f2dce7c6f238f057e9c4fa8d912ce6b5;p=mesa.git diff --git a/src/mesa/drivers/dri/i965/intel_mipmap_tree.c b/src/mesa/drivers/dri/i965/intel_mipmap_tree.c index 31386b99656..87e01366932 100644 --- a/src/mesa/drivers/dri/i965/intel_mipmap_tree.c +++ b/src/mesa/drivers/dri/i965/intel_mipmap_tree.c @@ -1,5 +1,4 @@ -/************************************************************************** - * +/* * Copyright 2006 VMware, Inc. * All Rights Reserved. * @@ -7,7 +6,7 @@ * copy of this software and associated documentation files (the * "Software"), to deal in the Software without restriction, including * without limitation the rights to use, copy, modify, merge, publish, - * distribute, sub license, and/or sell copies of the Software, and to + * distribute, sublicense, and/or sell copies of the Software, and to * permit persons to whom the Software is furnished to do so, subject to * the following conditions: * @@ -17,13 +16,12 @@ * * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS * OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF - * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT. + * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. * IN NO EVENT SHALL VMWARE AND/OR ITS SUPPLIERS BE LIABLE FOR * ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, * TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE * SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. - * - **************************************************************************/ + */ #include #include @@ -37,6 +35,7 @@ #include "brw_blorp.h" #include "brw_context.h" +#include "brw_state.h" #include "main/enums.h" #include "main/fbobject.h" @@ -49,6 +48,11 @@ #define FILE_DEBUG_FLAG DEBUG_MIPTREE +static void *intel_miptree_map_raw(struct brw_context *brw, + struct intel_mipmap_tree *mt); + +static void intel_miptree_unmap_raw(struct intel_mipmap_tree *mt); + static bool intel_miptree_alloc_mcs(struct brw_context *brw, struct intel_mipmap_tree *mt, @@ -59,7 +63,7 @@ intel_miptree_alloc_mcs(struct brw_context *brw, * created, based on the chip generation and the surface type. */ static enum intel_msaa_layout -compute_msaa_layout(struct brw_context *brw, mesa_format format, GLenum target, +compute_msaa_layout(struct brw_context *brw, mesa_format format, bool disable_aux_buffers) { /* Prior to Gen7, all MSAA surfaces used IMS layout. */ @@ -140,8 +144,7 @@ compute_msaa_layout(struct brw_context *brw, mesa_format format, GLenum target, * by half the block width, and Y coordinates by half the block height. */ void -intel_get_non_msrt_mcs_alignment(struct brw_context *brw, - struct intel_mipmap_tree *mt, +intel_get_non_msrt_mcs_alignment(struct intel_mipmap_tree *mt, unsigned *width_px, unsigned *height) { switch (mt->tiling) { @@ -158,7 +161,7 @@ intel_get_non_msrt_mcs_alignment(struct brw_context *brw, } } -bool +static bool intel_tiling_supports_non_msrt_mcs(struct brw_context *brw, unsigned tiling) { /* From the Ivy Bridge PRM, Vol2 Part1 11.7 "MCS Buffer for Render @@ -190,10 +193,16 @@ intel_tiling_supports_non_msrt_mcs(struct brw_context *brw, unsigned tiling) * * - MCS buffer for non-MSRT is supported only for RT formats 32bpp, * 64bpp, and 128bpp. + * + * From the Skylake documentation, it is made clear that X-tiling is no longer + * supported: + * + * - MCS and Lossless compression is supported for TiledY/TileYs/TileYf + * non-MSRTs only. */ -bool -intel_miptree_is_fast_clear_capable(struct brw_context *brw, - struct intel_mipmap_tree *mt) +static bool +intel_miptree_supports_non_msrt_fast_clear(struct brw_context *brw, + struct intel_mipmap_tree *mt) { /* MCS support does not exist prior to Gen7 */ if (brw->gen < 7) @@ -202,6 +211,10 @@ intel_miptree_is_fast_clear_capable(struct brw_context *brw, if (mt->disable_aux_buffers) return false; + /* This function applies only to non-multisampled render targets. */ + if (mt->num_samples > 1) + return false; + /* MCS is only supported for color buffers */ switch (_mesa_get_format_base_format(mt->format)) { case GL_DEPTH_COMPONENT: @@ -220,7 +233,16 @@ intel_miptree_is_fast_clear_capable(struct brw_context *brw, return false; } + + /* Check for layered surfaces. */ if (mt->physical_depth0 != 1) { + /* Multisample surfaces with the CMS layout are not layered surfaces, + * yet still have physical_depth0 > 1. Assert that we don't + * accidentally reject a multisampled surface here. We should have + * rejected it earlier by explicitly checking the sample count. + */ + assert(mt->num_samples <= 1); + if (brw->gen >= 8) { perf_debug("Layered fast clear - giving up. (%dx%d%d)\n", mt->logical_width0, mt->logical_height0, @@ -236,7 +258,11 @@ intel_miptree_is_fast_clear_capable(struct brw_context *brw, if (!brw->format_supported_as_render_target[mt->format]) return false; - return true; + if (brw->gen >= 9) { + const uint32_t brw_format = brw_format_for_mesa_format(mt->format); + return brw_losslessly_compressible_format(brw, brw_format); + } else + return true; } @@ -272,7 +298,6 @@ intel_miptree_create_layout(struct brw_context *brw, GLuint height0, GLuint depth0, GLuint num_samples, - enum intel_miptree_tiling_mode requested, uint32_t layout_flags) { struct intel_mipmap_tree *mt = calloc(sizeof(*mt), 1); @@ -280,7 +305,7 @@ intel_miptree_create_layout(struct brw_context *brw, return NULL; DBG("%s target %s format %s level %d..%d slices %d <-- %p\n", __func__, - _mesa_lookup_enum_by_nr(target), + _mesa_enum_to_string(target), _mesa_get_format_name(format), first_level, last_level, depth0, mt); @@ -314,15 +339,7 @@ intel_miptree_create_layout(struct brw_context *brw, mt->fast_clear_state = INTEL_FAST_CLEAR_STATE_NO_MCS; mt->disable_aux_buffers = (layout_flags & MIPTREE_LAYOUT_DISABLE_AUX) != 0; exec_list_make_empty(&mt->hiz_map); - - /* The cpp is bytes per (1, blockheight)-sized block for compressed - * textures. This is why you'll see divides by blockheight all over - */ - unsigned bw, bh; - _mesa_get_format_block_size(format, &bw, &bh); - assert(_mesa_get_format_bytes(mt->format) % bw == 0); - mt->cpp = _mesa_get_format_bytes(mt->format) / bw; - + mt->cpp = _mesa_get_format_bytes(format); mt->num_samples = num_samples; mt->compressed = _mesa_is_format_compressed(format); mt->msaa_layout = INTEL_MSAA_LAYOUT_NONE; @@ -331,7 +348,7 @@ intel_miptree_create_layout(struct brw_context *brw, if (num_samples > 1) { /* Adjust width/height/depth for MSAA */ mt->msaa_layout = compute_msaa_layout(brw, format, - mt->target, mt->disable_aux_buffers); + mt->disable_aux_buffers); if (mt->msaa_layout == INTEL_MSAA_LAYOUT_IMS) { /* From the Ivybridge PRM, Volume 1, Part 1, page 108: * "If the surface is multisampled and it is a depth or stencil @@ -402,9 +419,13 @@ intel_miptree_create_layout(struct brw_context *brw, width0 = ALIGN(width0, 2) * 4; height0 = ALIGN(height0, 2) * 2; break; + case 16: + width0 = ALIGN(width0, 2) * 4; + height0 = ALIGN(height0, 2) * 4; + break; default: - /* num_samples should already have been quantized to 0, 1, 2, 4, or - * 8. + /* num_samples should already have been quantized to 0, 1, 2, 4, 8 + * or 16. */ unreachable("not reached"); } @@ -454,8 +475,10 @@ intel_miptree_create_layout(struct brw_context *brw, (brw->has_separate_stencil && intel_miptree_wants_hiz_buffer(brw, mt)))) { uint32_t stencil_flags = MIPTREE_LAYOUT_ACCELERATED_UPLOAD; - if (brw->gen == 6) - stencil_flags |= MIPTREE_LAYOUT_FORCE_ALL_SLICE_AT_LOD; + if (brw->gen == 6) { + stencil_flags |= MIPTREE_LAYOUT_FORCE_ALL_SLICE_AT_LOD | + MIPTREE_LAYOUT_TILING_ANY; + } mt->stencil_mt = intel_miptree_create(brw, mt->target, @@ -466,7 +489,6 @@ intel_miptree_create_layout(struct brw_context *brw, mt->logical_height0, mt->logical_depth0, num_samples, - INTEL_MIPTREE_TILING_ANY, stencil_flags); if (!mt->stencil_mt) { @@ -500,7 +522,7 @@ intel_miptree_create_layout(struct brw_context *brw, * 7 | ? | ? * 6 | ? | ? */ - if (intel_miptree_is_fast_clear_capable(brw, mt)) { + if (intel_miptree_supports_non_msrt_fast_clear(brw, mt)) { if (brw->gen >= 9 || (brw->gen == 8 && num_samples <= 1)) layout_flags |= MIPTREE_LAYOUT_FORCE_HALIGN16; } else if (brw->gen >= 9 && num_samples > 1) { @@ -510,7 +532,7 @@ intel_miptree_create_layout(struct brw_context *brw, assert((layout_flags & MIPTREE_LAYOUT_FORCE_HALIGN16) == 0); } - brw_miptree_layout(brw, mt, requested, layout_flags); + brw_miptree_layout(brw, mt, layout_flags); if (mt->disable_aux_buffers) assert(mt->msaa_layout != INTEL_MSAA_LAYOUT_CMS); @@ -558,6 +580,33 @@ intel_lower_compressed_format(struct brw_context *brw, mesa_format format) } } +/* This function computes Yf/Ys tiled bo size, alignment and pitch. */ +static unsigned long +intel_get_yf_ys_bo_size(struct intel_mipmap_tree *mt, unsigned *alignment, + unsigned long *pitch) +{ + uint32_t tile_width, tile_height; + unsigned long stride, size, aligned_y; + + assert(mt->tr_mode != INTEL_MIPTREE_TRMODE_NONE); + intel_get_tile_dims(mt->tiling, mt->tr_mode, mt->cpp, + &tile_width, &tile_height); + + aligned_y = ALIGN(mt->total_height, tile_height); + stride = mt->total_width * mt->cpp; + stride = ALIGN(stride, tile_width); + size = stride * aligned_y; + + if (mt->tr_mode == INTEL_MIPTREE_TRMODE_YF) { + assert(size % 4096 == 0); + *alignment = 4096; + } else { + assert(size % (64 * 1024) == 0); + *alignment = 64 * 1024; + } + *pitch = stride; + return size; +} struct intel_mipmap_tree * intel_miptree_create(struct brw_context *brw, @@ -569,7 +618,6 @@ intel_miptree_create(struct brw_context *brw, GLuint height0, GLuint depth0, GLuint num_samples, - enum intel_miptree_tiling_mode requested_tiling, uint32_t layout_flags) { struct intel_mipmap_tree *mt; @@ -587,7 +635,7 @@ intel_miptree_create(struct brw_context *brw, mt = intel_miptree_create_layout(brw, target, format, first_level, last_level, width0, height0, depth0, num_samples, - requested_tiling, layout_flags); + layout_flags); /* * pitch == 0 || height == 0 indicates the null texture */ @@ -616,10 +664,22 @@ intel_miptree_create(struct brw_context *brw, alloc_flags |= BO_ALLOC_FOR_RENDER; unsigned long pitch; - mt->bo = drm_intel_bo_alloc_tiled(brw->bufmgr, "miptree", total_width, - total_height, mt->cpp, &mt->tiling, - &pitch, alloc_flags); mt->etc_format = etc_format; + + if (mt->tr_mode != INTEL_MIPTREE_TRMODE_NONE) { + unsigned alignment = 0; + unsigned long size; + size = intel_get_yf_ys_bo_size(mt, &alignment, &pitch); + assert(size); + mt->bo = drm_intel_bo_alloc_for_render(brw->bufmgr, "miptree", + size, alignment); + } else { + mt->bo = drm_intel_bo_alloc_tiled(brw->bufmgr, "miptree", + total_width, total_height, mt->cpp, + &mt->tiling, &pitch, + alloc_flags); + } + mt->pitch = pitch; /* If the BO is too large to fit in the aperture, we need to use the @@ -660,9 +720,9 @@ intel_miptree_create(struct brw_context *brw, * clear actually occurs. */ if (intel_tiling_supports_non_msrt_mcs(brw, mt->tiling) && - intel_miptree_is_fast_clear_capable(brw, mt)) { + intel_miptree_supports_non_msrt_fast_clear(brw, mt)) { mt->fast_clear_state = INTEL_FAST_CLEAR_STATE_RESOLVED; - assert(brw->gen < 8 || mt->align_w == 16 || num_samples <= 1); + assert(brw->gen < 8 || mt->halign == 16 || num_samples <= 1); } return mt; @@ -698,17 +758,16 @@ intel_miptree_create_for_bo(struct brw_context *brw, target = depth > 1 ? GL_TEXTURE_2D_ARRAY : GL_TEXTURE_2D; - /* 'requested' parameter of intel_miptree_create_layout() is relevant - * only for non bo miptree. Tiling for bo is already computed above. - * So, the tiling requested (INTEL_MIPTREE_TILING_ANY) below is - * just a place holder and will not make any change to the miptree - * tiling format. + /* The BO already has a tiling format and we shouldn't confuse the lower + * layers by making it try to find a tiling format again. */ + assert((layout_flags & MIPTREE_LAYOUT_TILING_ANY) == 0); + assert((layout_flags & MIPTREE_LAYOUT_TILING_NONE) == 0); + layout_flags |= MIPTREE_LAYOUT_FOR_BO; mt = intel_miptree_create_layout(brw, target, format, 0, 0, width, height, depth, 0, - INTEL_MIPTREE_TILING_ANY, layout_flags); if (!mt) return NULL; @@ -769,8 +828,9 @@ intel_update_winsys_renderbuffer_miptree(struct brw_context *intel, * clear actually occurs. */ if (intel_tiling_supports_non_msrt_mcs(intel, singlesample_mt->tiling) && - intel_miptree_is_fast_clear_capable(intel, singlesample_mt)) + intel_miptree_supports_non_msrt_fast_clear(intel, singlesample_mt)) { singlesample_mt->fast_clear_state = INTEL_FAST_CLEAR_STATE_RESOLVED; + } if (num_samples == 0) { intel_miptree_release(&irb->mt); @@ -816,11 +876,13 @@ intel_miptree_create_for_renderbuffer(struct brw_context *brw, uint32_t depth = 1; bool ok; GLenum target = num_samples > 1 ? GL_TEXTURE_2D_MULTISAMPLE : GL_TEXTURE_2D; + const uint32_t layout_flags = MIPTREE_LAYOUT_ACCELERATED_UPLOAD | + MIPTREE_LAYOUT_TILING_ANY; + mt = intel_miptree_create(brw, target, format, 0, 0, width, height, depth, num_samples, - INTEL_MIPTREE_TILING_ANY, - MIPTREE_LAYOUT_ACCELERATED_UPLOAD); + layout_flags); if (!mt) goto fail; @@ -888,12 +950,18 @@ intel_miptree_release(struct intel_mipmap_tree **mt) *mt = NULL; } + void -intel_miptree_get_dimensions_for_image(struct gl_texture_image *image, - int *width, int *height, int *depth) +intel_get_image_dims(struct gl_texture_image *image, + int *width, int *height, int *depth) { switch (image->TexObject->Target) { case GL_TEXTURE_1D_ARRAY: + /* For a 1D Array texture the OpenGL API will treat the image height as + * the number of array slices. For Intel hardware, we treat the 1D array + * as a 2D Array with a height of 1. So, here we want to swap image + * height and depth. + */ *width = image->Width; *height = 1; *depth = image->Height; @@ -937,7 +1005,7 @@ intel_miptree_match_image(struct intel_mipmap_tree *mt, if (image->TexFormat != mt_format) return false; - intel_miptree_get_dimensions_for_image(image, &width, &height, &depth); + intel_get_image_dims(image, &width, &height, &depth); if (mt->target == GL_TEXTURE_CUBE_MAP) depth = 6; @@ -1022,37 +1090,82 @@ intel_miptree_get_image_offset(const struct intel_mipmap_tree *mt, *y = mt->level[level].slice[slice].y_offset; } + +/** + * This function computes the tile_w (in bytes) and tile_h (in rows) of + * different tiling patterns. If the BO is untiled, tile_w is set to cpp + * and tile_h is set to 1. + */ +void +intel_get_tile_dims(uint32_t tiling, uint32_t tr_mode, uint32_t cpp, + uint32_t *tile_w, uint32_t *tile_h) +{ + if (tr_mode == INTEL_MIPTREE_TRMODE_NONE) { + switch (tiling) { + case I915_TILING_X: + *tile_w = 512; + *tile_h = 8; + break; + case I915_TILING_Y: + *tile_w = 128; + *tile_h = 32; + break; + case I915_TILING_NONE: + *tile_w = cpp; + *tile_h = 1; + break; + default: + unreachable("not reached"); + } + } else { + uint32_t aspect_ratio = 1; + assert(_mesa_is_pow_two(cpp)); + + switch (cpp) { + case 1: + *tile_h = 64; + break; + case 2: + case 4: + *tile_h = 32; + break; + case 8: + case 16: + *tile_h = 16; + break; + default: + unreachable("not reached"); + } + + if (cpp == 2 || cpp == 8) + aspect_ratio = 2; + + if (tr_mode == INTEL_MIPTREE_TRMODE_YS) + *tile_h *= 4; + + *tile_w = *tile_h * aspect_ratio * cpp; + } +} + + /** * This function computes masks that may be used to select the bits of the X * and Y coordinates that indicate the offset within a tile. If the BO is * untiled, the masks are set to 0. */ void -intel_miptree_get_tile_masks(const struct intel_mipmap_tree *mt, - uint32_t *mask_x, uint32_t *mask_y, - bool map_stencil_as_y_tiled) +intel_get_tile_masks(uint32_t tiling, uint32_t tr_mode, uint32_t cpp, + bool map_stencil_as_y_tiled, + uint32_t *mask_x, uint32_t *mask_y) { - int cpp = mt->cpp; - uint32_t tiling = mt->tiling; - + uint32_t tile_w_bytes, tile_h; if (map_stencil_as_y_tiled) tiling = I915_TILING_Y; - switch (tiling) { - default: - unreachable("not reached"); - case I915_TILING_NONE: - *mask_x = *mask_y = 0; - break; - case I915_TILING_X: - *mask_x = 512 / cpp - 1; - *mask_y = 7; - break; - case I915_TILING_Y: - *mask_x = 128 / cpp - 1; - *mask_y = 31; - break; - } + intel_get_tile_dims(tiling, tr_mode, cpp, &tile_w_bytes, &tile_h); + + *mask_x = tile_w_bytes / cpp - 1; + *mask_y = tile_h - 1; } /** @@ -1117,7 +1230,7 @@ intel_miptree_get_tile_offsets(const struct intel_mipmap_tree *mt, uint32_t x, y; uint32_t mask_x, mask_y; - intel_miptree_get_tile_masks(mt, &mask_x, &mask_y, false); + intel_get_tile_masks(mt->tiling, mt->tr_mode, mt->cpp, false, &mask_x, &mask_y); intel_miptree_get_image_offset(mt, level, slice, &x, &y); *tile_x = x & mask_x; @@ -1213,8 +1326,8 @@ intel_miptree_copy_slice(struct brw_context *brw, if (dst_mt->compressed) { unsigned int i, j; _mesa_get_format_block_size(dst_mt->format, &i, &j); - height = ALIGN(height, j) / j; - width = ALIGN(width, i); + height = ALIGN_NPOT(height, j) / j; + width = ALIGN_NPOT(width, i) / i; } /* If it's a packed depth/stencil buffer with separate stencil, the blit @@ -1317,6 +1430,12 @@ intel_miptree_alloc_mcs(struct brw_context *brw, */ format = MESA_FORMAT_R_UINT32; break; + case 16: + /* 64 bits/pixel are required for MCS data when using 16x MSAA (4 bits + * for each sample). + */ + format = MESA_FORMAT_RG_UINT32; + break; default: unreachable("Unrecognized sample count in intel_miptree_alloc_mcs"); }; @@ -1325,6 +1444,8 @@ intel_miptree_alloc_mcs(struct brw_context *brw, * * "The MCS surface must be stored as Tile Y." */ + const uint32_t mcs_flags = MIPTREE_LAYOUT_ACCELERATED_UPLOAD | + MIPTREE_LAYOUT_TILING_Y; mt->mcs_mt = intel_miptree_create(brw, mt->target, format, @@ -1334,8 +1455,7 @@ intel_miptree_alloc_mcs(struct brw_context *brw, mt->logical_height0, mt->logical_depth0, 0 /* num_samples */, - INTEL_MIPTREE_TILING_Y, - MIPTREE_LAYOUT_ACCELERATED_UPLOAD); + mcs_flags); /* From the Ivy Bridge PRM, Vol 2 Part 1 p326: * @@ -1349,7 +1469,7 @@ intel_miptree_alloc_mcs(struct brw_context *brw, */ void *data = intel_miptree_map_raw(brw, mt->mcs_mt); memset(data, 0xff, mt->mcs_mt->total_height * mt->mcs_mt->pitch); - intel_miptree_unmap_raw(brw, mt->mcs_mt); + intel_miptree_unmap_raw(mt->mcs_mt); mt->fast_clear_state = INTEL_FAST_CLEAR_STATE_CLEAR; return mt->mcs_mt; @@ -1375,17 +1495,30 @@ intel_miptree_alloc_non_msrt_mcs(struct brw_context *brw, const mesa_format format = MESA_FORMAT_R_UINT32; unsigned block_width_px; unsigned block_height; - intel_get_non_msrt_mcs_alignment(brw, mt, &block_width_px, &block_height); + intel_get_non_msrt_mcs_alignment(mt, &block_width_px, &block_height); unsigned width_divisor = block_width_px * 4; unsigned height_divisor = block_height * 8; + + /* The Skylake MCS is twice as tall as the Broadwell MCS. + * + * In pre-Skylake, each bit in the MCS contained the state of 2 cachelines + * in the main surface. In Skylake, it's two bits. The extra bit + * doubles the MCS height, not width, because in Skylake the MCS is always + * Y-tiled. + */ + if (brw->gen >= 9) + height_divisor /= 2; + unsigned mcs_width = ALIGN(mt->logical_width0, width_divisor) / width_divisor; unsigned mcs_height = ALIGN(mt->logical_height0, height_divisor) / height_divisor; assert(mt->logical_depth0 == 1); - uint32_t layout_flags = MIPTREE_LAYOUT_ACCELERATED_UPLOAD; - if (brw->gen >= 8) + uint32_t layout_flags = MIPTREE_LAYOUT_ACCELERATED_UPLOAD | + MIPTREE_LAYOUT_TILING_Y; + if (brw->gen >= 8) { layout_flags |= MIPTREE_LAYOUT_FORCE_HALIGN16; + } mt->mcs_mt = intel_miptree_create(brw, mt->target, format, @@ -1395,7 +1528,6 @@ intel_miptree_alloc_non_msrt_mcs(struct brw_context *brw, mcs_height, mt->logical_depth0, 0 /* num_samples */, - INTEL_MIPTREE_TILING_Y, layout_flags); return mt->mcs_mt; @@ -1456,23 +1588,21 @@ intel_gen7_hiz_buf_create(struct brw_context *brw, /* Gen7 PRM Volume 2, Part 1, 11.5.3 "Hierarchical Depth Buffer" documents * adjustments required for Z_Height and Z_Width based on multisampling. */ - if (brw->gen < 9) { - switch (mt->num_samples) { - case 0: - case 1: - break; - case 2: - case 4: - z_width *= 2; - z_height *= 2; - break; - case 8: - z_width *= 4; - z_height *= 2; - break; - default: - unreachable("unsupported sample count"); - } + switch (mt->num_samples) { + case 0: + case 1: + break; + case 2: + case 4: + z_width *= 2; + z_height *= 2; + break; + case 8: + z_width *= 4; + z_height *= 2; + break; + default: + unreachable("unsupported sample count"); } const unsigned vertical_align = 8; /* 'j' in the docs */ @@ -1488,7 +1618,7 @@ intel_gen7_hiz_buf_create(struct brw_context *brw, unsigned H_i = H0; unsigned Z_i = Z0; hz_height = 0; - for (int level = mt->first_level; level <= mt->last_level; ++level) { + for (unsigned level = mt->first_level; level <= mt->last_level; ++level) { unsigned h_i = ALIGN(H_i, vertical_align); /* sum(i=0 to m; h_i * max(1, floor(Z_Depth/2**i))) */ hz_height += h_i * Z_i; @@ -1552,21 +1682,23 @@ intel_gen8_hiz_buf_create(struct brw_context *brw, /* Gen7 PRM Volume 2, Part 1, 11.5.3 "Hierarchical Depth Buffer" documents * adjustments required for Z_Height and Z_Width based on multisampling. */ - switch (mt->num_samples) { - case 0: - case 1: - break; - case 2: - case 4: - z_width *= 2; - z_height *= 2; - break; - case 8: - z_width *= 4; - z_height *= 2; - break; - default: - unreachable("unsupported sample count"); + if (brw->gen < 9) { + switch (mt->num_samples) { + case 0: + case 1: + break; + case 2: + case 4: + z_width *= 2; + z_height *= 2; + break; + case 8: + z_width *= 4; + z_height *= 2; + break; + default: + unreachable("unsupported sample count"); + } } const unsigned vertical_align = 8; /* 'j' in the docs */ @@ -1582,7 +1714,7 @@ intel_gen8_hiz_buf_create(struct brw_context *brw, unsigned Z_i = Z0; unsigned sum_h_i = 0; unsigned hz_height_3d_sum = 0; - for (int level = mt->first_level; level <= mt->last_level; ++level) { + for (unsigned level = mt->first_level; level <= mt->last_level; ++level) { unsigned i = level - mt->first_level; unsigned h_i = ALIGN(H_i, vertical_align); /* sum(i=2 to m; h_i) */ @@ -1648,6 +1780,7 @@ intel_hiz_miptree_buf_create(struct brw_context *brw, if (!buf) return NULL; + layout_flags |= MIPTREE_LAYOUT_TILING_ANY; buf->mt = intel_miptree_create(brw, mt->target, mt->format, @@ -1657,7 +1790,6 @@ intel_hiz_miptree_buf_create(struct brw_context *brw, mt->logical_height0, mt->logical_depth0, mt->num_samples, - INTEL_MIPTREE_TILING_ANY, layout_flags); if (!buf->mt) { free(buf); @@ -1715,11 +1847,11 @@ intel_miptree_alloc_hiz(struct brw_context *brw, return false; /* Mark that all slices need a HiZ resolve. */ - for (int level = mt->first_level; level <= mt->last_level; ++level) { + for (unsigned level = mt->first_level; level <= mt->last_level; ++level) { if (!intel_miptree_level_enable_hiz(brw, mt, level)) continue; - for (int layer = 0; layer < mt->level[level].depth; ++layer) { + for (unsigned layer = 0; layer < mt->level[level].depth; ++layer) { struct intel_resolve_map *m = malloc(sizeof(struct intel_resolve_map)); exec_node_init(&m->link); m->level = level; @@ -2020,8 +2152,7 @@ intel_miptree_map_raw(struct brw_context *brw, struct intel_mipmap_tree *mt) } void -intel_miptree_unmap_raw(struct brw_context *brw, - struct intel_mipmap_tree *mt) +intel_miptree_unmap_raw(struct intel_mipmap_tree *mt) { drm_intel_bo_unmap(mt->bo); } @@ -2044,7 +2175,9 @@ intel_miptree_map_gtt(struct brw_context *brw, */ _mesa_get_format_block_size(mt->format, &bw, &bh); assert(y % bh == 0); + assert(x % bw == 0); y /= bh; + x /= bw; base = intel_miptree_map_raw(brw, mt) + mt->offset; @@ -2070,13 +2203,9 @@ intel_miptree_map_gtt(struct brw_context *brw, } static void -intel_miptree_unmap_gtt(struct brw_context *brw, - struct intel_mipmap_tree *mt, - struct intel_miptree_map *map, - unsigned int level, - unsigned int slice) +intel_miptree_unmap_gtt(struct intel_mipmap_tree *mt) { - intel_miptree_unmap_raw(brw, mt); + intel_miptree_unmap_raw(mt); } static void @@ -2085,16 +2214,18 @@ intel_miptree_map_blit(struct brw_context *brw, struct intel_miptree_map *map, unsigned int level, unsigned int slice) { - map->mt = intel_miptree_create(brw, GL_TEXTURE_2D, mt->format, - 0, 0, - map->w, map->h, 1, - 0, INTEL_MIPTREE_TILING_NONE, 0); + map->linear_mt = intel_miptree_create(brw, GL_TEXTURE_2D, mt->format, + /* first_level */ 0, + /* last_level */ 0, + map->w, map->h, 1, + /* samples */ 0, + MIPTREE_LAYOUT_TILING_NONE); - if (!map->mt) { + if (!map->linear_mt) { fprintf(stderr, "Failed to allocate blit temporary\n"); goto fail; } - map->stride = map->mt->pitch; + map->stride = map->linear_mt->pitch; /* One of either READ_BIT or WRITE_BIT or both is set. READ_BIT implies no * INVALIDATE_RANGE_BIT. WRITE_BIT needs the original values read in unless @@ -2105,7 +2236,7 @@ intel_miptree_map_blit(struct brw_context *brw, if (!intel_miptree_blit(brw, mt, level, slice, map->x, map->y, false, - map->mt, 0, 0, + map->linear_mt, 0, 0, 0, 0, false, map->w, map->h, GL_COPY)) { fprintf(stderr, "Failed to blit\n"); @@ -2113,7 +2244,7 @@ intel_miptree_map_blit(struct brw_context *brw, } } - map->ptr = intel_miptree_map_raw(brw, map->mt); + map->ptr = intel_miptree_map_raw(brw, map->linear_mt); DBG("%s: %d,%d %dx%d from mt %p (%s) %d,%d = %p/%d\n", __func__, map->x, map->y, map->w, map->h, @@ -2123,7 +2254,7 @@ intel_miptree_map_blit(struct brw_context *brw, return; fail: - intel_miptree_release(&map->mt); + intel_miptree_release(&map->linear_mt); map->ptr = NULL; map->stride = 0; } @@ -2137,11 +2268,11 @@ intel_miptree_unmap_blit(struct brw_context *brw, { struct gl_context *ctx = &brw->ctx; - intel_miptree_unmap_raw(brw, map->mt); + intel_miptree_unmap_raw(map->linear_mt); if (map->mode & GL_MAP_WRITE_BIT) { bool ok = intel_miptree_blit(brw, - map->mt, 0, 0, + map->linear_mt, 0, 0, 0, 0, false, mt, level, slice, map->x, map->y, false, @@ -2149,7 +2280,7 @@ intel_miptree_unmap_blit(struct brw_context *brw, WARN_ONCE(!ok, "Failed to blit from linear temporary mapping"); } - intel_miptree_release(&map->mt); + intel_miptree_release(&map->linear_mt); } /** @@ -2209,7 +2340,7 @@ intel_miptree_map_movntdqa(struct brw_context *brw, _mesa_streaming_load_memcpy(dst_ptr, src_ptr, width_bytes); } - intel_miptree_unmap_raw(brw, mt); + intel_miptree_unmap_raw(mt); } static void @@ -2258,7 +2389,7 @@ intel_miptree_map_s8(struct brw_context *brw, } } - intel_miptree_unmap_raw(brw, mt); + intel_miptree_unmap_raw(mt); DBG("%s: %d,%d %dx%d from mt %p %d,%d = %p/%d\n", __func__, map->x, map->y, map->w, map->h, @@ -2294,7 +2425,7 @@ intel_miptree_unmap_s8(struct brw_context *brw, } } - intel_miptree_unmap_raw(brw, mt); + intel_miptree_unmap_raw(mt); } free(map->buffer); @@ -2348,7 +2479,7 @@ intel_miptree_unmap_etc(struct brw_context *brw, map->ptr, map->stride, map->w, map->h, mt->etc_format); - intel_miptree_unmap_raw(brw, mt); + intel_miptree_unmap_raw(mt); free(map->buffer); } @@ -2418,8 +2549,8 @@ intel_miptree_map_depthstencil(struct brw_context *brw, } } - intel_miptree_unmap_raw(brw, s_mt); - intel_miptree_unmap_raw(brw, z_mt); + intel_miptree_unmap_raw(s_mt); + intel_miptree_unmap_raw(z_mt); DBG("%s: %d,%d %dx%d from z mt %p %d,%d, s mt %p %d,%d = %p/%d\n", __func__, @@ -2478,8 +2609,8 @@ intel_miptree_unmap_depthstencil(struct brw_context *brw, } } - intel_miptree_unmap_raw(brw, s_mt); - intel_miptree_unmap_raw(brw, z_mt); + intel_miptree_unmap_raw(s_mt); + intel_miptree_unmap_raw(z_mt); DBG("%s: %d,%d %dx%d from z mt %p (%s) %d,%d, s mt %p %d,%d = %p/%d\n", __func__, @@ -2673,14 +2804,14 @@ intel_miptree_unmap(struct brw_context *brw, intel_miptree_unmap_etc(brw, mt, map, level, slice); } else if (mt->stencil_mt && !(map->mode & BRW_MAP_DIRECT_BIT)) { intel_miptree_unmap_depthstencil(brw, mt, map, level, slice); - } else if (map->mt) { + } else if (map->linear_mt) { intel_miptree_unmap_blit(brw, mt, map, level, slice); #if defined(USE_SSE41) } else if (map->buffer && cpu_has_sse4_1) { intel_miptree_unmap_movntdqa(brw, mt, map, level, slice); #endif } else { - intel_miptree_unmap_gtt(brw, mt, map, level, slice); + intel_miptree_unmap_gtt(mt); } intel_miptree_release_map(mt, level, slice);