X-Git-Url: https://git.libre-soc.org/?a=blobdiff_plain;f=src%2Fmesa%2Fdrivers%2Fdri%2Fi965%2Fintel_mipmap_tree.h;h=583a75103ef0f69472994904e207a8ff5529f9f1;hb=baa9e059659ed834d084ee4faf6271a8dd508494;hp=29d0e2fac65f2272531083b963844b97ec33d479;hpb=d41fc8dc9f17aa04000586f01fe543c690cf2c8e;p=mesa.git diff --git a/src/mesa/drivers/dri/i965/intel_mipmap_tree.h b/src/mesa/drivers/dri/i965/intel_mipmap_tree.h index 29d0e2fac65..583a75103ef 100644 --- a/src/mesa/drivers/dri/i965/intel_mipmap_tree.h +++ b/src/mesa/drivers/dri/i965/intel_mipmap_tree.h @@ -31,7 +31,7 @@ * The hardware has a fixed layout of a texture depending on parameters such * as the target/type (2D, 3D, CUBE), width, height, pitch, and number of * mipmap levels. The individual level/layer slices are each 2D rectangles of - * pixels at some x/y offset from the start of the drm_intel_bo. + * pixels at some x/y offset from the start of the brw_bo. * * Original OpenGL allowed texture miplevels to be specified in arbitrary * order, and a texture may change size over time. Thus, each @@ -48,8 +48,8 @@ #include "main/mtypes.h" #include "isl/isl.h" -#include "intel_bufmgr.h" -#include "intel_resolve_map.h" +#include "blorp/blorp.h" +#include "brw_bufmgr.h" #include #ifdef __cplusplus @@ -59,7 +59,6 @@ extern "C" { struct brw_context; struct intel_renderbuffer; -struct intel_resolve_map; struct intel_texture_image; /** @@ -100,21 +99,6 @@ struct intel_mipmap_level /** Offset to this miptree level, used in computing y_offset. */ GLuint level_y; - /** - * \brief Number of 2D slices in this miplevel. - * - * The exact semantics of depth varies according to the texture target: - * - For GL_TEXTURE_CUBE_MAP, depth is 6. - * - For GL_TEXTURE_2D_ARRAY, depth is the number of array slices. It is - * identical for all miplevels in the texture. - * - For GL_TEXTURE_3D, it is the texture's depth at this miplevel. Its - * value, like width and height, varies with miplevel. - * - For other texture types, depth is 1. - * - Additionally, for UMS and CMS miptrees, depth is multiplied by - * sample count. - */ - GLuint depth; - /** * \brief Is HiZ enabled for this level? * @@ -131,26 +115,6 @@ struct intel_mipmap_level * layers in a 3D texture. The list's length is \c depth. */ struct intel_mipmap_slice { - /** - * \name Offset to slice - * \{ - * - * Hardware formats are so diverse that that there is no unified way to - * compute the slice offsets, so we store them in this table. - * - * The (x, y) offset to slice \c s at level \c l relative the miptrees - * base address is - * \code - * x = mt->level[l].slice[s].x_offset - * y = mt->level[l].slice[s].y_offset - * - * On some hardware generations, we program these offsets into - * RENDER_SURFACE_STATE.XOffset and RENDER_SURFACE_STATE.YOffset. - */ - GLuint x_offset; - GLuint y_offset; - /** \} */ - /** * Mapping information. Persistent for the duration of * intel_miptree_map/unmap on this slice. @@ -159,100 +123,6 @@ struct intel_mipmap_level } *slice; }; -/** - * Enum for keeping track of the different MSAA layouts supported by Gen7. - */ -enum intel_msaa_layout -{ - /** - * Ordinary surface with no MSAA. - */ - INTEL_MSAA_LAYOUT_NONE, - - /** - * Interleaved Multisample Surface. The additional samples are - * accommodated by scaling up the width and the height of the surface so - * that all the samples corresponding to a pixel are located at nearby - * memory locations. - * - * @see PRM section "Interleaved Multisampled Surfaces" - */ - INTEL_MSAA_LAYOUT_IMS, - - /** - * Uncompressed Multisample Surface. The surface is stored as a 2D array, - * with array slice n containing all pixel data for sample n. - * - * @see PRM section "Uncompressed Multisampled Surfaces" - */ - INTEL_MSAA_LAYOUT_UMS, - - /** - * Compressed Multisample Surface. The surface is stored as in - * INTEL_MSAA_LAYOUT_UMS, but there is an additional buffer called the MCS - * (Multisample Control Surface) buffer. Each pixel in the MCS buffer - * indicates the mapping from sample number to array slice. This allows - * the common case (where all samples constituting a pixel have the same - * color value) to be stored efficiently by just using a single array - * slice. - * - * @see PRM section "Compressed Multisampled Surfaces" - */ - INTEL_MSAA_LAYOUT_CMS, -}; - -enum miptree_array_layout { - /* Each array slice contains all miplevels packed together. - * - * Gen hardware usually wants multilevel miptrees configured this way. - * - * A 2D Array texture with 2 slices and multiple LODs using - * ALL_LOD_IN_EACH_SLICE would look somewhat like this: - * - * +----------+ - * | | - * | | - * +----------+ - * +---+ +-+ - * | | +-+ - * +---+ * - * +----------+ - * | | - * | | - * +----------+ - * +---+ +-+ - * | | +-+ - * +---+ * - */ - ALL_LOD_IN_EACH_SLICE, - - /* Each LOD contains all slices of that LOD packed together. - * - * In some situations, Gen7+ hardware can use the array_spacing_lod0 - * feature to save space when the surface only contains LOD 0. - * - * Gen6 uses this for separate stencil and hiz since gen6 does not support - * multiple LODs for separate stencil and hiz. - * - * A 2D Array texture with 2 slices and multiple LODs using - * ALL_SLICES_AT_EACH_LOD would look somewhat like this: - * - * +----------+ - * | | - * | | - * +----------+ - * | | - * | | - * +----------+ - * +---+ +-+ - * | | +-+ - * +---+ +-+ - * | | : - * +---+ - */ - ALL_SLICES_AT_EACH_LOD, -}; - /** * Miptree aux buffer. These buffers are associated with a miptree, but the * format is managed by the hardware. @@ -263,13 +133,15 @@ enum miptree_array_layout { */ struct intel_miptree_aux_buffer { + struct isl_surf surf; + /** * Buffer object containing the pixel data. * * @see RENDER_SURFACE_STATE.AuxiliarySurfaceBaseAddress * @see 3DSTATE_HIER_DEPTH_BUFFER.AuxiliarySurfaceBaseAddress */ - drm_intel_bo *bo; + struct brw_bo *bo; /** * Offset into bo where the surface starts. @@ -308,30 +180,11 @@ struct intel_miptree_aux_buffer */ uint32_t qpitch; }; -/** - * The HiZ buffer requires extra attributes on earlier GENs. This is easily - * contained within an intel_mipmap_tree. To make sure we do not abuse this, we - * keep the hiz datastructure separate. - */ -struct intel_miptree_hiz_buffer -{ - struct intel_miptree_aux_buffer aux_base; - - /** - * Hiz miptree. Used only by Gen6. - */ - struct intel_mipmap_tree *mt; -}; - -/* Tile resource modes */ -enum intel_miptree_tr_mode { - INTEL_MIPTREE_TRMODE_NONE, - INTEL_MIPTREE_TRMODE_YF, - INTEL_MIPTREE_TRMODE_YS -}; struct intel_mipmap_tree { + struct isl_surf surf; + /** * Buffer object containing the surface. * @@ -342,32 +195,7 @@ struct intel_mipmap_tree * @see 3DSTATE_HIER_DEPTH_BUFFER.SurfaceBaseAddress * @see 3DSTATE_STENCIL_BUFFER.SurfaceBaseAddress */ - drm_intel_bo *bo; - - /** - * Pitch in bytes. - * - * @see RENDER_SURFACE_STATE.SurfacePitch - * @see RENDER_SURFACE_STATE.AuxiliarySurfacePitch - * @see 3DSTATE_DEPTH_BUFFER.SurfacePitch - * @see 3DSTATE_HIER_DEPTH_BUFFER.SurfacePitch - * @see 3DSTATE_STENCIL_BUFFER.SurfacePitch - */ - uint32_t pitch; - - /** - * One of the I915_TILING_* flags. - * - * @see RENDER_SURFACE_STATE.TileMode - * @see 3DSTATE_DEPTH_BUFFER.TileMode - */ - uint32_t tiling; - - /** - * @see RENDER_SURFACE_STATE.TiledResourceMode - * @see 3DSTATE_DEPTH_BUFFER.TiledResourceMode - */ - enum intel_miptree_tr_mode tr_mode; + struct brw_bo *bo; /** * @brief One of GL_TEXTURE_2D, GL_TEXTURE_2D_ARRAY, etc. @@ -404,130 +232,14 @@ struct intel_mipmap_tree */ mesa_format etc_format; - /** - * @name Surface Alignment - * @{ - * - * This defines the alignment of the upperleft pixel of each "slice" in the - * surface. The alignment is in pixel coordinates relative to the surface's - * most upperleft pixel, which is the pixel at (x=0, y=0, layer=0, - * level=0). - * - * The hardware docs do not use the term "slice". We use "slice" to mean - * the pixels at a given miplevel and layer. For 2D surfaces, the layer is - * the array slice; for 3D surfaces, the layer is the z offset. - * - * In the surface layout equations found in the hardware docs, the - * horizontal and vertical surface alignments often appear as variables 'i' - * and 'j'. - */ - - /** @see RENDER_SURFACE_STATE.SurfaceHorizontalAlignment */ - uint32_t halign; - - /** @see RENDER_SURFACE_STATE.SurfaceVerticalAlignment */ - uint32_t valign; - /** @} */ - GLuint first_level; GLuint last_level; - /** - * Level zero image dimensions. These dimensions correspond to the - * physical layout of data in memory. Accordingly, they account for the - * extra width, height, and or depth that must be allocated in order to - * accommodate multisample formats, and they account for the extra factor - * of 6 in depth that must be allocated in order to accommodate cubemap - * textures. - */ - GLuint physical_width0, physical_height0, physical_depth0; - /** Bytes per pixel (or bytes per block if compressed) */ GLuint cpp; - /** - * @see RENDER_SURFACE_STATE.NumberOfMultisamples - * @see 3DSTATE_MULTISAMPLE.NumberOfMultisamples - */ - GLuint num_samples; - bool compressed; - /** - * @name Level zero image dimensions - * @{ - * - * These dimensions correspond to the - * logical width, height, and depth of the texture as seen by client code. - * Accordingly, they do not account for the extra width, height, and/or - * depth that must be allocated in order to accommodate multisample - * formats, nor do they account for the extra factor of 6 in depth that - * must be allocated in order to accommodate cubemap textures. - */ - - /** - * @see RENDER_SURFACE_STATE.Width - * @see 3DSTATE_DEPTH_BUFFER.Width - */ - uint32_t logical_width0; - - /** - * @see RENDER_SURFACE_STATE.Height - * @see 3DSTATE_DEPTH_BUFFER.Height - */ - uint32_t logical_height0; - - /** - * @see RENDER_SURFACE_STATE.Depth - * @see 3DSTATE_DEPTH_BUFFER.Depth - */ - uint32_t logical_depth0; - /** @} */ - - /** - * Indicates if we use the standard miptree layout (ALL_LOD_IN_EACH_SLICE), - * or if we tightly pack array slices at each LOD (ALL_SLICES_AT_EACH_LOD). - */ - enum miptree_array_layout array_layout; - - /** - * The distance in between array slices. - * - * The value is the one that is sent in the surface state. The actual - * meaning depends on certain criteria. Usually it is simply the number of - * uncompressed rows between each slice. However on Gen9+ for compressed - * surfaces it is the number of blocks. For 1D array surfaces that have the - * mipmap tree stored horizontally it is the number of pixels between each - * slice. - * - * @see RENDER_SURFACE_STATE.SurfaceQPitch - * @see 3DSTATE_DEPTH_BUFFER.SurfaceQPitch - * @see 3DSTATE_HIER_DEPTH_BUFFER.SurfaceQPitch - * @see 3DSTATE_STENCIL_BUFFER.SurfaceQPitch - */ - uint32_t qpitch; - - /** - * MSAA layout used by this buffer. - * - * @see RENDER_SURFACE_STATE.MultisampledSurfaceStorageFormat - */ - enum intel_msaa_layout msaa_layout; - - /* Derived from the above: - */ - GLuint total_width; - GLuint total_height; - - /** - * The depth value used during the most recent fast depth clear performed - * on the surface. This field is invalid only if surface has never - * underwent a fast depth clear. - * - * @see 3DSTATE_CLEAR_PARAMS.DepthClearValue - */ - uint32_t depth_clear_value; - /* Includes image offset tables: */ struct intel_mipmap_level level[MAX_TEXTURE_LEVELS]; @@ -549,27 +261,36 @@ struct intel_mipmap_tree * To allocate the hiz buffer, use intel_miptree_alloc_hiz(). * * To determine if hiz is enabled, do not check this pointer. Instead, use - * intel_miptree_slice_has_hiz(). + * intel_miptree_level_has_hiz(). */ - struct intel_miptree_hiz_buffer *hiz_buf; + struct intel_miptree_aux_buffer *hiz_buf; /** - * \brief Maps of miptree slices to needed resolves. - * - * hiz_map is used only when the miptree has a child HiZ miptree. - * - * Let \c mt be a depth miptree with HiZ enabled. Then the resolve map is - * \c mt->hiz_map. The resolve map of the child HiZ miptree, \c - * mt->hiz_mt->hiz_map, is unused. + * \brief The type of auxiliary compression used by this miptree. * + * This describes the type of auxiliary compression that is intended to be + * used by this miptree. An aux usage of ISL_AUX_USAGE_NONE means that + * auxiliary compression is permanently disabled. An aux usage other than + * ISL_AUX_USAGE_NONE does not imply that the auxiliary buffer has actually + * been allocated nor does it imply that auxiliary compression will always + * be enabled for this surface. For instance, with CCS_D, we may allocate + * the CCS on-the-fly and it may not be used for texturing if the miptree + * is fully resolved. + */ + enum isl_aux_usage aux_usage; + + /** + * \brief Whether or not this miptree supports fast clears. + */ + bool supports_fast_clear; + + /** + * \brief Maps miptree slices to their current aux state * - * color_resolve_map is used only when the miptree uses fast clear (Gen7+) - * lossless compression (Gen9+). It should be noted that absence in the - * map means implicitly RESOLVED state. If item is found it always - * indicates state other than RESOLVED. + * This two-dimensional array is indexed as [level][layer] and stores an + * aux state for each slice. */ - struct exec_list hiz_map; /* List of intel_resolve_map. */ - struct exec_list color_resolve_map; /* List of intel_resolve_map. */ + enum isl_aux_state **aux_state; /** * \brief Stencil miptree for depthstencil textures. @@ -613,79 +334,23 @@ struct intel_mipmap_tree struct intel_mipmap_tree *plane[2]; /** - * The SURFACE_STATE bits associated with the last fast color clear to this - * color mipmap tree, if any. - * - * Prior to GEN9 there is a single bit for RGBA clear values which gives you - * the option of 2^4 clear colors. Each bit determines if the color channel - * is fully saturated or unsaturated (Cherryview does add a 32b value per - * channel, but it is globally applied instead of being part of the render - * surface state). Starting with GEN9, the surface state accepts a 32b value - * for each color channel. - * - * @see RENDER_SURFACE_STATE.RedClearColor - * @see RENDER_SURFACE_STATE.GreenClearColor - * @see RENDER_SURFACE_STATE.BlueClearColor - * @see RENDER_SURFACE_STATE.AlphaClearColor - */ - union { - uint32_t fast_clear_color_value; - union gl_color_union gen9_fast_clear_color; - }; - - /** - * Disable allocation of auxiliary buffers, such as the HiZ buffer and MCS - * buffer. This is useful for sharing the miptree bo with an external client - * that doesn't understand auxiliary buffers. + * Fast clear color for this surface. For depth surfaces, the clear value + * is stored as a float32 in the red component. */ - bool disable_aux_buffers; - - /** - * Fast clear and lossless compression are always disabled for this - * miptree. - */ - bool no_ccs; - - /** - * Tells if the underlying buffer is to be also consumed by entities other - * than the driver. This allows logic to turn off features such as lossless - * compression which is not currently understood by client applications. - */ - bool is_scanout; + union isl_color_value fast_clear_color; /* These are also refcounted: */ GLuint refcount; }; -void -intel_get_non_msrt_mcs_alignment(const struct intel_mipmap_tree *mt, - unsigned *width_px, unsigned *height); - -bool -intel_miptree_is_lossless_compressed(const struct brw_context *brw, - const struct intel_mipmap_tree *mt); - -bool -intel_tiling_supports_non_msrt_mcs(const struct brw_context *brw, - unsigned tiling); - -bool -intel_miptree_supports_non_msrt_fast_clear(struct brw_context *brw, - const struct intel_mipmap_tree *mt); - bool -intel_miptree_supports_lossless_compressed(struct brw_context *brw, - const struct intel_mipmap_tree *mt); - -bool -intel_miptree_alloc_non_msrt_mcs(struct brw_context *brw, - struct intel_mipmap_tree *mt, - bool is_lossless_compressed); +intel_miptree_alloc_ccs(struct brw_context *brw, + struct intel_mipmap_tree *mt); enum { MIPTREE_LAYOUT_ACCELERATED_UPLOAD = 1 << 0, - MIPTREE_LAYOUT_FORCE_ALL_SLICE_AT_LOD = 1 << 1, + MIPTREE_LAYOUT_GEN6_HIZ_STENCIL = 1 << 1, MIPTREE_LAYOUT_FOR_BO = 1 << 2, MIPTREE_LAYOUT_DISABLE_AUX = 1 << 3, MIPTREE_LAYOUT_FORCE_HALIGN16 = 1 << 4, @@ -711,7 +376,7 @@ struct intel_mipmap_tree *intel_miptree_create(struct brw_context *brw, struct intel_mipmap_tree * intel_miptree_create_for_bo(struct brw_context *brw, - drm_intel_bo *bo, + struct brw_bo *bo, mesa_format format, uint32_t offset, uint32_t width, @@ -720,10 +385,17 @@ intel_miptree_create_for_bo(struct brw_context *brw, int pitch, uint32_t layout_flags); -void +struct intel_mipmap_tree * +intel_miptree_create_for_dri_image(struct brw_context *brw, + __DRIimage *image, + GLenum target, + enum isl_colorspace colorspace, + bool is_winsys_image); + +bool intel_update_winsys_renderbuffer_miptree(struct brw_context *intel, struct intel_renderbuffer *irb, - drm_intel_bo *bo, + struct intel_mipmap_tree *singlesample_mt, uint32_t width, uint32_t height, uint32_t pitch); @@ -748,19 +420,10 @@ mesa_format intel_lower_compressed_format(struct brw_context *brw, mesa_format format); /** \brief Assert that the level and layer are valid for the miptree. */ -static inline void +void intel_miptree_check_level_layer(const struct intel_mipmap_tree *mt, uint32_t level, - uint32_t layer) -{ - (void) mt; - (void) level; - (void) layer; - - assert(level >= mt->first_level); - assert(level <= mt->last_level); - assert(layer < mt->level[level].depth); -} + uint32_t layer); void intel_miptree_reference(struct intel_mipmap_tree **dst, struct intel_mipmap_tree *src); @@ -781,36 +444,23 @@ enum isl_surf_dim get_isl_surf_dim(GLenum target); enum isl_dim_layout -get_isl_dim_layout(const struct gen_device_info *devinfo, uint32_t tiling, - GLenum target); +get_isl_dim_layout(const struct gen_device_info *devinfo, + enum isl_tiling tiling, GLenum target); -enum isl_tiling -intel_miptree_get_isl_tiling(const struct intel_mipmap_tree *mt); - -void -intel_miptree_get_isl_surf(struct brw_context *brw, - const struct intel_mipmap_tree *mt, - struct isl_surf *surf); -void -intel_miptree_get_aux_isl_surf(struct brw_context *brw, - const struct intel_mipmap_tree *mt, - struct isl_surf *surf, - enum isl_aux_usage *usage); - -union isl_color_value -intel_miptree_get_isl_clear_color(struct brw_context *brw, - const struct intel_mipmap_tree *mt); +enum isl_aux_usage +intel_miptree_get_aux_isl_usage(const struct brw_context *brw, + const struct intel_mipmap_tree *mt); void intel_get_image_dims(struct gl_texture_image *image, int *width, int *height, int *depth); void -intel_get_tile_masks(uint32_t tiling, uint32_t tr_mode, uint32_t cpp, +intel_get_tile_masks(enum isl_tiling tiling, uint32_t cpp, uint32_t *mask_x, uint32_t *mask_y); void -intel_get_tile_dims(uint32_t tiling, uint32_t tr_mode, uint32_t cpp, +intel_get_tile_dims(enum isl_tiling tiling, uint32_t cpp, uint32_t *tile_w, uint32_t *tile_h); uint32_t @@ -822,13 +472,12 @@ uint32_t intel_miptree_get_aligned_offset(const struct intel_mipmap_tree *mt, uint32_t x, uint32_t y); -void intel_miptree_set_level_info(struct intel_mipmap_tree *mt, - GLuint level, - GLuint x, GLuint y, GLuint d); - -void intel_miptree_set_image_offset(struct intel_mipmap_tree *mt, - GLuint level, - GLuint img, GLuint x, GLuint y); +void +intel_miptree_copy_slice(struct brw_context *brw, + struct intel_mipmap_tree *src_mt, + unsigned src_level, unsigned src_layer, + struct intel_mipmap_tree *dst_mt, + unsigned dst_level, unsigned dst_layer); void intel_miptree_copy_teximage(struct brw_context *brw, @@ -843,10 +492,6 @@ intel_miptree_copy_teximage(struct brw_context *brw, * functions on a miptree without HiZ. In that case, each function is a no-op. */ -bool -intel_miptree_wants_hiz_buffer(struct brw_context *brw, - struct intel_mipmap_tree *mt); - /** * \brief Allocate the miptree's embedded HiZ miptree. * \see intel_mipmap_tree:hiz_mt @@ -857,99 +502,153 @@ intel_miptree_alloc_hiz(struct brw_context *brw, struct intel_mipmap_tree *mt); bool -intel_miptree_level_has_hiz(struct intel_mipmap_tree *mt, uint32_t level); +intel_miptree_level_has_hiz(const struct intel_mipmap_tree *mt, uint32_t level); -void -intel_miptree_slice_set_needs_hiz_resolve(struct intel_mipmap_tree *mt, - uint32_t level, - uint32_t depth); -void -intel_miptree_slice_set_needs_depth_resolve(struct intel_mipmap_tree *mt, - uint32_t level, - uint32_t depth); - -void -intel_miptree_set_all_slices_need_depth_resolve(struct intel_mipmap_tree *mt, - uint32_t level); +/**\}*/ -/** - * \return false if no resolve was needed - */ bool -intel_miptree_slice_resolve_hiz(struct brw_context *brw, - struct intel_mipmap_tree *mt, - unsigned int level, - unsigned int depth); +intel_miptree_has_color_unresolved(const struct intel_mipmap_tree *mt, + unsigned start_level, unsigned num_levels, + unsigned start_layer, unsigned num_layers); -/** - * \return false if no resolve was needed - */ -bool -intel_miptree_slice_resolve_depth(struct brw_context *brw, - struct intel_mipmap_tree *mt, - unsigned int level, - unsigned int depth); -/** - * \return false if no resolve was needed - */ -bool -intel_miptree_all_slices_resolve_hiz(struct brw_context *brw, - struct intel_mipmap_tree *mt); +#define INTEL_REMAINING_LAYERS UINT32_MAX +#define INTEL_REMAINING_LEVELS UINT32_MAX -/** - * \return false if no resolve was needed +/** Prepare a miptree for access + * + * This function should be called prior to any access to miptree in order to + * perform any needed resolves. + * + * \param[in] start_level The first mip level to be accessed + * + * \param[in] num_levels The number of miplevels to be accessed or + * INTEL_REMAINING_LEVELS to indicate every level + * above start_level will be accessed + * + * \param[in] start_layer The first array slice or 3D layer to be accessed + * + * \param[in] num_layers The number of array slices or 3D layers be + * accessed or INTEL_REMAINING_LAYERS to indicate + * every layer above start_layer will be accessed + * + * \param[in] aux_supported Whether or not the access will support the + * miptree's auxiliary compression format; this + * must be false for uncompressed miptrees + * + * \param[in] fast_clear_supported Whether or not the access will support + * fast clears in the miptree's auxiliary + * compression format */ -bool -intel_miptree_all_slices_resolve_depth(struct brw_context *brw, - struct intel_mipmap_tree *mt); - -/**\}*/ - -enum intel_fast_clear_state -intel_miptree_get_fast_clear_state(const struct intel_mipmap_tree *mt, - unsigned level, unsigned layer); +void +intel_miptree_prepare_access(struct brw_context *brw, + struct intel_mipmap_tree *mt, + uint32_t start_level, uint32_t num_levels, + uint32_t start_layer, uint32_t num_layers, + bool aux_supported, bool fast_clear_supported); +/** Complete a write operation + * + * This function should be called after any operation writes to a miptree. + * This will update the miptree's compression state so that future resolves + * happen correctly. Technically, this function can be called before the + * write occurs but the caller must ensure that they don't interlace + * intel_miptree_prepare_access and intel_miptree_finish_write calls to + * overlapping layer/level ranges. + * + * \param[in] level The mip level that was written + * + * \param[in] start_layer The first array slice or 3D layer written + * + * \param[in] num_layers The number of array slices or 3D layers + * written or INTEL_REMAINING_LAYERS to indicate + * every layer above start_layer was written + * + * \param[in] written_with_aux Whether or not the write was done with + * auxiliary compression enabled + */ void -intel_miptree_set_fast_clear_state(struct intel_mipmap_tree *mt, - unsigned level, - unsigned first_layer, - unsigned num_layers, - enum intel_fast_clear_state new_state); +intel_miptree_finish_write(struct brw_context *brw, + struct intel_mipmap_tree *mt, uint32_t level, + uint32_t start_layer, uint32_t num_layers, + bool written_with_aux); -bool -intel_miptree_has_color_unresolved(const struct intel_mipmap_tree *mt, - unsigned start_level, unsigned num_levels, - unsigned start_layer, unsigned num_layers); +/** Get the auxiliary compression state of a miptree slice */ +enum isl_aux_state +intel_miptree_get_aux_state(const struct intel_mipmap_tree *mt, + uint32_t level, uint32_t layer); -/** - * Update the fast clear state for a miptree to indicate that it has been used - * for rendering. +/** Set the auxiliary compression state of a miptree slice range + * + * This function directly sets the auxiliary compression state of a slice + * range of a miptree. It only modifies data structures and does not do any + * resolves. This should only be called by code which directly performs + * compression operations such as fast clears and resolves. Most code should + * use intel_miptree_prepare_access or intel_miptree_finish_write. */ void -intel_miptree_used_for_rendering(const struct brw_context *brw, - struct intel_mipmap_tree *mt, unsigned level, - unsigned start_layer, unsigned num_layers); +intel_miptree_set_aux_state(struct brw_context *brw, + struct intel_mipmap_tree *mt, uint32_t level, + uint32_t start_layer, uint32_t num_layers, + enum isl_aux_state aux_state); /** - * Flag values telling color resolve pass which special types of buffers - * can be ignored. + * Prepare a miptree for raw access * - * INTEL_MIPTREE_IGNORE_CCS_E: Lossless compressed (single-sample - * compression scheme since gen9) + * This helper prepares the miptree for access that knows nothing about any + * sort of compression whatsoever. This is useful when mapping the surface or + * using it with the blitter. */ -#define INTEL_MIPTREE_IGNORE_CCS_E (1 << 0) - -bool -intel_miptree_resolve_color(struct brw_context *brw, - struct intel_mipmap_tree *mt, unsigned level, - unsigned start_layer, unsigned num_layers, - int flags); +static inline void +intel_miptree_access_raw(struct brw_context *brw, + struct intel_mipmap_tree *mt, + uint32_t level, uint32_t layer, + bool write) +{ + intel_miptree_prepare_access(brw, mt, level, 1, layer, 1, false, false); + if (write) + intel_miptree_finish_write(brw, mt, level, layer, 1, false); +} +enum isl_aux_usage +intel_miptree_texture_aux_usage(struct brw_context *brw, + struct intel_mipmap_tree *mt, + enum isl_format view_format); +void +intel_miptree_prepare_texture(struct brw_context *brw, + struct intel_mipmap_tree *mt, + mesa_format view_format, + bool *aux_supported_out); +void +intel_miptree_prepare_image(struct brw_context *brw, + struct intel_mipmap_tree *mt); +void +intel_miptree_prepare_fb_fetch(struct brw_context *brw, + struct intel_mipmap_tree *mt, uint32_t level, + uint32_t start_layer, uint32_t num_layers); +enum isl_aux_usage +intel_miptree_render_aux_usage(struct brw_context *brw, + struct intel_mipmap_tree *mt, + bool srgb_enabled); void -intel_miptree_all_slices_resolve_color(struct brw_context *brw, - struct intel_mipmap_tree *mt, - int flags); +intel_miptree_prepare_render(struct brw_context *brw, + struct intel_mipmap_tree *mt, uint32_t level, + uint32_t start_layer, uint32_t layer_count, + bool srgb_enabled); +void +intel_miptree_finish_render(struct brw_context *brw, + struct intel_mipmap_tree *mt, uint32_t level, + uint32_t start_layer, uint32_t layer_count, + bool srgb_enabled); +void +intel_miptree_prepare_depth(struct brw_context *brw, + struct intel_mipmap_tree *mt, uint32_t level, + uint32_t start_layer, uint32_t layer_count); +void +intel_miptree_finish_depth(struct brw_context *brw, + struct intel_mipmap_tree *mt, uint32_t level, + uint32_t start_layer, uint32_t layer_count, + bool depth_written); void intel_miptree_make_shareable(struct brw_context *brw, @@ -964,25 +663,7 @@ void intel_update_r8stencil(struct brw_context *brw, struct intel_mipmap_tree *mt); -/** - * Horizontal distance from one slice to the next in the two-dimensional - * miptree layout. - */ -unsigned -brw_miptree_get_horizontal_slice_pitch(const struct brw_context *brw, - const struct intel_mipmap_tree *mt, - unsigned level); - -/** - * Vertical distance from one slice to the next in the two-dimensional miptree - * layout. - */ -unsigned -brw_miptree_get_vertical_slice_pitch(const struct brw_context *brw, - const struct intel_mipmap_tree *mt, - unsigned level); - -void +bool brw_miptree_layout(struct brw_context *brw, struct intel_mipmap_tree *mt, uint32_t layout_flags); @@ -1006,10 +687,6 @@ intel_miptree_unmap(struct brw_context *brw, unsigned int level, unsigned int slice); -void -intel_hiz_exec(struct brw_context *brw, struct intel_mipmap_tree *mt, - unsigned int level, unsigned int layer, enum blorp_hiz_op op); - bool intel_miptree_sample_with_hiz(struct brw_context *brw, struct intel_mipmap_tree *mt);