X-Git-Url: https://git.libre-soc.org/?a=blobdiff_plain;f=src%2Fmesa%2Fdrivers%2Fdri%2Fi965%2Fintel_mipmap_tree.h;h=752aeaaf9b7b7d350620f67ca9c81695be78a4df;hb=248f2e788860240ab84fc10f0d18332c34712b85;hp=50ab0045d4ef5fcb40858545b9912df0aa2a5fae;hpb=641405f7970536d7705e39e8c9bb09e3b0b6b165;p=mesa.git diff --git a/src/mesa/drivers/dri/i965/intel_mipmap_tree.h b/src/mesa/drivers/dri/i965/intel_mipmap_tree.h index 50ab0045d4e..752aeaaf9b7 100644 --- a/src/mesa/drivers/dri/i965/intel_mipmap_tree.h +++ b/src/mesa/drivers/dri/i965/intel_mipmap_tree.h @@ -48,8 +48,9 @@ #include "main/mtypes.h" #include "isl/isl.h" +#include "blorp/blorp.h" #include "brw_bufmgr.h" -#include "intel_resolve_map.h" +#include "brw_context.h" #include #ifdef __cplusplus @@ -59,7 +60,6 @@ extern "C" { struct brw_context; struct intel_renderbuffer; -struct intel_resolve_map; struct intel_texture_image; /** @@ -88,6 +88,12 @@ struct intel_miptree_map { void *ptr; /** Stride of the mapping. */ int stride; + + void (*unmap)(struct brw_context *brw, + struct intel_mipmap_tree *mt, + struct intel_miptree_map *map, + unsigned int level, + unsigned int slice); }; /** @@ -100,21 +106,6 @@ struct intel_mipmap_level /** Offset to this miptree level, used in computing y_offset. */ GLuint level_y; - /** - * \brief Number of 2D slices in this miplevel. - * - * The exact semantics of depth varies according to the texture target: - * - For GL_TEXTURE_CUBE_MAP, depth is 6. - * - For GL_TEXTURE_2D_ARRAY, depth is the number of array slices. It is - * identical for all miplevels in the texture. - * - For GL_TEXTURE_3D, it is the texture's depth at this miplevel. Its - * value, like width and height, varies with miplevel. - * - For other texture types, depth is 1. - * - Additionally, for UMS and CMS miptrees, depth is multiplied by - * sample count. - */ - GLuint depth; - /** * \brief Is HiZ enabled for this level? * @@ -131,26 +122,6 @@ struct intel_mipmap_level * layers in a 3D texture. The list's length is \c depth. */ struct intel_mipmap_slice { - /** - * \name Offset to slice - * \{ - * - * Hardware formats are so diverse that that there is no unified way to - * compute the slice offsets, so we store them in this table. - * - * The (x, y) offset to slice \c s at level \c l relative the miptrees - * base address is - * \code - * x = mt->level[l].slice[s].x_offset - * y = mt->level[l].slice[s].y_offset - * - * On some hardware generations, we program these offsets into - * RENDER_SURFACE_STATE.XOffset and RENDER_SURFACE_STATE.YOffset. - */ - GLuint x_offset; - GLuint y_offset; - /** \} */ - /** * Mapping information. Persistent for the duration of * intel_miptree_map/unmap on this slice. @@ -159,145 +130,6 @@ struct intel_mipmap_level } *slice; }; -/** - * Enum for keeping track of the different MSAA layouts supported by Gen7. - */ -enum intel_msaa_layout -{ - /** - * Ordinary surface with no MSAA. - */ - INTEL_MSAA_LAYOUT_NONE, - - /** - * Interleaved Multisample Surface. The additional samples are - * accommodated by scaling up the width and the height of the surface so - * that all the samples corresponding to a pixel are located at nearby - * memory locations. - * - * @see PRM section "Interleaved Multisampled Surfaces" - */ - INTEL_MSAA_LAYOUT_IMS, - - /** - * Uncompressed Multisample Surface. The surface is stored as a 2D array, - * with array slice n containing all pixel data for sample n. - * - * @see PRM section "Uncompressed Multisampled Surfaces" - */ - INTEL_MSAA_LAYOUT_UMS, - - /** - * Compressed Multisample Surface. The surface is stored as in - * INTEL_MSAA_LAYOUT_UMS, but there is an additional buffer called the MCS - * (Multisample Control Surface) buffer. Each pixel in the MCS buffer - * indicates the mapping from sample number to array slice. This allows - * the common case (where all samples constituting a pixel have the same - * color value) to be stored efficiently by just using a single array - * slice. - * - * @see PRM section "Compressed Multisampled Surfaces" - */ - INTEL_MSAA_LAYOUT_CMS, -}; - -enum miptree_array_layout { - /* Each array slice contains all miplevels packed together. - * - * Gen hardware usually wants multilevel miptrees configured this way. - * - * A 2D Array texture with 2 slices and multiple LODs using - * ALL_LOD_IN_EACH_SLICE would look somewhat like this: - * - * +----------+ - * | | - * | | - * +----------+ - * +---+ +-+ - * | | +-+ - * +---+ * - * +----------+ - * | | - * | | - * +----------+ - * +---+ +-+ - * | | +-+ - * +---+ * - */ - ALL_LOD_IN_EACH_SLICE, - - /* Each LOD contains all slices of that LOD packed together. - * - * In some situations, Gen7+ hardware can use the array_spacing_lod0 - * feature to save space when the surface only contains LOD 0. - * - * Gen6 uses this for separate stencil and hiz since gen6 does not support - * multiple LODs for separate stencil and hiz. - * - * A 2D Array texture with 2 slices and multiple LODs using - * ALL_SLICES_AT_EACH_LOD would look somewhat like this: - * - * +----------+ - * | | - * | | - * +----------+ - * | | - * | | - * +----------+ - * +---+ +-+ - * | | +-+ - * +---+ +-+ - * | | : - * +---+ - */ - ALL_SLICES_AT_EACH_LOD, - - /* On Sandy Bridge, HiZ and stencil buffers work the same as on Ivy Bridge - * except that they don't technically support mipmapping. That does not, - * however, stop us from doing it. As far as Sandy Bridge hardware is - * concerned, HiZ and stencil always operates on a single miplevel 2D - * (possibly array) image. The dimensions of that image are NOT minified. - * - * In order to implement HiZ and stencil on Sandy Bridge, we create one - * full-sized 2D (possibly array) image for every LOD with every image - * aligned to a page boundary. In order to save memory, we pretend that - * the width of each miplevel is minified and we place LOD1 and above below - * LOD0 but horizontally adjacent to each other. When considered as - * full-sized images, LOD1 and above technically overlap. However, since - * we only write to part of that image, the hardware will never notice the - * overlap. - * - * This layout looks something like this: - * - * +---------+ - * | | - * | | - * +---------+ - * | | - * | | - * +---------+ - * - * +----+ +-+ . - * | | +-+ - * +----+ - * - * +----+ +-+ . - * | | +-+ - * +----+ - */ - GEN6_HIZ_STENCIL, -}; - -enum intel_aux_disable { - INTEL_AUX_DISABLE_NONE = 0, - INTEL_AUX_DISABLE_HIZ = 1 << 1, - INTEL_AUX_DISABLE_MCS = 1 << 2, - INTEL_AUX_DISABLE_CCS = 1 << 3, - INTEL_AUX_DISABLE_ALL = INTEL_AUX_DISABLE_HIZ | - INTEL_AUX_DISABLE_MCS | - INTEL_AUX_DISABLE_CCS -}; - /** * Miptree aux buffer. These buffers are associated with a miptree, but the * format is managed by the hardware. @@ -308,6 +140,8 @@ enum intel_aux_disable { */ struct intel_miptree_aux_buffer { + struct isl_surf surf; + /** * Buffer object containing the pixel data. * @@ -328,48 +162,27 @@ struct intel_miptree_aux_buffer */ uint32_t offset; - /* - * Size of the MCS surface. - * - * This is needed when doing any gtt mapped operations on the buffer (which - * will be Y-tiled). It is possible that it will not be the same as bo->size - * when the drm allocator rounds up the requested size. - */ - size_t size; - /** - * Pitch in bytes. + * Buffer object containing the indirect clear color. * - * @see RENDER_SURFACE_STATE.AuxiliarySurfacePitch - * @see 3DSTATE_HIER_DEPTH_BUFFER.SurfacePitch + * @see create_ccs_buf_for_image + * @see RENDER_SURFACE_STATE.ClearValueAddress */ - uint32_t pitch; + struct brw_bo *clear_color_bo; /** - * The distance in rows between array slices. + * Offset into bo where the clear color can be found. * - * @see RENDER_SURFACE_STATE.AuxiliarySurfaceQPitch - * @see 3DSTATE_HIER_DEPTH_BUFFER.SurfaceQPitch - */ - uint32_t qpitch; -}; -/** - * The HiZ buffer requires extra attributes on earlier GENs. This is easily - * contained within an intel_mipmap_tree. To make sure we do not abuse this, we - * keep the hiz datastructure separate. - */ -struct intel_miptree_hiz_buffer -{ - struct intel_miptree_aux_buffer aux_base; - - /** - * Hiz miptree. Used only by Gen6. + * @see create_ccs_buf_for_image + * @see RENDER_SURFACE_STATE.ClearValueAddress */ - struct intel_mipmap_tree *mt; + uint32_t clear_color_offset; }; struct intel_mipmap_tree { + struct isl_surf surf; + /** * Buffer object containing the surface. * @@ -382,25 +195,6 @@ struct intel_mipmap_tree */ struct brw_bo *bo; - /** - * Pitch in bytes. - * - * @see RENDER_SURFACE_STATE.SurfacePitch - * @see RENDER_SURFACE_STATE.AuxiliarySurfacePitch - * @see 3DSTATE_DEPTH_BUFFER.SurfacePitch - * @see 3DSTATE_HIER_DEPTH_BUFFER.SurfacePitch - * @see 3DSTATE_STENCIL_BUFFER.SurfacePitch - */ - uint32_t pitch; - - /** - * One of the I915_TILING_* flags. - * - * @see RENDER_SURFACE_STATE.TileMode - * @see 3DSTATE_DEPTH_BUFFER.TileMode - */ - uint32_t tiling; - /** * @brief One of GL_TEXTURE_2D, GL_TEXTURE_2D_ARRAY, etc. * @@ -436,121 +230,14 @@ struct intel_mipmap_tree */ mesa_format etc_format; - /** - * @name Surface Alignment - * @{ - * - * This defines the alignment of the upperleft pixel of each "slice" in the - * surface. The alignment is in pixel coordinates relative to the surface's - * most upperleft pixel, which is the pixel at (x=0, y=0, layer=0, - * level=0). - * - * The hardware docs do not use the term "slice". We use "slice" to mean - * the pixels at a given miplevel and layer. For 2D surfaces, the layer is - * the array slice; for 3D surfaces, the layer is the z offset. - * - * In the surface layout equations found in the hardware docs, the - * horizontal and vertical surface alignments often appear as variables 'i' - * and 'j'. - */ - - /** @see RENDER_SURFACE_STATE.SurfaceHorizontalAlignment */ - uint32_t halign; - - /** @see RENDER_SURFACE_STATE.SurfaceVerticalAlignment */ - uint32_t valign; - /** @} */ - GLuint first_level; GLuint last_level; - /** - * Level zero image dimensions. These dimensions correspond to the - * physical layout of data in memory. Accordingly, they account for the - * extra width, height, and or depth that must be allocated in order to - * accommodate multisample formats, and they account for the extra factor - * of 6 in depth that must be allocated in order to accommodate cubemap - * textures. - */ - GLuint physical_width0, physical_height0, physical_depth0; - /** Bytes per pixel (or bytes per block if compressed) */ GLuint cpp; - /** - * @see RENDER_SURFACE_STATE.NumberOfMultisamples - * @see 3DSTATE_MULTISAMPLE.NumberOfMultisamples - */ - GLuint num_samples; - bool compressed; - /** - * @name Level zero image dimensions - * @{ - * - * These dimensions correspond to the - * logical width, height, and depth of the texture as seen by client code. - * Accordingly, they do not account for the extra width, height, and/or - * depth that must be allocated in order to accommodate multisample - * formats, nor do they account for the extra factor of 6 in depth that - * must be allocated in order to accommodate cubemap textures. - */ - - /** - * @see RENDER_SURFACE_STATE.Width - * @see 3DSTATE_DEPTH_BUFFER.Width - */ - uint32_t logical_width0; - - /** - * @see RENDER_SURFACE_STATE.Height - * @see 3DSTATE_DEPTH_BUFFER.Height - */ - uint32_t logical_height0; - - /** - * @see RENDER_SURFACE_STATE.Depth - * @see 3DSTATE_DEPTH_BUFFER.Depth - */ - uint32_t logical_depth0; - /** @} */ - - /** - * Indicates if we use the standard miptree layout (ALL_LOD_IN_EACH_SLICE), - * or if we tightly pack array slices at each LOD (ALL_SLICES_AT_EACH_LOD). - */ - enum miptree_array_layout array_layout; - - /** - * The distance in between array slices. - * - * The value is the one that is sent in the surface state. The actual - * meaning depends on certain criteria. Usually it is simply the number of - * uncompressed rows between each slice. However on Gen9+ for compressed - * surfaces it is the number of blocks. For 1D array surfaces that have the - * mipmap tree stored horizontally it is the number of pixels between each - * slice. - * - * @see RENDER_SURFACE_STATE.SurfaceQPitch - * @see 3DSTATE_DEPTH_BUFFER.SurfaceQPitch - * @see 3DSTATE_HIER_DEPTH_BUFFER.SurfaceQPitch - * @see 3DSTATE_STENCIL_BUFFER.SurfaceQPitch - */ - uint32_t qpitch; - - /** - * MSAA layout used by this buffer. - * - * @see RENDER_SURFACE_STATE.MultisampledSurfaceStorageFormat - */ - enum intel_msaa_layout msaa_layout; - - /* Derived from the above: - */ - GLuint total_width; - GLuint total_height; - /* Includes image offset tables: */ struct intel_mipmap_level level[MAX_TEXTURE_LEVELS]; @@ -567,14 +254,23 @@ struct intel_mipmap_tree uint32_t offset; /** - * \brief HiZ aux buffer - * - * To allocate the hiz buffer, use intel_miptree_alloc_hiz(). + * \brief The type of auxiliary compression used by this miptree. * - * To determine if hiz is enabled, do not check this pointer. Instead, use - * intel_miptree_slice_has_hiz(). + * This describes the type of auxiliary compression that is intended to be + * used by this miptree. An aux usage of ISL_AUX_USAGE_NONE means that + * auxiliary compression is permanently disabled. An aux usage other than + * ISL_AUX_USAGE_NONE does not imply that the auxiliary buffer has actually + * been allocated nor does it imply that auxiliary compression will always + * be enabled for this surface. For instance, with CCS_D, we may allocate + * the CCS on-the-fly and it may not be used for texturing if the miptree + * is fully resolved. */ - struct intel_miptree_hiz_buffer *hiz_buf; + enum isl_aux_usage aux_usage; + + /** + * \brief Whether or not this miptree supports fast clears. + */ + bool supports_fast_clear; /** * \brief Maps miptree slices to their current aux state @@ -598,27 +294,43 @@ struct intel_mipmap_tree struct intel_mipmap_tree *stencil_mt; /** - * \brief Stencil texturing miptree for sampling from a stencil texture + * \brief Shadow miptree for sampling when the main isn't supported by HW. * - * Some hardware doesn't support sampling from the stencil texture as - * required by the GL_ARB_stencil_texturing extenion. To workaround this we - * blit the texture into a new texture that can be sampled. + * To workaround various sampler bugs and limitations, we blit the main + * texture into a new texture that can be sampled. * - * \see intel_update_r8stencil() + * This miptree may be used for: + * - Stencil texturing (pre-BDW) as required by GL_ARB_stencil_texturing. + * - To store the decompressed ETC/EAC data in case we emulate the ETC + * compression on Gen 7 or earlier GPUs. */ - struct intel_mipmap_tree *r8stencil_mt; - bool r8stencil_needs_update; + struct intel_mipmap_tree *shadow_mt; + bool shadow_needs_update; /** - * \brief MCS auxiliary buffer. + * \brief CCS, MCS, or HiZ auxiliary buffer. + * + * NULL if no auxiliary buffer is in use for this surface. + * + * For single-sampled color miptrees: + * This buffer contains the Color Control Surface, which stores the + * necessary information to implement lossless color compression (CCS_E) + * and "fast color clear" (CCS_D) behaviour. + * + * For multi-sampled color miptrees: + * This buffer contains the Multisample Control Surface, which stores the + * necessary information to implement compressed MSAA + * (INTEL_MSAA_FORMAT_CMS). * - * This buffer contains the "multisample control surface", which stores - * the necessary information to implement compressed MSAA - * (INTEL_MSAA_FORMAT_CMS) and "fast color clear" behaviour on Gen7+. + * For depth miptrees: + * This buffer contains the Hierarchical Depth Buffer, which stores the + * necessary information to implement lossless depth compression and fast + * depth clear behavior. * - * NULL if no MCS buffer is in use for this surface. + * To determine if HiZ is enabled, do not check this pointer. Instead, + * use intel_miptree_level_has_hiz(). */ - struct intel_miptree_aux_buffer *mcs_buf; + struct intel_miptree_aux_buffer *aux_buf; /** * Planes 1 and 2 in case this is a planar surface. @@ -632,18 +344,11 @@ struct intel_mipmap_tree union isl_color_value fast_clear_color; /** - * Disable allocation of auxiliary buffers, such as the HiZ buffer and MCS - * buffer. This is useful for sharing the miptree bo with an external client - * that doesn't understand auxiliary buffers. + * For external surfaces, this is DRM format modifier that was used to + * create or import the surface. For internal surfaces, this will always + * be DRM_FORMAT_MOD_INVALID. */ - enum intel_aux_disable aux_disable; - - /** - * Tells if the underlying buffer is to be also consumed by entities other - * than the driver. This allows logic to turn off features such as lossless - * compression which is not currently understood by client applications. - */ - bool is_scanout; + uint64_t drm_modifier; /* These are also refcounted: */ @@ -651,39 +356,29 @@ struct intel_mipmap_tree }; bool -intel_miptree_is_lossless_compressed(const struct brw_context *brw, - const struct intel_mipmap_tree *mt); +intel_miptree_alloc_aux(struct brw_context *brw, + struct intel_mipmap_tree *mt); -bool -intel_tiling_supports_non_msrt_mcs(const struct brw_context *brw, - unsigned tiling); - -bool -intel_miptree_supports_non_msrt_fast_clear(struct brw_context *brw, - const struct intel_mipmap_tree *mt); +enum intel_miptree_create_flags { + /** No miptree create flags */ + MIPTREE_CREATE_DEFAULT = 0, -bool -intel_miptree_supports_lossless_compressed(struct brw_context *brw, - const struct intel_mipmap_tree *mt); + /** Miptree creation should try to allocate a currently busy BO + * + * This may be advantageous if we know the next thing to touch the BO will + * be the GPU because the BO will likely already be in the GTT and maybe + * even in some caches. If there is a chance that the next thing to touch + * the miptree BO will be the CPU, this flag should not be set. + */ + MIPTREE_CREATE_BUSY = 1 << 0, -bool -intel_miptree_alloc_non_msrt_mcs(struct brw_context *brw, - struct intel_mipmap_tree *mt, - bool is_lossless_compressed); - -enum { - MIPTREE_LAYOUT_ACCELERATED_UPLOAD = 1 << 0, - MIPTREE_LAYOUT_GEN6_HIZ_STENCIL = 1 << 1, - MIPTREE_LAYOUT_FOR_BO = 1 << 2, - MIPTREE_LAYOUT_DISABLE_AUX = 1 << 3, - MIPTREE_LAYOUT_FORCE_HALIGN16 = 1 << 4, - - MIPTREE_LAYOUT_TILING_Y = 1 << 5, - MIPTREE_LAYOUT_TILING_NONE = 1 << 6, - MIPTREE_LAYOUT_TILING_ANY = MIPTREE_LAYOUT_TILING_Y | - MIPTREE_LAYOUT_TILING_NONE, - - MIPTREE_LAYOUT_FOR_SCANOUT = 1 << 7, + /** Create the miptree with auxiliary compression disabled + * + * This does not prevent the caller of intel_miptree_create from coming + * along later and turning auxiliary compression back on but it does mean + * that the miptree will be created with mt->aux_usage == NONE. + */ + MIPTREE_CREATE_NO_AUX = 1 << 1, }; struct intel_mipmap_tree *intel_miptree_create(struct brw_context *brw, @@ -695,7 +390,7 @@ struct intel_mipmap_tree *intel_miptree_create(struct brw_context *brw, GLuint height0, GLuint depth0, GLuint num_samples, - uint32_t flags); + enum intel_miptree_create_flags flags); struct intel_mipmap_tree * intel_miptree_create_for_bo(struct brw_context *brw, @@ -706,12 +401,20 @@ intel_miptree_create_for_bo(struct brw_context *brw, uint32_t height, uint32_t depth, int pitch, - uint32_t layout_flags); + enum isl_tiling tiling, + enum intel_miptree_create_flags flags); -void +struct intel_mipmap_tree * +intel_miptree_create_for_dri_image(struct brw_context *brw, + __DRIimage *image, + GLenum target, + mesa_format format, + bool allow_internal_aux); + +bool intel_update_winsys_renderbuffer_miptree(struct brw_context *intel, struct intel_renderbuffer *irb, - struct brw_bo *bo, + struct intel_mipmap_tree *singlesample_mt, uint32_t width, uint32_t height, uint32_t pitch); @@ -735,20 +438,14 @@ intel_depth_format_for_depthstencil_format(mesa_format format); mesa_format intel_lower_compressed_format(struct brw_context *brw, mesa_format format); +unsigned +brw_get_num_logical_layers(const struct intel_mipmap_tree *mt, unsigned level); + /** \brief Assert that the level and layer are valid for the miptree. */ -static inline void +void intel_miptree_check_level_layer(const struct intel_mipmap_tree *mt, uint32_t level, - uint32_t layer) -{ - (void) mt; - (void) level; - (void) layer; - - assert(level >= mt->first_level); - assert(level <= mt->last_level); - assert(layer < mt->level[level].depth); -} + uint32_t layer); void intel_miptree_reference(struct intel_mipmap_tree **dst, struct intel_mipmap_tree *src); @@ -769,32 +466,19 @@ enum isl_surf_dim get_isl_surf_dim(GLenum target); enum isl_dim_layout -get_isl_dim_layout(const struct gen_device_info *devinfo, uint32_t tiling, - GLenum target, enum miptree_array_layout array_layout); - -enum isl_tiling -intel_miptree_get_isl_tiling(const struct intel_mipmap_tree *mt); - -void -intel_miptree_get_isl_surf(struct brw_context *brw, - const struct intel_mipmap_tree *mt, - struct isl_surf *surf); -void -intel_miptree_get_aux_isl_surf(struct brw_context *brw, - const struct intel_mipmap_tree *mt, - struct isl_surf *surf, - enum isl_aux_usage *usage); +get_isl_dim_layout(const struct gen_device_info *devinfo, + enum isl_tiling tiling, GLenum target); void intel_get_image_dims(struct gl_texture_image *image, int *width, int *height, int *depth); void -intel_get_tile_masks(uint32_t tiling, uint32_t cpp, +intel_get_tile_masks(enum isl_tiling tiling, uint32_t cpp, uint32_t *mask_x, uint32_t *mask_y); void -intel_get_tile_dims(uint32_t tiling, uint32_t cpp, +intel_get_tile_dims(enum isl_tiling tiling, uint32_t cpp, uint32_t *tile_w, uint32_t *tile_h); uint32_t @@ -806,18 +490,17 @@ uint32_t intel_miptree_get_aligned_offset(const struct intel_mipmap_tree *mt, uint32_t x, uint32_t y); -void intel_miptree_set_level_info(struct intel_mipmap_tree *mt, - GLuint level, - GLuint x, GLuint y, GLuint d); - -void intel_miptree_set_image_offset(struct intel_mipmap_tree *mt, - GLuint level, - GLuint img, GLuint x, GLuint y); +void +intel_miptree_copy_slice(struct brw_context *brw, + struct intel_mipmap_tree *src_mt, + unsigned src_level, unsigned src_layer, + struct intel_mipmap_tree *dst_mt, + unsigned dst_level, unsigned dst_layer); void intel_miptree_copy_teximage(struct brw_context *brw, struct intel_texture_image *intelImage, - struct intel_mipmap_tree *dst_mt, bool invalidate); + struct intel_mipmap_tree *dst_mt); /** * \name Miptree HiZ functions @@ -827,19 +510,6 @@ intel_miptree_copy_teximage(struct brw_context *brw, * functions on a miptree without HiZ. In that case, each function is a no-op. */ -bool -intel_miptree_wants_hiz_buffer(struct brw_context *brw, - struct intel_mipmap_tree *mt); - -/** - * \brief Allocate the miptree's embedded HiZ miptree. - * \see intel_mipmap_tree:hiz_mt - * \return false if allocation failed - */ -bool -intel_miptree_alloc_hiz(struct brw_context *brw, - struct intel_mipmap_tree *mt); - bool intel_miptree_level_has_hiz(const struct intel_mipmap_tree *mt, uint32_t level); @@ -884,7 +554,8 @@ intel_miptree_prepare_access(struct brw_context *brw, struct intel_mipmap_tree *mt, uint32_t start_level, uint32_t num_levels, uint32_t start_layer, uint32_t num_layers, - bool aux_supported, bool fast_clear_supported); + enum isl_aux_usage aux_usage, + bool fast_clear_supported); /** Complete a write operation * @@ -910,7 +581,7 @@ void intel_miptree_finish_write(struct brw_context *brw, struct intel_mipmap_tree *mt, uint32_t level, uint32_t start_layer, uint32_t num_layers, - bool written_with_aux); + enum isl_aux_usage aux_usage); /** Get the auxiliary compression state of a miptree slice */ enum isl_aux_state @@ -944,32 +615,44 @@ intel_miptree_access_raw(struct brw_context *brw, uint32_t level, uint32_t layer, bool write) { - intel_miptree_prepare_access(brw, mt, level, 1, layer, 1, false, false); + intel_miptree_prepare_access(brw, mt, level, 1, layer, 1, + ISL_AUX_USAGE_NONE, false); if (write) - intel_miptree_finish_write(brw, mt, level, layer, 1, false); + intel_miptree_finish_write(brw, mt, level, layer, 1, ISL_AUX_USAGE_NONE); } +enum isl_aux_usage +intel_miptree_texture_aux_usage(struct brw_context *brw, + struct intel_mipmap_tree *mt, + enum isl_format view_format, + enum gen9_astc5x5_wa_tex_type astc5x5_wa_bits); void intel_miptree_prepare_texture(struct brw_context *brw, struct intel_mipmap_tree *mt, - mesa_format view_format, - bool *aux_supported_out); + enum isl_format view_format, + uint32_t start_level, uint32_t num_levels, + uint32_t start_layer, uint32_t num_layers, + enum gen9_astc5x5_wa_tex_type astc5x5_wa_bits); void intel_miptree_prepare_image(struct brw_context *brw, struct intel_mipmap_tree *mt); -void -intel_miptree_prepare_fb_fetch(struct brw_context *brw, - struct intel_mipmap_tree *mt, uint32_t level, - uint32_t start_layer, uint32_t num_layers); + +enum isl_aux_usage +intel_miptree_render_aux_usage(struct brw_context *brw, + struct intel_mipmap_tree *mt, + enum isl_format render_format, + bool blend_enabled, + bool draw_aux_disabled); void intel_miptree_prepare_render(struct brw_context *brw, struct intel_mipmap_tree *mt, uint32_t level, uint32_t start_layer, uint32_t layer_count, - bool srgb_enabled); + enum isl_aux_usage aux_usage); void intel_miptree_finish_render(struct brw_context *brw, struct intel_mipmap_tree *mt, uint32_t level, - uint32_t start_layer, uint32_t layer_count); + uint32_t start_layer, uint32_t layer_count, + enum isl_aux_usage aux_usage); void intel_miptree_prepare_depth(struct brw_context *brw, struct intel_mipmap_tree *mt, uint32_t level, @@ -979,6 +662,12 @@ intel_miptree_finish_depth(struct brw_context *brw, struct intel_mipmap_tree *mt, uint32_t level, uint32_t start_layer, uint32_t layer_count, bool depth_written); +void +intel_miptree_prepare_external(struct brw_context *brw, + struct intel_mipmap_tree *mt); +void +intel_miptree_finish_external(struct brw_context *brw, + struct intel_mipmap_tree *mt); void intel_miptree_make_shareable(struct brw_context *brw, @@ -993,29 +682,6 @@ void intel_update_r8stencil(struct brw_context *brw, struct intel_mipmap_tree *mt); -/** - * Horizontal distance from one slice to the next in the two-dimensional - * miptree layout. - */ -unsigned -brw_miptree_get_horizontal_slice_pitch(const struct brw_context *brw, - const struct intel_mipmap_tree *mt, - unsigned level); - -/** - * Vertical distance from one slice to the next in the two-dimensional miptree - * layout. - */ -unsigned -brw_miptree_get_vertical_slice_pitch(const struct brw_context *brw, - const struct intel_mipmap_tree *mt, - unsigned level); - -bool -brw_miptree_layout(struct brw_context *brw, - struct intel_mipmap_tree *mt, - uint32_t layout_flags); - void intel_miptree_map(struct brw_context *brw, struct intel_mipmap_tree *mt, @@ -1039,6 +705,55 @@ bool intel_miptree_sample_with_hiz(struct brw_context *brw, struct intel_mipmap_tree *mt); +bool +intel_miptree_set_clear_color(struct brw_context *brw, + struct intel_mipmap_tree *mt, + union isl_color_value clear_color); + +/* Get a clear color suitable for filling out an ISL surface state. */ +union isl_color_value +intel_miptree_get_clear_color(const struct gen_device_info *devinfo, + const struct intel_mipmap_tree *mt, + enum isl_format view_format, bool sampling, + struct brw_bo **clear_color_bo, + uint64_t *clear_color_offset); + + +static inline int +intel_miptree_blt_pitch(struct intel_mipmap_tree *mt) +{ + int pitch = mt->surf.row_pitch_B; + if (mt->surf.tiling != ISL_TILING_LINEAR) + pitch /= 4; + return pitch; +} + +isl_memcpy_type +intel_miptree_get_memcpy_type(mesa_format tiledFormat, GLenum format, GLenum type, + uint32_t *cpp); + +static inline bool +intel_miptree_needs_fake_etc(struct brw_context *brw, + struct intel_mipmap_tree *mt) +{ + const struct gen_device_info *devinfo = &brw->screen->devinfo; + bool is_etc = _mesa_is_format_etc2(mt->format) || + (mt->format == MESA_FORMAT_ETC1_RGB8); + + return devinfo->gen < 8 && !devinfo->is_baytrail && is_etc; +} + +static inline bool +intel_miptree_has_etc_shadow(struct brw_context *brw, + struct intel_mipmap_tree *mt) +{ + return intel_miptree_needs_fake_etc(brw, mt) && mt->shadow_mt; +} + +void +intel_miptree_update_etc_shadow_levels(struct brw_context *brw, + struct intel_mipmap_tree *mt); + #ifdef __cplusplus } #endif