X-Git-Url: https://git.libre-soc.org/?a=blobdiff_plain;f=src%2Fmesa%2Fdrivers%2Fdri%2Fi965%2Fintel_mipmap_tree.h;h=752aeaaf9b7b7d350620f67ca9c81695be78a4df;hb=248f2e788860240ab84fc10f0d18332c34712b85;hp=fbb6b9cd83fad819cc6f5e2f0ea6a2d3faaef6b5;hpb=c9314d2c4684682af9f8abd06fa017a0cec3cf87;p=mesa.git diff --git a/src/mesa/drivers/dri/i965/intel_mipmap_tree.h b/src/mesa/drivers/dri/i965/intel_mipmap_tree.h index fbb6b9cd83f..752aeaaf9b7 100644 --- a/src/mesa/drivers/dri/i965/intel_mipmap_tree.h +++ b/src/mesa/drivers/dri/i965/intel_mipmap_tree.h @@ -50,6 +50,7 @@ #include "isl/isl.h" #include "blorp/blorp.h" #include "brw_bufmgr.h" +#include "brw_context.h" #include #ifdef __cplusplus @@ -87,6 +88,12 @@ struct intel_miptree_map { void *ptr; /** Stride of the mapping. */ int stride; + + void (*unmap)(struct brw_context *brw, + struct intel_mipmap_tree *mt, + struct intel_miptree_map *map, + unsigned int level, + unsigned int slice); }; /** @@ -155,30 +162,21 @@ struct intel_miptree_aux_buffer */ uint32_t offset; - /* - * Size of the MCS surface. - * - * This is needed when doing any gtt mapped operations on the buffer (which - * will be Y-tiled). It is possible that it will not be the same as bo->size - * when the drm allocator rounds up the requested size. - */ - size_t size; - /** - * Pitch in bytes. + * Buffer object containing the indirect clear color. * - * @see RENDER_SURFACE_STATE.AuxiliarySurfacePitch - * @see 3DSTATE_HIER_DEPTH_BUFFER.SurfacePitch + * @see create_ccs_buf_for_image + * @see RENDER_SURFACE_STATE.ClearValueAddress */ - uint32_t pitch; + struct brw_bo *clear_color_bo; /** - * The distance in rows between array slices. + * Offset into bo where the clear color can be found. * - * @see RENDER_SURFACE_STATE.AuxiliarySurfaceQPitch - * @see 3DSTATE_HIER_DEPTH_BUFFER.SurfaceQPitch + * @see create_ccs_buf_for_image + * @see RENDER_SURFACE_STATE.ClearValueAddress */ - uint32_t qpitch; + uint32_t clear_color_offset; }; struct intel_mipmap_tree @@ -255,16 +253,6 @@ struct intel_mipmap_tree */ uint32_t offset; - /** - * \brief HiZ aux buffer - * - * To allocate the hiz buffer, use intel_miptree_alloc_hiz(). - * - * To determine if hiz is enabled, do not check this pointer. Instead, use - * intel_miptree_level_has_hiz(). - */ - struct intel_miptree_aux_buffer *hiz_buf; - /** * \brief The type of auxiliary compression used by this miptree. * @@ -306,27 +294,43 @@ struct intel_mipmap_tree struct intel_mipmap_tree *stencil_mt; /** - * \brief Stencil texturing miptree for sampling from a stencil texture + * \brief Shadow miptree for sampling when the main isn't supported by HW. * - * Some hardware doesn't support sampling from the stencil texture as - * required by the GL_ARB_stencil_texturing extenion. To workaround this we - * blit the texture into a new texture that can be sampled. + * To workaround various sampler bugs and limitations, we blit the main + * texture into a new texture that can be sampled. * - * \see intel_update_r8stencil() + * This miptree may be used for: + * - Stencil texturing (pre-BDW) as required by GL_ARB_stencil_texturing. + * - To store the decompressed ETC/EAC data in case we emulate the ETC + * compression on Gen 7 or earlier GPUs. */ - struct intel_mipmap_tree *r8stencil_mt; - bool r8stencil_needs_update; + struct intel_mipmap_tree *shadow_mt; + bool shadow_needs_update; /** - * \brief MCS auxiliary buffer. + * \brief CCS, MCS, or HiZ auxiliary buffer. + * + * NULL if no auxiliary buffer is in use for this surface. + * + * For single-sampled color miptrees: + * This buffer contains the Color Control Surface, which stores the + * necessary information to implement lossless color compression (CCS_E) + * and "fast color clear" (CCS_D) behaviour. * - * This buffer contains the "multisample control surface", which stores - * the necessary information to implement compressed MSAA - * (INTEL_MSAA_FORMAT_CMS) and "fast color clear" behaviour on Gen7+. + * For multi-sampled color miptrees: + * This buffer contains the Multisample Control Surface, which stores the + * necessary information to implement compressed MSAA + * (INTEL_MSAA_FORMAT_CMS). * - * NULL if no MCS buffer is in use for this surface. + * For depth miptrees: + * This buffer contains the Hierarchical Depth Buffer, which stores the + * necessary information to implement lossless depth compression and fast + * depth clear behavior. + * + * To determine if HiZ is enabled, do not check this pointer. Instead, + * use intel_miptree_level_has_hiz(). */ - struct intel_miptree_aux_buffer *mcs_buf; + struct intel_miptree_aux_buffer *aux_buf; /** * Planes 1 and 2 in case this is a planar surface. @@ -339,28 +343,42 @@ struct intel_mipmap_tree */ union isl_color_value fast_clear_color; + /** + * For external surfaces, this is DRM format modifier that was used to + * create or import the surface. For internal surfaces, this will always + * be DRM_FORMAT_MOD_INVALID. + */ + uint64_t drm_modifier; + /* These are also refcounted: */ GLuint refcount; }; bool -intel_miptree_alloc_ccs(struct brw_context *brw, +intel_miptree_alloc_aux(struct brw_context *brw, struct intel_mipmap_tree *mt); -enum { - MIPTREE_LAYOUT_ACCELERATED_UPLOAD = 1 << 0, - MIPTREE_LAYOUT_GEN6_HIZ_STENCIL = 1 << 1, - MIPTREE_LAYOUT_FOR_BO = 1 << 2, - MIPTREE_LAYOUT_DISABLE_AUX = 1 << 3, - MIPTREE_LAYOUT_FORCE_HALIGN16 = 1 << 4, +enum intel_miptree_create_flags { + /** No miptree create flags */ + MIPTREE_CREATE_DEFAULT = 0, - MIPTREE_LAYOUT_TILING_Y = 1 << 5, - MIPTREE_LAYOUT_TILING_NONE = 1 << 6, - MIPTREE_LAYOUT_TILING_ANY = MIPTREE_LAYOUT_TILING_Y | - MIPTREE_LAYOUT_TILING_NONE, + /** Miptree creation should try to allocate a currently busy BO + * + * This may be advantageous if we know the next thing to touch the BO will + * be the GPU because the BO will likely already be in the GTT and maybe + * even in some caches. If there is a chance that the next thing to touch + * the miptree BO will be the CPU, this flag should not be set. + */ + MIPTREE_CREATE_BUSY = 1 << 0, - MIPTREE_LAYOUT_FOR_SCANOUT = 1 << 7, + /** Create the miptree with auxiliary compression disabled + * + * This does not prevent the caller of intel_miptree_create from coming + * along later and turning auxiliary compression back on but it does mean + * that the miptree will be created with mt->aux_usage == NONE. + */ + MIPTREE_CREATE_NO_AUX = 1 << 1, }; struct intel_mipmap_tree *intel_miptree_create(struct brw_context *brw, @@ -372,7 +390,7 @@ struct intel_mipmap_tree *intel_miptree_create(struct brw_context *brw, GLuint height0, GLuint depth0, GLuint num_samples, - uint32_t flags); + enum intel_miptree_create_flags flags); struct intel_mipmap_tree * intel_miptree_create_for_bo(struct brw_context *brw, @@ -383,14 +401,15 @@ intel_miptree_create_for_bo(struct brw_context *brw, uint32_t height, uint32_t depth, int pitch, - uint32_t layout_flags); + enum isl_tiling tiling, + enum intel_miptree_create_flags flags); struct intel_mipmap_tree * intel_miptree_create_for_dri_image(struct brw_context *brw, __DRIimage *image, GLenum target, - enum isl_colorspace colorspace, - bool is_winsys_image); + mesa_format format, + bool allow_internal_aux); bool intel_update_winsys_renderbuffer_miptree(struct brw_context *intel, @@ -419,6 +438,9 @@ intel_depth_format_for_depthstencil_format(mesa_format format); mesa_format intel_lower_compressed_format(struct brw_context *brw, mesa_format format); +unsigned +brw_get_num_logical_layers(const struct intel_mipmap_tree *mt, unsigned level); + /** \brief Assert that the level and layer are valid for the miptree. */ void intel_miptree_check_level_layer(const struct intel_mipmap_tree *mt, @@ -447,10 +469,6 @@ enum isl_dim_layout get_isl_dim_layout(const struct gen_device_info *devinfo, enum isl_tiling tiling, GLenum target); -enum isl_aux_usage -intel_miptree_get_aux_isl_usage(const struct brw_context *brw, - const struct intel_mipmap_tree *mt); - void intel_get_image_dims(struct gl_texture_image *image, int *width, int *height, int *depth); @@ -482,7 +500,7 @@ intel_miptree_copy_slice(struct brw_context *brw, void intel_miptree_copy_teximage(struct brw_context *brw, struct intel_texture_image *intelImage, - struct intel_mipmap_tree *dst_mt, bool invalidate); + struct intel_mipmap_tree *dst_mt); /** * \name Miptree HiZ functions @@ -492,15 +510,6 @@ intel_miptree_copy_teximage(struct brw_context *brw, * functions on a miptree without HiZ. In that case, each function is a no-op. */ -/** - * \brief Allocate the miptree's embedded HiZ miptree. - * \see intel_mipmap_tree:hiz_mt - * \return false if allocation failed - */ -bool -intel_miptree_alloc_hiz(struct brw_context *brw, - struct intel_mipmap_tree *mt); - bool intel_miptree_level_has_hiz(const struct intel_mipmap_tree *mt, uint32_t level); @@ -545,7 +554,8 @@ intel_miptree_prepare_access(struct brw_context *brw, struct intel_mipmap_tree *mt, uint32_t start_level, uint32_t num_levels, uint32_t start_layer, uint32_t num_layers, - bool aux_supported, bool fast_clear_supported); + enum isl_aux_usage aux_usage, + bool fast_clear_supported); /** Complete a write operation * @@ -571,7 +581,7 @@ void intel_miptree_finish_write(struct brw_context *brw, struct intel_mipmap_tree *mt, uint32_t level, uint32_t start_layer, uint32_t num_layers, - bool written_with_aux); + enum isl_aux_usage aux_usage); /** Get the auxiliary compression state of a miptree slice */ enum isl_aux_state @@ -605,36 +615,44 @@ intel_miptree_access_raw(struct brw_context *brw, uint32_t level, uint32_t layer, bool write) { - intel_miptree_prepare_access(brw, mt, level, 1, layer, 1, false, false); + intel_miptree_prepare_access(brw, mt, level, 1, layer, 1, + ISL_AUX_USAGE_NONE, false); if (write) - intel_miptree_finish_write(brw, mt, level, layer, 1, false); + intel_miptree_finish_write(brw, mt, level, layer, 1, ISL_AUX_USAGE_NONE); } enum isl_aux_usage intel_miptree_texture_aux_usage(struct brw_context *brw, struct intel_mipmap_tree *mt, - enum isl_format view_format); + enum isl_format view_format, + enum gen9_astc5x5_wa_tex_type astc5x5_wa_bits); void intel_miptree_prepare_texture(struct brw_context *brw, struct intel_mipmap_tree *mt, - mesa_format view_format, - bool *aux_supported_out); + enum isl_format view_format, + uint32_t start_level, uint32_t num_levels, + uint32_t start_layer, uint32_t num_layers, + enum gen9_astc5x5_wa_tex_type astc5x5_wa_bits); void intel_miptree_prepare_image(struct brw_context *brw, struct intel_mipmap_tree *mt); -void -intel_miptree_prepare_fb_fetch(struct brw_context *brw, - struct intel_mipmap_tree *mt, uint32_t level, - uint32_t start_layer, uint32_t num_layers); + +enum isl_aux_usage +intel_miptree_render_aux_usage(struct brw_context *brw, + struct intel_mipmap_tree *mt, + enum isl_format render_format, + bool blend_enabled, + bool draw_aux_disabled); void intel_miptree_prepare_render(struct brw_context *brw, struct intel_mipmap_tree *mt, uint32_t level, uint32_t start_layer, uint32_t layer_count, - bool srgb_enabled); + enum isl_aux_usage aux_usage); void intel_miptree_finish_render(struct brw_context *brw, struct intel_mipmap_tree *mt, uint32_t level, - uint32_t start_layer, uint32_t layer_count); + uint32_t start_layer, uint32_t layer_count, + enum isl_aux_usage aux_usage); void intel_miptree_prepare_depth(struct brw_context *brw, struct intel_mipmap_tree *mt, uint32_t level, @@ -644,6 +662,12 @@ intel_miptree_finish_depth(struct brw_context *brw, struct intel_mipmap_tree *mt, uint32_t level, uint32_t start_layer, uint32_t layer_count, bool depth_written); +void +intel_miptree_prepare_external(struct brw_context *brw, + struct intel_mipmap_tree *mt); +void +intel_miptree_finish_external(struct brw_context *brw, + struct intel_mipmap_tree *mt); void intel_miptree_make_shareable(struct brw_context *brw, @@ -658,11 +682,6 @@ void intel_update_r8stencil(struct brw_context *brw, struct intel_mipmap_tree *mt); -bool -brw_miptree_layout(struct brw_context *brw, - struct intel_mipmap_tree *mt, - uint32_t layout_flags); - void intel_miptree_map(struct brw_context *brw, struct intel_mipmap_tree *mt, @@ -686,6 +705,55 @@ bool intel_miptree_sample_with_hiz(struct brw_context *brw, struct intel_mipmap_tree *mt); +bool +intel_miptree_set_clear_color(struct brw_context *brw, + struct intel_mipmap_tree *mt, + union isl_color_value clear_color); + +/* Get a clear color suitable for filling out an ISL surface state. */ +union isl_color_value +intel_miptree_get_clear_color(const struct gen_device_info *devinfo, + const struct intel_mipmap_tree *mt, + enum isl_format view_format, bool sampling, + struct brw_bo **clear_color_bo, + uint64_t *clear_color_offset); + + +static inline int +intel_miptree_blt_pitch(struct intel_mipmap_tree *mt) +{ + int pitch = mt->surf.row_pitch_B; + if (mt->surf.tiling != ISL_TILING_LINEAR) + pitch /= 4; + return pitch; +} + +isl_memcpy_type +intel_miptree_get_memcpy_type(mesa_format tiledFormat, GLenum format, GLenum type, + uint32_t *cpp); + +static inline bool +intel_miptree_needs_fake_etc(struct brw_context *brw, + struct intel_mipmap_tree *mt) +{ + const struct gen_device_info *devinfo = &brw->screen->devinfo; + bool is_etc = _mesa_is_format_etc2(mt->format) || + (mt->format == MESA_FORMAT_ETC1_RGB8); + + return devinfo->gen < 8 && !devinfo->is_baytrail && is_etc; +} + +static inline bool +intel_miptree_has_etc_shadow(struct brw_context *brw, + struct intel_mipmap_tree *mt) +{ + return intel_miptree_needs_fake_etc(brw, mt) && mt->shadow_mt; +} + +void +intel_miptree_update_etc_shadow_levels(struct brw_context *brw, + struct intel_mipmap_tree *mt); + #ifdef __cplusplus } #endif