X-Git-Url: https://git.libre-soc.org/?a=blobdiff_plain;f=src%2Fmesa%2Fdrivers%2Fdri%2Fi965%2Fintel_screen.c;h=5911b44445492ed234649dc82208a19ba5257fc4;hb=9b387b5d3f4103c51079ea5298d33086af6da433;hp=34bda9f9a35df254b7213d9abb0810846cc6b802;hpb=9ac9d133ed3d675a0c4cb527fb643ca590fe7d78;p=mesa.git diff --git a/src/mesa/drivers/dri/i965/intel_screen.c b/src/mesa/drivers/dri/i965/intel_screen.c index 34bda9f9a35..5911b444454 100644 --- a/src/mesa/drivers/dri/i965/intel_screen.c +++ b/src/mesa/drivers/dri/i965/intel_screen.c @@ -37,6 +37,9 @@ #include "main/fbobject.h" #include "main/version.h" #include "swrast/s_renderbuffer.h" +#include "util/ralloc.h" +#include "brw_shader.h" +#include "glsl/nir/nir.h" #include "utils.h" #include "xmlpool.h" @@ -60,10 +63,6 @@ DRI_CONF_BEGIN DRI_CONF_OPT_BEGIN_B(hiz, "true") DRI_CONF_DESC(en, "Enable Hierarchical Z on gen6+") DRI_CONF_OPT_END - - DRI_CONF_OPT_BEGIN_B(disable_derivative_optimization, "false") - DRI_CONF_DESC(en, "Derivatives with finer granularity by default") - DRI_CONF_OPT_END DRI_CONF_SECTION_END DRI_CONF_SECTION_QUALITY @@ -83,6 +82,7 @@ DRI_CONF_BEGIN DRI_CONF_FORCE_GLSL_EXTENSIONS_WARN("false") DRI_CONF_DISABLE_GLSL_LINE_CONTINUATIONS("false") DRI_CONF_DISABLE_BLEND_FUNC_EXTENDED("false") + DRI_CONF_ALLOW_GLSL_EXTENSION_DIRECTIVE_MIDSHADER("false") DRI_CONF_OPT_BEGIN_B(shader_precompile, "true") DRI_CONF_DESC(en, "Perform code generation at shader link time.") @@ -94,12 +94,11 @@ DRI_CONF_END #include "intel_batchbuffer.h" #include "intel_buffers.h" #include "intel_bufmgr.h" -#include "intel_chipset.h" #include "intel_fbo.h" #include "intel_mipmap_tree.h" #include "intel_screen.h" #include "intel_tex.h" -#include "intel_regions.h" +#include "intel_image.h" #include "brw_context.h" @@ -123,7 +122,7 @@ aub_dump_bmp(struct gl_context *ctx) { struct gl_framebuffer *fb = ctx->DrawBuffer; - for (int i = 0; i < fb->_NumColorDrawBuffers; i++) { + for (unsigned i = 0; i < fb->_NumColorDrawBuffers; i++) { struct intel_renderbuffer *irb = intel_renderbuffer(fb->_ColorDrawBuffers[i]); @@ -139,21 +138,20 @@ aub_dump_bmp(struct gl_context *ctx) continue; } - assert(irb->mt->region->pitch % irb->mt->region->cpp == 0); - drm_intel_gem_bo_aub_dump_bmp(irb->mt->region->bo, + drm_intel_gem_bo_aub_dump_bmp(irb->mt->bo, irb->draw_x, irb->draw_y, irb->Base.Base.Width, irb->Base.Base.Height, format, - irb->mt->region->pitch, + irb->mt->pitch, 0); } } } static const __DRItexBufferExtension intelTexBufferExtension = { - .base = { __DRI_TEX_BUFFER, __DRI_TEX_BUFFER_VERSION }, + .base = { __DRI_TEX_BUFFER, 3 }, .setTexBuffer = intelSetTexBuffer, .setTexBuffer2 = intelSetTexBuffer2, @@ -178,10 +176,10 @@ intel_dri2_flush_with_flags(__DRIcontext *cPriv, if (flags & __DRI2_FLUSH_DRAWABLE) intel_resolve_for_dri2_flush(brw, dPriv); - if (reason == __DRI2_THROTTLE_SWAPBUFFER || - reason == __DRI2_THROTTLE_FLUSHFRONT) { - brw->need_throttle = true; - } + if (reason == __DRI2_THROTTLE_SWAPBUFFER) + brw->need_swap_throttle = true; + if (reason == __DRI2_THROTTLE_FLUSHFRONT) + brw->need_flush_throttle = true; intel_batchbuffer_flush(brw); @@ -216,15 +214,27 @@ static struct intel_image_format intel_image_formats[] = { { __DRI_IMAGE_FOURCC_ARGB8888, __DRI_IMAGE_COMPONENTS_RGBA, 1, { { 0, 0, 0, __DRI_IMAGE_FORMAT_ARGB8888, 4 } } }, + { __DRI_IMAGE_FOURCC_ABGR8888, __DRI_IMAGE_COMPONENTS_RGBA, 1, + { { 0, 0, 0, __DRI_IMAGE_FORMAT_ABGR8888, 4 } } }, + { __DRI_IMAGE_FOURCC_SARGB8888, __DRI_IMAGE_COMPONENTS_RGBA, 1, { { 0, 0, 0, __DRI_IMAGE_FORMAT_SARGB8, 4 } } }, { __DRI_IMAGE_FOURCC_XRGB8888, __DRI_IMAGE_COMPONENTS_RGB, 1, { { 0, 0, 0, __DRI_IMAGE_FORMAT_XRGB8888, 4 }, } }, + { __DRI_IMAGE_FOURCC_XBGR8888, __DRI_IMAGE_COMPONENTS_RGB, 1, + { { 0, 0, 0, __DRI_IMAGE_FORMAT_XBGR8888, 4 }, } }, + { __DRI_IMAGE_FOURCC_RGB565, __DRI_IMAGE_COMPONENTS_RGB, 1, { { 0, 0, 0, __DRI_IMAGE_FORMAT_RGB565, 2 } } }, + { __DRI_IMAGE_FOURCC_R8, __DRI_IMAGE_COMPONENTS_R, 1, + { { 0, 0, 0, __DRI_IMAGE_FORMAT_R8, 1 }, } }, + + { __DRI_IMAGE_FOURCC_GR88, __DRI_IMAGE_COMPONENTS_RG, 1, + { { 0, 0, 0, __DRI_IMAGE_FORMAT_GR88, 2 }, } }, + { __DRI_IMAGE_FOURCC_YUV410, __DRI_IMAGE_COMPONENTS_Y_U_V, 3, { { 0, 0, 0, __DRI_IMAGE_FORMAT_R8, 1 }, { 1, 2, 2, __DRI_IMAGE_FORMAT_R8, 1 }, @@ -271,6 +281,18 @@ static struct intel_image_format intel_image_formats[] = { { 0, 1, 0, __DRI_IMAGE_FORMAT_ARGB8888, 4 } } } }; +static void +intel_image_warn_if_unaligned(__DRIimage *image, const char *func) +{ + uint32_t tiling, swizzle; + drm_intel_bo_get_tiling(image->bo, &tiling, &swizzle); + + if (tiling != I915_TILING_NONE && (image->offset & 0xfff)) { + _mesa_warning(NULL, "%s: offset 0x%08x not on tile boundary", + func, image->offset); + } +} + static struct intel_image_format * intel_image_format_lookup(int fourcc) { @@ -286,6 +308,17 @@ intel_image_format_lookup(int fourcc) return f; } +static boolean intel_lookup_fourcc(int dri_format, int *fourcc) +{ + for (unsigned i = 0; i < ARRAY_SIZE(intel_image_formats); i++) { + if (intel_image_formats[i].planes[0].dri_format == dri_format) { + *fourcc = intel_image_formats[i].fourcc; + return true; + } + } + return false; +} + static __DRIimage * intel_allocate_image(int dri_format, void *loaderPrivate) { @@ -312,44 +345,28 @@ intel_allocate_image(int dri_format, void *loaderPrivate) } /** - * Sets up a DRIImage structure to point to our shared image in a region + * Sets up a DRIImage structure to point to a slice out of a miptree. */ static void intel_setup_image_from_mipmap_tree(struct brw_context *brw, __DRIimage *image, struct intel_mipmap_tree *mt, GLuint level, GLuint zoffset) { - unsigned int draw_x, draw_y; - uint32_t mask_x, mask_y; - intel_miptree_make_shareable(brw, mt); intel_miptree_check_level_layer(mt, level, zoffset); - intel_region_get_tile_masks(mt->region, &mask_x, &mask_y, false); - intel_miptree_get_image_offset(mt, level, zoffset, &draw_x, &draw_y); + image->width = minify(mt->physical_width0, level - mt->first_level); + image->height = minify(mt->physical_height0, level - mt->first_level); + image->pitch = mt->pitch; - image->width = minify(mt->physical_width0, level); - image->height = minify(mt->physical_height0, level); - image->tile_x = draw_x & mask_x; - image->tile_y = draw_y & mask_y; + image->offset = intel_miptree_get_tile_offsets(mt, level, zoffset, + &image->tile_x, + &image->tile_y); - image->offset = intel_region_get_aligned_offset(mt->region, - draw_x & ~mask_x, - draw_y & ~mask_y, - false); - - intel_region_reference(&image->region, mt->region); -} - -static void -intel_setup_image_from_dimensions(__DRIimage *image) -{ - image->width = image->region->width; - image->height = image->region->height; - image->tile_x = 0; - image->tile_y = 0; - image->has_depthstencil = false; + drm_intel_bo_unreference(image->bo); + image->bo = mt->bo; + drm_intel_bo_reference(mt->bo); } static __DRIimage * @@ -369,16 +386,17 @@ intel_create_image_from_name(__DRIscreen *screen, cpp = 1; else cpp = _mesa_get_format_bytes(image->format); - image->region = intel_region_alloc_for_handle(intelScreen, - cpp, width, height, - pitch * cpp, name, "image"); - if (image->region == NULL) { + + image->width = width; + image->height = height; + image->pitch = pitch * cpp; + image->bo = drm_intel_bo_gem_create_from_name(intelScreen->bufmgr, "image", + name); + if (!image->bo) { free(image); return NULL; } - intel_setup_image_from_dimensions(image); - return image; } @@ -408,8 +426,12 @@ intel_create_image_from_renderbuffer(__DRIcontext *context, image->format = rb->Format; image->offset = 0; image->data = loaderPrivate; - intel_region_reference(&image->region, irb->mt->region); - intel_setup_image_from_dimensions(image); + drm_intel_bo_unreference(image->bo); + image->bo = irb->mt->bo; + drm_intel_bo_reference(irb->mt->bo); + image->width = rb->Width; + image->height = rb->Height; + image->pitch = irb->mt->pitch; image->dri_format = driGLFormatToImageFormat(image->format); image->has_depthstencil = irb->mt->stencil_mt? true : false; @@ -480,8 +502,8 @@ intel_create_image_from_texture(__DRIcontext *context, int target, static void intel_destroy_image(__DRIimage *image) { - intel_region_release(&image->region); - free(image); + drm_intel_bo_unreference(image->bo); + free(image); } static __DRIimage * @@ -494,6 +516,7 @@ intel_create_image(__DRIscreen *screen, struct intel_screen *intelScreen = screen->driverPrivate; uint32_t tiling; int cpp; + unsigned long pitch; tiling = I915_TILING_X; if (use & __DRI_IMAGE_USE_CURSOR) { @@ -509,15 +532,18 @@ intel_create_image(__DRIscreen *screen, if (image == NULL) return NULL; + cpp = _mesa_get_format_bytes(image->format); - image->region = - intel_region_alloc(intelScreen, tiling, cpp, width, height, true); - if (image->region == NULL) { + image->bo = drm_intel_bo_alloc_tiled(intelScreen->bufmgr, "image", + width, height, cpp, &tiling, + &pitch, 0); + if (image->bo == NULL) { free(image); return NULL; } - - intel_setup_image_from_dimensions(image); + image->width = width; + image->height = height; + image->pitch = pitch; return image; } @@ -527,21 +553,21 @@ intel_query_image(__DRIimage *image, int attrib, int *value) { switch (attrib) { case __DRI_IMAGE_ATTRIB_STRIDE: - *value = image->region->pitch; + *value = image->pitch; return true; case __DRI_IMAGE_ATTRIB_HANDLE: - *value = image->region->bo->handle; + *value = image->bo->handle; return true; case __DRI_IMAGE_ATTRIB_NAME: - return intel_region_flink(image->region, (uint32_t *) value); + return !drm_intel_bo_flink(image->bo, (uint32_t *) value); case __DRI_IMAGE_ATTRIB_FORMAT: *value = image->dri_format; return true; case __DRI_IMAGE_ATTRIB_WIDTH: - *value = image->region->width; + *value = image->width; return true; case __DRI_IMAGE_ATTRIB_HEIGHT: - *value = image->region->height; + *value = image->height; return true; case __DRI_IMAGE_ATTRIB_COMPONENTS: if (image->planar_format == NULL) @@ -549,9 +575,17 @@ intel_query_image(__DRIimage *image, int attrib, int *value) *value = image->planar_format->components; return true; case __DRI_IMAGE_ATTRIB_FD: - if (drm_intel_bo_gem_export_to_prime(image->region->bo, value) == 0) + if (drm_intel_bo_gem_export_to_prime(image->bo, value) == 0) return true; return false; + case __DRI_IMAGE_ATTRIB_FOURCC: + if (intel_lookup_fourcc(image->dri_format, value)) + return true; + return false; + case __DRI_IMAGE_ATTRIB_NUM_PLANES: + *value = 1; + return true; + default: return false; } @@ -566,12 +600,8 @@ intel_dup_image(__DRIimage *orig_image, void *loaderPrivate) if (image == NULL) return NULL; - intel_region_reference(&image->region, orig_image->region); - if (image->region == NULL) { - free(image); - return NULL; - } - + drm_intel_bo_reference(orig_image->bo); + image->bo = orig_image->bo; image->internal_format = orig_image->internal_format; image->planar_format = orig_image->planar_format; image->dri_format = orig_image->dri_format; @@ -579,6 +609,7 @@ intel_dup_image(__DRIimage *orig_image, void *loaderPrivate) image->offset = orig_image->offset; image->width = orig_image->width; image->height = orig_image->height; + image->pitch = orig_image->pitch; image->tile_x = orig_image->tile_x; image->tile_y = orig_image->tile_y; image->has_depthstencil = orig_image->has_depthstencil; @@ -594,7 +625,7 @@ static GLboolean intel_validate_usage(__DRIimage *image, unsigned int use) { if (use & __DRI_IMAGE_USE_CURSOR) { - if (image->region->width != 64 || image->region->height != 64) + if (image->width != 64 || image->height != 64) return GL_FALSE; } @@ -663,13 +694,16 @@ intel_create_image_from_fds(__DRIscreen *screen, if (image == NULL) return NULL; - image->region = intel_region_alloc_for_fd(intelScreen, - f->planes[0].cpp, width, height, strides[0], - height * strides[0], fds[0], "image"); - if (image->region == NULL) { + image->bo = drm_intel_bo_gem_create_from_prime(intelScreen->bufmgr, + fds[0], + height * strides[0]); + if (image->bo == NULL) { free(image); return NULL; } + image->width = width; + image->height = height; + image->pitch = strides[0]; image->planar_format = f; for (i = 0; i < f->nplanes; i++) { @@ -678,7 +712,10 @@ intel_create_image_from_fds(__DRIscreen *screen, image->strides[index] = strides[index]; } - intel_setup_image_from_dimensions(image); + if (f->nplanes == 1) { + image->offset = image->offsets[0]; + intel_image_warn_if_unaligned(image, __func__); + } return image; } @@ -733,7 +770,6 @@ intel_from_planar(__DRIimage *parent, int plane, void *loaderPrivate) { int width, height, offset, stride, dri_format, index; struct intel_image_format *f; - uint32_t mask_x, mask_y; __DRIimage *image; if (parent == NULL || parent->planar_format == NULL) @@ -744,8 +780,8 @@ intel_from_planar(__DRIimage *parent, int plane, void *loaderPrivate) if (plane >= f->nplanes) return NULL; - width = parent->region->width >> f->planes[plane].width_shift; - height = parent->region->height >> f->planes[plane].height_shift; + width = parent->width >> f->planes[plane].width_shift; + height = parent->height >> f->planes[plane].height_shift; dri_format = f->planes[plane].dri_format; index = f->planes[plane].buffer_index; offset = parent->offsets[index]; @@ -755,39 +791,27 @@ intel_from_planar(__DRIimage *parent, int plane, void *loaderPrivate) if (image == NULL) return NULL; - if (offset + height * stride > parent->region->bo->size) { + if (offset + height * stride > parent->bo->size) { _mesa_warning(NULL, "intel_create_sub_image: subimage out of bounds"); free(image); return NULL; } - image->region = calloc(sizeof(*image->region), 1); - if (image->region == NULL) { - free(image); - return NULL; - } + image->bo = parent->bo; + drm_intel_bo_reference(parent->bo); - image->region->cpp = _mesa_get_format_bytes(image->format); - image->region->width = width; - image->region->height = height; - image->region->pitch = stride; - image->region->refcount = 1; - image->region->bo = parent->region->bo; - drm_intel_bo_reference(image->region->bo); - image->region->tiling = parent->region->tiling; + image->width = width; + image->height = height; + image->pitch = stride; image->offset = offset; - intel_setup_image_from_dimensions(image); - intel_region_get_tile_masks(image->region, &mask_x, &mask_y, false); - if (offset & mask_x) - _mesa_warning(NULL, - "intel_create_sub_image: offset not on tile boundary"); + intel_image_warn_if_unaligned(image, __func__); return image; } -static struct __DRIimageExtensionRec intelImageExtension = { - .base = { __DRI_IMAGE, 8 }, +static const __DRIimageExtension intelImageExtension = { + .base = { __DRI_IMAGE, 11 }, .createImageFromName = intel_create_image_from_name, .createImageFromRenderbuffer = intel_create_image_from_renderbuffer, @@ -800,7 +824,9 @@ static struct __DRIimageExtensionRec intelImageExtension = { .fromPlanar = intel_from_planar, .createImageFromTexture = intel_create_image_from_texture, .createImageFromFds = intel_create_image_from_fds, - .createImageFromDmaBufs = intel_create_image_from_dma_bufs + .createImageFromDmaBufs = intel_create_image_from_dma_bufs, + .blitImage = NULL, + .getCapabilities = NULL }; static int @@ -842,7 +868,7 @@ brw_query_renderer_integer(__DRIscreen *psp, int param, unsigned int *value) * (uint64_t) system_page_size; const unsigned system_memory_megabytes = - (unsigned) (system_memory_bytes / 1024); + (unsigned) (system_memory_bytes / (1024 * 1024)); value[0] = MIN2(system_memory_megabytes, gpu_mappable_megabytes); return 0; @@ -850,10 +876,6 @@ brw_query_renderer_integer(__DRIscreen *psp, int param, unsigned int *value) case __DRI2_RENDERER_UNIFIED_MEMORY_ARCHITECTURE: value[0] = 1; return 0; - case __DRI2_RENDERER_PREFERRED_PROFILE: - value[0] = (psp->max_gl_core_version != 0) - ? (1U << __DRI_API_OPENGL_CORE) : (1U << __DRI_API_OPENGL); - return 0; default: return driQueryRendererIntegerCommon(psp, param, value); } @@ -881,19 +903,20 @@ brw_query_renderer_string(__DRIscreen *psp, int param, const char **value) return -1; } -static struct __DRI2rendererQueryExtensionRec intelRendererQueryExtension = { +static const __DRI2rendererQueryExtension intelRendererQueryExtension = { .base = { __DRI2_RENDERER_QUERY, 1 }, .queryInteger = brw_query_renderer_integer, .queryString = brw_query_renderer_string }; -static const struct __DRIrobustnessExtensionRec dri2Robustness = { - { __DRI2_ROBUSTNESS, 1 } +static const __DRIrobustnessExtension dri2Robustness = { + .base = { __DRI2_ROBUSTNESS, 1 } }; static const __DRIextension *intelScreenExtensions[] = { &intelTexBufferExtension.base, + &intelFenceExtension.base, &intelFlushExtension.base, &intelImageExtension.base, &intelRendererQueryExtension.base, @@ -903,6 +926,7 @@ static const __DRIextension *intelScreenExtensions[] = { static const __DRIextension *intelRobustScreenExtensions[] = { &intelTexBufferExtension.base, + &intelFenceExtension.base, &intelFlushExtension.base, &intelImageExtension.base, &intelRendererQueryExtension.base, @@ -946,7 +970,7 @@ intelDestroyScreen(__DRIscreen * sPriv) dri_bufmgr_destroy(intelScreen->bufmgr); driDestroyOptionInfo(&intelScreen->optionCache); - free(intelScreen); + ralloc_free(intelScreen); sPriv->driverPrivate = NULL; } @@ -974,6 +998,11 @@ intelCreateBuffer(__DRIscreen * driScrnPriv, _mesa_initialize_window_framebuffer(fb, mesaVis); + if (screen->winsys_msaa_samples_override != -1) { + num_samples = screen->winsys_msaa_samples_override; + fb->Visual.samples = num_samples; + } + if (mesaVis->redBits == 5) rgbFormat = MESA_FORMAT_B5G6R5_UNORM; else if (mesaVis->sRGBCapable) @@ -1100,6 +1129,50 @@ intel_detect_swizzling(struct intel_screen *screen) return true; } +static int +intel_detect_timestamp(struct intel_screen *screen) +{ + uint64_t dummy = 0, last = 0; + int upper, lower, loops; + + /* On 64bit systems, some old kernels trigger a hw bug resulting in the + * TIMESTAMP register being shifted and the low 32bits always zero. + * + * More recent kernels offer an interface to read the full 36bits + * everywhere. + */ + if (drm_intel_reg_read(screen->bufmgr, TIMESTAMP | 1, &dummy) == 0) + return 3; + + /* Determine if we have a 32bit or 64bit kernel by inspecting the + * upper 32bits for a rapidly changing timestamp. + */ + if (drm_intel_reg_read(screen->bufmgr, TIMESTAMP, &last)) + return 0; + + upper = lower = 0; + for (loops = 0; loops < 10; loops++) { + /* The TIMESTAMP should change every 80ns, so several round trips + * through the kernel should be enough to advance it. + */ + if (drm_intel_reg_read(screen->bufmgr, TIMESTAMP, &dummy)) + return 0; + + upper += (dummy >> 32) != (last >> 32); + if (upper > 1) /* beware 32bit counter overflow */ + return 2; /* upper dword holds the low 32bits of the timestamp */ + + lower += (dummy & 0xffffffff) != (last & 0xffffffff); + if (lower > 1) + return 1; /* timestamp is unshifted */ + + last = dummy; + } + + /* No advancement? No timestamp! */ + return 0; +} + /** * Return array of MSAA modes supported by the hardware. The array is * zero-terminated and sorted in decreasing order. @@ -1128,7 +1201,8 @@ intel_screen_make_configs(__DRIscreen *dri_screen) { static const mesa_format formats[] = { MESA_FORMAT_B5G6R5_UNORM, - MESA_FORMAT_B8G8R8A8_UNORM + MESA_FORMAT_B8G8R8A8_UNORM, + MESA_FORMAT_B8G8R8X8_UNORM }; /* GLX_SWAP_COPY_OML is not supported due to page flipping. */ @@ -1145,7 +1219,7 @@ intel_screen_make_configs(__DRIscreen *dri_screen) __DRIconfig **configs = NULL; /* Generate singlesample configs without accumulation buffer. */ - for (int i = 0; i < ARRAY_SIZE(formats); i++) { + for (unsigned i = 0; i < ARRAY_SIZE(formats); i++) { __DRIconfig **new_configs; int num_depth_stencil_bits = 2; @@ -1182,7 +1256,7 @@ intel_screen_make_configs(__DRIscreen *dri_screen) /* Generate the minimum possible set of configs that include an * accumulation buffer. */ - for (int i = 0; i < ARRAY_SIZE(formats); i++) { + for (unsigned i = 0; i < ARRAY_SIZE(formats); i++) { __DRIconfig **new_configs; if (formats[i] == MESA_FORMAT_B5G6R5_UNORM) { @@ -1214,7 +1288,7 @@ intel_screen_make_configs(__DRIscreen *dri_screen) * supported. Singlebuffer configs are not supported because no one wants * them. */ - for (int i = 0; i < ARRAY_SIZE(formats); i++) { + for (unsigned i = 0; i < ARRAY_SIZE(formats); i++) { if (devinfo->gen < 6) break; @@ -1264,15 +1338,11 @@ set_max_gl_versions(struct intel_screen *screen) __DRIscreen *psp = screen->driScrnPriv; switch (screen->devinfo->gen) { + case 9: case 8: case 7: - psp->max_gl_core_version = 33; - psp->max_gl_compat_version = 30; - psp->max_gl_es1_version = 11; - psp->max_gl_es2_version = 30; - break; case 6: - psp->max_gl_core_version = 31; + psp->max_gl_core_version = 33; psp->max_gl_compat_version = 30; psp->max_gl_es1_version = 11; psp->max_gl_es2_version = 30; @@ -1285,11 +1355,33 @@ set_max_gl_versions(struct intel_screen *screen) psp->max_gl_es2_version = 20; break; default: - assert(!"unrecognized intel_screen::gen"); - break; + unreachable("unrecognized intel_screen::gen"); } } +static int +brw_get_revision(int fd) +{ + struct drm_i915_getparam gp; + int revision; + int ret; + + memset(&gp, 0, sizeof(gp)); + gp.param = I915_PARAM_REVISION; + gp.value = &revision; + + ret = drmCommandWriteRead(fd, DRM_I915_GETPARAM, &gp, sizeof(gp)); + if (ret) + revision = -1; + + return revision; +} + +/* Drop when RS headers get pulled to libdrm */ +#ifndef I915_PARAM_HAS_RESOURCE_STREAMER +#define I915_PARAM_HAS_RESOURCE_STREAMER 36 +#endif + /** * This is the driver specific part of the createNewScreen entry point. * Called when using DRI2. @@ -1311,7 +1403,7 @@ __DRIconfig **intelInitScreen2(__DRIscreen *psp) } /* Allocate the private area */ - intelScreen = calloc(1, sizeof *intelScreen); + intelScreen = rzalloc(NULL, struct intel_screen); if (!intelScreen) { fprintf(stderr, "\nERROR! Allocating private area failed\n"); return false; @@ -1326,13 +1418,27 @@ __DRIconfig **intelInitScreen2(__DRIscreen *psp) return false; intelScreen->deviceID = drm_intel_bufmgr_gem_get_devid(intelScreen->bufmgr); - intelScreen->devinfo = brw_get_device_info(intelScreen->deviceID); + intelScreen->devinfo = brw_get_device_info(intelScreen->deviceID, + brw_get_revision(psp->fd)); if (!intelScreen->devinfo) return false; + brw_process_intel_debug_variable(intelScreen); + intelScreen->hw_must_use_separate_stencil = intelScreen->devinfo->gen >= 7; intelScreen->hw_has_swizzling = intel_detect_swizzling(intelScreen); + intelScreen->hw_has_timestamp = intel_detect_timestamp(intelScreen); + + const char *force_msaa = getenv("INTEL_FORCE_MSAA"); + if (force_msaa) { + intelScreen->winsys_msaa_samples_override = + intel_quantize_num_samples(intelScreen, atoi(force_msaa)); + printf("Forcing winsys sample count to %d\n", + intelScreen->winsys_msaa_samples_override); + } else { + intelScreen->winsys_msaa_samples_override = -1; + } set_max_gl_versions(intelScreen); @@ -1342,23 +1448,119 @@ __DRIconfig **intelInitScreen2(__DRIscreen *psp) * no error. If the ioctl is not supported, it always generate EINVAL. * Use this to determine whether to advertise the __DRI2_ROBUSTNESS * extension to the loader. + * + * Don't even try on pre-Gen6, since we don't attempt to use contexts there. */ - struct drm_i915_reset_stats stats; - memset(&stats, 0, sizeof(stats)); + if (intelScreen->devinfo->gen >= 6) { + struct drm_i915_reset_stats stats; + memset(&stats, 0, sizeof(stats)); + + const int ret = drmIoctl(psp->fd, DRM_IOCTL_I915_GET_RESET_STATS, &stats); - const int ret = drmIoctl(psp->fd, DRM_IOCTL_I915_GET_RESET_STATS, &stats); + intelScreen->has_context_reset_notification = + (ret != -1 || errno != EINVAL); + } - intelScreen->has_context_reset_notification = (ret != -1 || errno != EINVAL); + struct drm_i915_getparam getparam; + getparam.param = I915_PARAM_CMD_PARSER_VERSION; + getparam.value = &intelScreen->cmd_parser_version; + const int ret = drmIoctl(psp->fd, DRM_IOCTL_I915_GETPARAM, &getparam); + if (ret == -1) + intelScreen->cmd_parser_version = 0; psp->extensions = !intelScreen->has_context_reset_notification ? intelScreenExtensions : intelRobustScreenExtensions; + intelScreen->compiler = brw_compiler_create(intelScreen, + intelScreen->devinfo); + + if (intelScreen->devinfo->has_resource_streamer) { + int val = -1; + getparam.param = I915_PARAM_HAS_RESOURCE_STREAMER; + getparam.value = &val; + + drmIoctl(psp->fd, DRM_IOCTL_I915_GETPARAM, &getparam); + intelScreen->has_resource_streamer = val > 0; + } + return (const __DRIconfig**) intel_screen_make_configs(psp); } +struct intel_screen * +intel_screen_create(int fd) +{ + __DRIscreen *psp; + __DRIconfig **configs; + int i; + + psp = malloc(sizeof(*psp)); + if (psp == NULL) + return NULL; + + psp->image.loader = (void *) 1; /* Don't complain about this being NULL */ + psp->fd = fd; + psp->dri2.useInvalidate = (void *) 1; + + configs = (__DRIconfig **) intelInitScreen2(psp); + for (i = 0; configs[i]; i++) + free(configs[i]); + free(configs); + + return psp->driverPrivate; +} + +void +intel_screen_destroy(struct intel_screen *screen) +{ + __DRIscreen *psp; + + psp = screen->driScrnPriv; + intelDestroyScreen(screen->driScrnPriv); + free(psp); +} + + +struct brw_context * +intel_context_create(struct intel_screen *screen) +{ + __DRIcontext *driContextPriv; + struct brw_context *brw; + unsigned error; + + driContextPriv = malloc(sizeof(*driContextPriv)); + if (driContextPriv == NULL) + return NULL; + + driContextPriv->driScreenPriv = screen->driScrnPriv; + + brwCreateContext(API_OPENGL_CORE, + NULL, /* visual */ + driContextPriv, + 3, 0, + 0, /* flags */ + false, /* notify_reset */ + &error, + NULL); + + brw = driContextPriv->driverPrivate; + brw->ctx.FirstTimeCurrent = false; + + return driContextPriv->driverPrivate; +} + +void +intel_context_destroy(struct brw_context *brw) +{ + __DRIcontext *driContextPriv; + + driContextPriv = brw->driContext; + intelDestroyContext(driContextPriv); + free(driContextPriv); +} + struct intel_buffer { __DRIbuffer base; - struct intel_region *region; + drm_intel_bo *bo; }; static __DRIbuffer * @@ -1377,23 +1579,27 @@ intelAllocateBuffer(__DRIscreen *screen, return NULL; /* The front and back buffers are color buffers, which are X tiled. */ - intelBuffer->region = intel_region_alloc(intelScreen, - I915_TILING_X, - format / 8, - width, - height, - true); - - if (intelBuffer->region == NULL) { + uint32_t tiling = I915_TILING_X; + unsigned long pitch; + int cpp = format / 8; + intelBuffer->bo = drm_intel_bo_alloc_tiled(intelScreen->bufmgr, + "intelAllocateBuffer", + width, + height, + cpp, + &tiling, &pitch, + BO_ALLOC_FOR_RENDER); + + if (intelBuffer->bo == NULL) { free(intelBuffer); return NULL; } - intel_region_flink(intelBuffer->region, &intelBuffer->base.name); + drm_intel_bo_flink(intelBuffer->bo, &intelBuffer->base.name); intelBuffer->base.attachment = attachment; - intelBuffer->base.cpp = intelBuffer->region->cpp; - intelBuffer->base.pitch = intelBuffer->region->pitch; + intelBuffer->base.cpp = cpp; + intelBuffer->base.pitch = pitch; return &intelBuffer->base; } @@ -1403,7 +1609,7 @@ intelReleaseBuffer(__DRIscreen *screen, __DRIbuffer *buffer) { struct intel_buffer *intelBuffer = (struct intel_buffer *) buffer; - intel_region_release(&intelBuffer->region); + drm_intel_bo_unreference(intelBuffer->bo); free(intelBuffer); }