X-Git-Url: https://git.libre-soc.org/?a=blobdiff_plain;f=src%2Fmesa%2Fdrivers%2Fdri%2Fi965%2Fintel_screen.c;h=81df6b34e653fae75614af18e364127c5c5692db;hb=04dc6074cf7f651b720868e0ba24362b585d1b31;hp=ece4ce0e334c09d7283fc48d7918998eee7b6668;hpb=2a2e69f975bd791d64a88553d5b1d5eda7e8abdf;p=mesa.git diff --git a/src/mesa/drivers/dri/i965/intel_screen.c b/src/mesa/drivers/dri/i965/intel_screen.c index ece4ce0e334..81df6b34e65 100644 --- a/src/mesa/drivers/dri/i965/intel_screen.c +++ b/src/mesa/drivers/dri/i965/intel_screen.c @@ -23,7 +23,7 @@ * SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. */ -#include +#include "drm-uapi/drm_fourcc.h" #include #include #include @@ -34,6 +34,7 @@ #include "main/hash.h" #include "main/fbobject.h" #include "main/version.h" +#include "main/glthread.h" #include "swrast/s_renderbuffer.h" #include "util/ralloc.h" #include "util/disk_cache.h" @@ -62,6 +63,7 @@ DRI_CONF_BEGIN DRI_CONF_DESC_END DRI_CONF_OPT_END DRI_CONF_MESA_NO_ERROR("false") + DRI_CONF_MESA_GLTHREAD("false") DRI_CONF_SECTION_END DRI_CONF_SECTION_QUALITY @@ -86,6 +88,7 @@ DRI_CONF_BEGIN DRI_CONF_ALLOW_GLSL_BUILTIN_VARIABLE_REDECLARATION("false") DRI_CONF_ALLOW_GLSL_CROSS_STAGE_INTERPOLATION_MISMATCH("false") DRI_CONF_ALLOW_HIGHER_COMPAT_VERSION("false") + DRI_CONF_FORCE_COMPAT_PROFILE("false") DRI_CONF_FORCE_GLSL_ABS_SQRT("false") DRI_CONF_OPT_BEGIN_B(shader_precompile, "true") @@ -96,6 +99,8 @@ DRI_CONF_BEGIN DRI_CONF_SECTION_MISCELLANEOUS DRI_CONF_GLSL_ZERO_INIT("false") DRI_CONF_ALLOW_RGB10_CONFIGS("false") + DRI_CONF_ALLOW_RGB565_CONFIGS("true") + DRI_CONF_ALLOW_FP16_CONFIGS("false") DRI_CONF_SECTION_END DRI_CONF_END }; @@ -111,7 +116,7 @@ DRI_CONF_END #include "brw_context.h" -#include "i915_drm.h" +#include "drm-uapi/i915_drm.h" /** * For debugging purposes, this returns a time in seconds. @@ -147,6 +152,8 @@ intel_dri2_flush_with_flags(__DRIcontext *cPriv, struct gl_context *ctx = &brw->ctx; + _mesa_glthread_finish(ctx); + FLUSH_VERTICES(ctx, 0); if (flags & __DRI2_FLUSH_DRAWABLE) @@ -183,124 +190,133 @@ static const struct __DRI2flushExtensionRec intelFlushExtension = { }; static const struct intel_image_format intel_image_formats[] = { - { __DRI_IMAGE_FOURCC_ARGB2101010, __DRI_IMAGE_COMPONENTS_RGBA, 1, + { DRM_FORMAT_ABGR16161616F, __DRI_IMAGE_COMPONENTS_RGBA, 1, + { { 0, 0, 0, __DRI_IMAGE_FORMAT_ABGR16161616F, 8 } } }, + + { DRM_FORMAT_XBGR16161616F, __DRI_IMAGE_COMPONENTS_RGB, 1, + { { 0, 0, 0, __DRI_IMAGE_FORMAT_XBGR16161616F, 8 } } }, + + { DRM_FORMAT_ARGB2101010, __DRI_IMAGE_COMPONENTS_RGBA, 1, { { 0, 0, 0, __DRI_IMAGE_FORMAT_ARGB2101010, 4 } } }, - { __DRI_IMAGE_FOURCC_XRGB2101010, __DRI_IMAGE_COMPONENTS_RGB, 1, + { DRM_FORMAT_XRGB2101010, __DRI_IMAGE_COMPONENTS_RGB, 1, { { 0, 0, 0, __DRI_IMAGE_FORMAT_XRGB2101010, 4 } } }, - { __DRI_IMAGE_FOURCC_ABGR2101010, __DRI_IMAGE_COMPONENTS_RGBA, 1, + { DRM_FORMAT_ABGR2101010, __DRI_IMAGE_COMPONENTS_RGBA, 1, { { 0, 0, 0, __DRI_IMAGE_FORMAT_ABGR2101010, 4 } } }, - { __DRI_IMAGE_FOURCC_XBGR2101010, __DRI_IMAGE_COMPONENTS_RGB, 1, + { DRM_FORMAT_XBGR2101010, __DRI_IMAGE_COMPONENTS_RGB, 1, { { 0, 0, 0, __DRI_IMAGE_FORMAT_XBGR2101010, 4 } } }, - { __DRI_IMAGE_FOURCC_ARGB8888, __DRI_IMAGE_COMPONENTS_RGBA, 1, + { DRM_FORMAT_ARGB8888, __DRI_IMAGE_COMPONENTS_RGBA, 1, { { 0, 0, 0, __DRI_IMAGE_FORMAT_ARGB8888, 4 } } }, - { __DRI_IMAGE_FOURCC_ABGR8888, __DRI_IMAGE_COMPONENTS_RGBA, 1, + { DRM_FORMAT_ABGR8888, __DRI_IMAGE_COMPONENTS_RGBA, 1, { { 0, 0, 0, __DRI_IMAGE_FORMAT_ABGR8888, 4 } } }, { __DRI_IMAGE_FOURCC_SARGB8888, __DRI_IMAGE_COMPONENTS_RGBA, 1, { { 0, 0, 0, __DRI_IMAGE_FORMAT_SARGB8, 4 } } }, - { __DRI_IMAGE_FOURCC_XRGB8888, __DRI_IMAGE_COMPONENTS_RGB, 1, + { DRM_FORMAT_XRGB8888, __DRI_IMAGE_COMPONENTS_RGB, 1, { { 0, 0, 0, __DRI_IMAGE_FORMAT_XRGB8888, 4 }, } }, - { __DRI_IMAGE_FOURCC_XBGR8888, __DRI_IMAGE_COMPONENTS_RGB, 1, + { DRM_FORMAT_XBGR8888, __DRI_IMAGE_COMPONENTS_RGB, 1, { { 0, 0, 0, __DRI_IMAGE_FORMAT_XBGR8888, 4 }, } }, - { __DRI_IMAGE_FOURCC_ARGB1555, __DRI_IMAGE_COMPONENTS_RGBA, 1, + { DRM_FORMAT_ARGB1555, __DRI_IMAGE_COMPONENTS_RGBA, 1, { { 0, 0, 0, __DRI_IMAGE_FORMAT_ARGB1555, 2 } } }, - { __DRI_IMAGE_FOURCC_RGB565, __DRI_IMAGE_COMPONENTS_RGB, 1, + { DRM_FORMAT_RGB565, __DRI_IMAGE_COMPONENTS_RGB, 1, { { 0, 0, 0, __DRI_IMAGE_FORMAT_RGB565, 2 } } }, - { __DRI_IMAGE_FOURCC_R8, __DRI_IMAGE_COMPONENTS_R, 1, + { DRM_FORMAT_R8, __DRI_IMAGE_COMPONENTS_R, 1, { { 0, 0, 0, __DRI_IMAGE_FORMAT_R8, 1 }, } }, - { __DRI_IMAGE_FOURCC_R16, __DRI_IMAGE_COMPONENTS_R, 1, + { DRM_FORMAT_R16, __DRI_IMAGE_COMPONENTS_R, 1, { { 0, 0, 0, __DRI_IMAGE_FORMAT_R16, 1 }, } }, - { __DRI_IMAGE_FOURCC_GR88, __DRI_IMAGE_COMPONENTS_RG, 1, + { DRM_FORMAT_GR88, __DRI_IMAGE_COMPONENTS_RG, 1, { { 0, 0, 0, __DRI_IMAGE_FORMAT_GR88, 2 }, } }, - { __DRI_IMAGE_FOURCC_GR1616, __DRI_IMAGE_COMPONENTS_RG, 1, + { DRM_FORMAT_GR1616, __DRI_IMAGE_COMPONENTS_RG, 1, { { 0, 0, 0, __DRI_IMAGE_FORMAT_GR1616, 2 }, } }, - { __DRI_IMAGE_FOURCC_YUV410, __DRI_IMAGE_COMPONENTS_Y_U_V, 3, + { DRM_FORMAT_YUV410, __DRI_IMAGE_COMPONENTS_Y_U_V, 3, { { 0, 0, 0, __DRI_IMAGE_FORMAT_R8, 1 }, { 1, 2, 2, __DRI_IMAGE_FORMAT_R8, 1 }, { 2, 2, 2, __DRI_IMAGE_FORMAT_R8, 1 } } }, - { __DRI_IMAGE_FOURCC_YUV411, __DRI_IMAGE_COMPONENTS_Y_U_V, 3, + { DRM_FORMAT_YUV411, __DRI_IMAGE_COMPONENTS_Y_U_V, 3, { { 0, 0, 0, __DRI_IMAGE_FORMAT_R8, 1 }, { 1, 2, 0, __DRI_IMAGE_FORMAT_R8, 1 }, { 2, 2, 0, __DRI_IMAGE_FORMAT_R8, 1 } } }, - { __DRI_IMAGE_FOURCC_YUV420, __DRI_IMAGE_COMPONENTS_Y_U_V, 3, + { DRM_FORMAT_YUV420, __DRI_IMAGE_COMPONENTS_Y_U_V, 3, { { 0, 0, 0, __DRI_IMAGE_FORMAT_R8, 1 }, { 1, 1, 1, __DRI_IMAGE_FORMAT_R8, 1 }, { 2, 1, 1, __DRI_IMAGE_FORMAT_R8, 1 } } }, - { __DRI_IMAGE_FOURCC_YUV422, __DRI_IMAGE_COMPONENTS_Y_U_V, 3, + { DRM_FORMAT_YUV422, __DRI_IMAGE_COMPONENTS_Y_U_V, 3, { { 0, 0, 0, __DRI_IMAGE_FORMAT_R8, 1 }, { 1, 1, 0, __DRI_IMAGE_FORMAT_R8, 1 }, { 2, 1, 0, __DRI_IMAGE_FORMAT_R8, 1 } } }, - { __DRI_IMAGE_FOURCC_YUV444, __DRI_IMAGE_COMPONENTS_Y_U_V, 3, + { DRM_FORMAT_YUV444, __DRI_IMAGE_COMPONENTS_Y_U_V, 3, { { 0, 0, 0, __DRI_IMAGE_FORMAT_R8, 1 }, { 1, 0, 0, __DRI_IMAGE_FORMAT_R8, 1 }, { 2, 0, 0, __DRI_IMAGE_FORMAT_R8, 1 } } }, - { __DRI_IMAGE_FOURCC_YVU410, __DRI_IMAGE_COMPONENTS_Y_U_V, 3, + { DRM_FORMAT_YVU410, __DRI_IMAGE_COMPONENTS_Y_U_V, 3, { { 0, 0, 0, __DRI_IMAGE_FORMAT_R8, 1 }, { 2, 2, 2, __DRI_IMAGE_FORMAT_R8, 1 }, { 1, 2, 2, __DRI_IMAGE_FORMAT_R8, 1 } } }, - { __DRI_IMAGE_FOURCC_YVU411, __DRI_IMAGE_COMPONENTS_Y_U_V, 3, + { DRM_FORMAT_YVU411, __DRI_IMAGE_COMPONENTS_Y_U_V, 3, { { 0, 0, 0, __DRI_IMAGE_FORMAT_R8, 1 }, { 2, 2, 0, __DRI_IMAGE_FORMAT_R8, 1 }, { 1, 2, 0, __DRI_IMAGE_FORMAT_R8, 1 } } }, - { __DRI_IMAGE_FOURCC_YVU420, __DRI_IMAGE_COMPONENTS_Y_U_V, 3, + { DRM_FORMAT_YVU420, __DRI_IMAGE_COMPONENTS_Y_U_V, 3, { { 0, 0, 0, __DRI_IMAGE_FORMAT_R8, 1 }, { 2, 1, 1, __DRI_IMAGE_FORMAT_R8, 1 }, { 1, 1, 1, __DRI_IMAGE_FORMAT_R8, 1 } } }, - { __DRI_IMAGE_FOURCC_YVU422, __DRI_IMAGE_COMPONENTS_Y_U_V, 3, + { DRM_FORMAT_YVU422, __DRI_IMAGE_COMPONENTS_Y_U_V, 3, { { 0, 0, 0, __DRI_IMAGE_FORMAT_R8, 1 }, { 2, 1, 0, __DRI_IMAGE_FORMAT_R8, 1 }, { 1, 1, 0, __DRI_IMAGE_FORMAT_R8, 1 } } }, - { __DRI_IMAGE_FOURCC_YVU444, __DRI_IMAGE_COMPONENTS_Y_U_V, 3, + { DRM_FORMAT_YVU444, __DRI_IMAGE_COMPONENTS_Y_U_V, 3, { { 0, 0, 0, __DRI_IMAGE_FORMAT_R8, 1 }, { 2, 0, 0, __DRI_IMAGE_FORMAT_R8, 1 }, { 1, 0, 0, __DRI_IMAGE_FORMAT_R8, 1 } } }, - { __DRI_IMAGE_FOURCC_NV12, __DRI_IMAGE_COMPONENTS_Y_UV, 2, + { DRM_FORMAT_NV12, __DRI_IMAGE_COMPONENTS_Y_UV, 2, { { 0, 0, 0, __DRI_IMAGE_FORMAT_R8, 1 }, { 1, 1, 1, __DRI_IMAGE_FORMAT_GR88, 2 } } }, - { __DRI_IMAGE_FOURCC_P010, __DRI_IMAGE_COMPONENTS_Y_UV, 2, + { DRM_FORMAT_P010, __DRI_IMAGE_COMPONENTS_Y_UV, 2, { { 0, 0, 0, __DRI_IMAGE_FORMAT_R16, 2 }, - { 1, 1, 1, __DRI_IMAGE_FORMAT_GR1616, 4 } } , 65535.0f/1023.0f }, + { 1, 1, 1, __DRI_IMAGE_FORMAT_GR1616, 4 } } }, - { __DRI_IMAGE_FOURCC_P012, __DRI_IMAGE_COMPONENTS_Y_UV, 2, + { DRM_FORMAT_P012, __DRI_IMAGE_COMPONENTS_Y_UV, 2, { { 0, 0, 0, __DRI_IMAGE_FORMAT_R16, 2 }, - { 1, 1, 1, __DRI_IMAGE_FORMAT_GR1616, 4 } } , 65535.0f/4095.0f }, + { 1, 1, 1, __DRI_IMAGE_FORMAT_GR1616, 4 } } }, - { __DRI_IMAGE_FOURCC_P016, __DRI_IMAGE_COMPONENTS_Y_UV, 2, + { DRM_FORMAT_P016, __DRI_IMAGE_COMPONENTS_Y_UV, 2, { { 0, 0, 0, __DRI_IMAGE_FORMAT_R16, 2 }, { 1, 1, 1, __DRI_IMAGE_FORMAT_GR1616, 4 } } }, - { __DRI_IMAGE_FOURCC_NV16, __DRI_IMAGE_COMPONENTS_Y_UV, 2, + { DRM_FORMAT_NV16, __DRI_IMAGE_COMPONENTS_Y_UV, 2, { { 0, 0, 0, __DRI_IMAGE_FORMAT_R8, 1 }, { 1, 1, 0, __DRI_IMAGE_FORMAT_GR88, 2 } } }, - { __DRI_IMAGE_FOURCC_AYUV, __DRI_IMAGE_COMPONENTS_AYUV, 1, + { DRM_FORMAT_AYUV, __DRI_IMAGE_COMPONENTS_AYUV, 1, { { 0, 0, 0, __DRI_IMAGE_FORMAT_ABGR8888, 4 } } }, + { DRM_FORMAT_XYUV8888, __DRI_IMAGE_COMPONENTS_XYUV, 1, + { { 0, 0, 0, __DRI_IMAGE_FORMAT_XBGR8888, 4 } } }, + /* For YUYV and UYVY buffers, we set up two overlapping DRI images * and treat them as planar buffers in the compositors. * Plane 0 is GR88 and samples YU or YV pairs and places Y into @@ -309,10 +325,10 @@ static const struct intel_image_format intel_image_formats[] = { * V into A. This lets the texture sampler interpolate the Y * components correctly when sampling from plane 0, and interpolate * U and V correctly when sampling from plane 1. */ - { __DRI_IMAGE_FOURCC_YUYV, __DRI_IMAGE_COMPONENTS_Y_XUXV, 2, + { DRM_FORMAT_YUYV, __DRI_IMAGE_COMPONENTS_Y_XUXV, 2, { { 0, 0, 0, __DRI_IMAGE_FORMAT_GR88, 2 }, { 0, 1, 0, __DRI_IMAGE_FORMAT_ARGB8888, 4 } } }, - { __DRI_IMAGE_FOURCC_UYVY, __DRI_IMAGE_COMPONENTS_Y_UXVX, 2, + { DRM_FORMAT_UYVY, __DRI_IMAGE_COMPONENTS_Y_UXVX, 2, { { 0, 0, 0, __DRI_IMAGE_FORMAT_GR88, 2 }, { 0, 1, 0, __DRI_IMAGE_FORMAT_ABGR8888, 4 } } } }; @@ -412,7 +428,7 @@ intel_image_format_lookup(int fourcc) return NULL; } -static boolean +static bool intel_image_get_fourcc(__DRIimage *image, int *fourcc) { if (image->planar_format) { @@ -738,7 +754,9 @@ intel_create_image_common(__DRIscreen *dri_screen, .samples = 1, .usage = ISL_SURF_USAGE_RENDER_TARGET_BIT | ISL_SURF_USAGE_TEXTURE_BIT | - ISL_SURF_USAGE_STORAGE_BIT, + ISL_SURF_USAGE_STORAGE_BIT | + ((use & __DRI_IMAGE_USE_SCANOUT) ? + ISL_SURF_USAGE_DISPLAY_BIT : 0), .tiling_flags = (1 << mod_info->tiling)); assert(ok); if (!ok) { @@ -1375,7 +1393,8 @@ intel_query_dma_buf_modifiers(__DRIscreen *_screen, int fourcc, int max, for (i = 0; i < num_mods && i < max; i++) { if (f->components == __DRI_IMAGE_COMPONENTS_Y_U_V || f->components == __DRI_IMAGE_COMPONENTS_Y_UV || - f->components == __DRI_IMAGE_COMPONENTS_Y_XUXV) { + f->components == __DRI_IMAGE_COMPONENTS_Y_XUXV || + f->components == __DRI_IMAGE_COMPONENTS_Y_UXVX) { external_only[i] = GL_TRUE; } else { @@ -1724,7 +1743,11 @@ intelCreateBuffer(__DRIscreen *dri_screen, fb->Visual.samples = num_samples; } - if (mesaVis->redBits == 10 && mesaVis->alphaBits > 0) { + if (mesaVis->redBits == 16 && mesaVis->alphaBits > 0 && mesaVis->floatMode) { + rgbFormat = MESA_FORMAT_RGBA_FLOAT16; + } else if (mesaVis->redBits == 16 && mesaVis->floatMode) { + rgbFormat = MESA_FORMAT_RGBX_FLOAT16; + } else if (mesaVis->redBits == 10 && mesaVis->alphaBits > 0) { rgbFormat = mesaVis->redMask == 0x3ff00000 ? MESA_FORMAT_B10G10R10A2_UNORM : MESA_FORMAT_R10G10B10A2_UNORM; } else if (mesaVis->redBits == 10) { @@ -1883,7 +1906,17 @@ intel_init_bufmgr(struct intel_screen *screen) if (getenv("INTEL_NO_HW") != NULL) screen->no_hw = true; - screen->bufmgr = brw_bufmgr_init(&screen->devinfo, dri_screen->fd); + bool bo_reuse = false; + int bo_reuse_mode = driQueryOptioni(&screen->optionCache, "bo_reuse"); + switch (bo_reuse_mode) { + case DRI_CONF_BO_REUSE_DISABLED: + break; + case DRI_CONF_BO_REUSE_ALL: + bo_reuse = true; + break; + } + + screen->bufmgr = brw_bufmgr_init(&screen->devinfo, dri_screen->fd, bo_reuse); if (screen->bufmgr == NULL) { fprintf(stderr, "[%s:%u] Error initializing buffer manager.\n", __func__, __LINE__); @@ -2138,6 +2171,45 @@ intel_loader_get_cap(const __DRIscreen *dri_screen, enum dri_loader_cap cap) return 0; } +static bool +intel_allowed_format(__DRIscreen *dri_screen, mesa_format format) +{ + struct intel_screen *screen = dri_screen->driverPrivate; + + /* Expose only BGRA ordering if the loader doesn't support RGBA ordering. */ + bool allow_rgba_ordering = intel_loader_get_cap(dri_screen, DRI_LOADER_CAP_RGBA_ORDERING); + if (!allow_rgba_ordering && + (format == MESA_FORMAT_R8G8B8A8_UNORM || + format == MESA_FORMAT_R8G8B8X8_UNORM || + format == MESA_FORMAT_R8G8B8A8_SRGB)) + return false; + + /* Shall we expose 10 bpc formats? */ + bool allow_rgb10_configs = driQueryOptionb(&screen->optionCache, + "allow_rgb10_configs"); + if (!allow_rgb10_configs && + (format == MESA_FORMAT_B10G10R10A2_UNORM || + format == MESA_FORMAT_B10G10R10X2_UNORM)) + return false; + + /* Shall we expose 565 formats? */ + bool allow_rgb565_configs = driQueryOptionb(&screen->optionCache, + "allow_rgb565_configs"); + if (!allow_rgb565_configs && format == MESA_FORMAT_B5G6R5_UNORM) + return false; + + /* Shall we expose fp16 formats? */ + bool allow_fp16_configs = driQueryOptionb(&screen->optionCache, + "allow_fp16_configs"); + allow_fp16_configs &= intel_loader_get_cap(dri_screen, DRI_LOADER_CAP_FP16); + if (!allow_fp16_configs && + (format == MESA_FORMAT_RGBA_FLOAT16 || + format == MESA_FORMAT_RGBX_FLOAT16)) + return false; + + return true; +} + static __DRIconfig** intel_screen_make_configs(__DRIscreen *dri_screen) { @@ -2152,6 +2224,9 @@ intel_screen_make_configs(__DRIscreen *dri_screen) MESA_FORMAT_B10G10R10A2_UNORM, MESA_FORMAT_B10G10R10X2_UNORM, + MESA_FORMAT_RGBA_FLOAT16, + MESA_FORMAT_RGBX_FLOAT16, + /* The 32-bit RGBA format must not precede the 32-bit BGRA format. * Likewise for RGBX and BGRX. Otherwise, the GLX client and the GLX * server may disagree on which format the GLXFBConfig represents, @@ -2188,16 +2263,7 @@ intel_screen_make_configs(__DRIscreen *dri_screen) uint8_t depth_bits[4], stencil_bits[4]; __DRIconfig **configs = NULL; - /* Expose only BGRA ordering if the loader doesn't support RGBA ordering. */ - unsigned num_formats; - if (intel_loader_get_cap(dri_screen, DRI_LOADER_CAP_RGBA_ORDERING)) - num_formats = ARRAY_SIZE(formats); - else - num_formats = ARRAY_SIZE(formats) - 3; /* all - RGBA_ORDERING formats */ - - /* Shall we expose 10 bpc formats? */ - bool allow_rgb10_configs = driQueryOptionb(&screen->optionCache, - "allow_rgb10_configs"); + unsigned num_formats = ARRAY_SIZE(formats); /* Generate singlesample configs, each without accumulation buffer * and with EGL_MUTABLE_RENDER_BUFFER_BIT_KHR. @@ -2206,9 +2272,7 @@ intel_screen_make_configs(__DRIscreen *dri_screen) __DRIconfig **new_configs; int num_depth_stencil_bits = 2; - if (!allow_rgb10_configs && - (formats[i] == MESA_FORMAT_B10G10R10A2_UNORM || - formats[i] == MESA_FORMAT_B10G10R10X2_UNORM)) + if (!intel_allowed_format(dri_screen, formats[i])) continue; /* Starting with DRI2 protocol version 1.1 we can request a depth/stencil @@ -2248,9 +2312,7 @@ intel_screen_make_configs(__DRIscreen *dri_screen) for (unsigned i = 0; i < num_formats; i++) { __DRIconfig **new_configs; - if (!allow_rgb10_configs && - (formats[i] == MESA_FORMAT_B10G10R10A2_UNORM || - formats[i] == MESA_FORMAT_B10G10R10X2_UNORM)) + if (!intel_allowed_format(dri_screen, formats[i])) continue; if (formats[i] == MESA_FORMAT_B5G6R5_UNORM) { @@ -2286,9 +2348,7 @@ intel_screen_make_configs(__DRIscreen *dri_screen) if (devinfo->gen < 6) break; - if (!allow_rgb10_configs && - (formats[i] == MESA_FORMAT_B10G10R10A2_UNORM || - formats[i] == MESA_FORMAT_B10G10R10X2_UNORM)) + if (!intel_allowed_format(dri_screen, formats[i])) continue; __DRIconfig **new_configs; @@ -2356,7 +2416,7 @@ set_max_gl_versions(struct intel_screen *screen) case 10: case 9: case 8: - dri_screen->max_gl_core_version = 45; + dri_screen->max_gl_core_version = 46; dri_screen->max_gl_compat_version = 30; dri_screen->max_gl_es1_version = 11; dri_screen->max_gl_es2_version = has_astc ? 32 : 31; @@ -2392,28 +2452,6 @@ set_max_gl_versions(struct intel_screen *screen) } } -/** - * Return the revision (generally the revid field of the PCI header) of the - * graphics device. - */ -int -intel_device_get_revision(int fd) -{ - struct drm_i915_getparam gp; - int revision; - int ret; - - memset(&gp, 0, sizeof(gp)); - gp.param = I915_PARAM_REVISION; - gp.value = &revision; - - ret = drmCommandWriteRead(fd, DRM_I915_GETPARAM, &gp, sizeof(gp)); - if (ret) - revision = -1; - - return revision; -} - static void shader_debug_log_mesa(void *data, const char *fmt, ...) { @@ -2422,10 +2460,10 @@ shader_debug_log_mesa(void *data, const char *fmt, ...) va_start(args, fmt); GLuint msg_id = 0; - _mesa_gl_vdebug(&brw->ctx, &msg_id, - MESA_DEBUG_SOURCE_SHADER_COMPILER, - MESA_DEBUG_TYPE_OTHER, - MESA_DEBUG_SEVERITY_NOTIFICATION, fmt, args); + _mesa_gl_vdebugf(&brw->ctx, &msg_id, + MESA_DEBUG_SOURCE_SHADER_COMPILER, + MESA_DEBUG_TYPE_OTHER, + MESA_DEBUG_SEVERITY_NOTIFICATION, fmt, args); va_end(args); } @@ -2446,10 +2484,10 @@ shader_perf_log_mesa(void *data, const char *fmt, ...) if (brw->perf_debug) { GLuint msg_id = 0; - _mesa_gl_vdebug(&brw->ctx, &msg_id, - MESA_DEBUG_SOURCE_SHADER_COMPILER, - MESA_DEBUG_TYPE_PERFORMANCE, - MESA_DEBUG_SEVERITY_MEDIUM, fmt, args); + _mesa_gl_vdebugf(&brw->ctx, &msg_id, + MESA_DEBUG_SOURCE_SHADER_COMPILER, + MESA_DEBUG_TYPE_PERFORMANCE, + MESA_DEBUG_SEVERITY_MEDIUM, fmt, args); } va_end(args); } @@ -2486,26 +2524,27 @@ __DRIconfig **intelInitScreen2(__DRIscreen *dri_screen) driParseOptionInfo(&options, brw_config_options.xml); driParseConfigFiles(&screen->optionCache, &options, dri_screen->myNum, - "i965", NULL); + "i965", NULL, NULL, 0); driDestroyOptionCache(&options); screen->driScrnPriv = dri_screen; dri_screen->driverPrivate = (void *) screen; - screen->deviceID = gen_get_pci_device_id_override(); - if (screen->deviceID < 0) - screen->deviceID = intel_get_integer(screen, I915_PARAM_CHIPSET_ID); - else - screen->no_hw = true; + if (!gen_get_device_info_from_fd(dri_screen->fd, &screen->devinfo)) + return NULL; + + const struct gen_device_info *devinfo = &screen->devinfo; + screen->deviceID = devinfo->chipset_id; + screen->no_hw = devinfo->no_hw; - if (!gen_get_device_info(screen->deviceID, &screen->devinfo)) + if (devinfo->gen >= 12) { + fprintf(stderr, "gen12 and newer are not supported on i965\n"); return NULL; + } if (!intel_init_bufmgr(screen)) return NULL; - const struct gen_device_info *devinfo = &screen->devinfo; - brw_process_intel_debug_variable(); if ((INTEL_DEBUG & DEBUG_SHADER_TIME) && devinfo->gen < 7) {