X-Git-Url: https://git.libre-soc.org/?a=blobdiff_plain;f=src%2Fmesa%2Fdrivers%2Fdri%2Fi965%2Fintel_screen.c;h=825a7c170cc04a743802e37200971d291eac33bd;hb=63c313de84afa9ee65f5d98e1c843ace3a5c9f21;hp=778d5008503fdf3ba6d9c28c5eccc52ed3054fd7;hpb=ea2cac01e875a9953496c03057480fc3bf7fbc0e;p=mesa.git diff --git a/src/mesa/drivers/dri/i965/intel_screen.c b/src/mesa/drivers/dri/i965/intel_screen.c index 778d5008503..825a7c170cc 100644 --- a/src/mesa/drivers/dri/i965/intel_screen.c +++ b/src/mesa/drivers/dri/i965/intel_screen.c @@ -1,5 +1,4 @@ -/************************************************************************** - * +/* * Copyright 2003 VMware, Inc. * All Rights Reserved. * @@ -7,7 +6,7 @@ * copy of this software and associated documentation files (the * "Software"), to deal in the Software without restriction, including * without limitation the rights to use, copy, modify, merge, publish, - * distribute, sub license, and/or sell copies of the Software, and to + * distribute, sublicense, and/or sell copies of the Software, and to * permit persons to whom the Software is furnished to do so, subject to * the following conditions: * @@ -17,18 +16,16 @@ * * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS * OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF - * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT. + * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. * IN NO EVENT SHALL VMWARE AND/OR ITS SUPPLIERS BE LIABLE FOR * ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, * TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE * SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. - * - **************************************************************************/ + */ #include #include #include -#include "main/glheader.h" #include "main/context.h" #include "main/framebuffer.h" #include "main/renderbuffer.h" @@ -37,7 +34,9 @@ #include "main/fbobject.h" #include "main/version.h" #include "swrast/s_renderbuffer.h" -#include "glsl/ralloc.h" +#include "util/ralloc.h" +#include "brw_shader.h" +#include "glsl/nir/nir.h" #include "utils.h" #include "xmlpool.h" @@ -61,10 +60,6 @@ DRI_CONF_BEGIN DRI_CONF_OPT_BEGIN_B(hiz, "true") DRI_CONF_DESC(en, "Enable Hierarchical Z on gen6+") DRI_CONF_OPT_END - - DRI_CONF_OPT_BEGIN_B(disable_derivative_optimization, "false") - DRI_CONF_DESC(en, "Derivatives with finer granularity by default") - DRI_CONF_OPT_END DRI_CONF_SECTION_END DRI_CONF_SECTION_QUALITY @@ -84,6 +79,7 @@ DRI_CONF_BEGIN DRI_CONF_FORCE_GLSL_EXTENSIONS_WARN("false") DRI_CONF_DISABLE_GLSL_LINE_CONTINUATIONS("false") DRI_CONF_DISABLE_BLEND_FUNC_EXTENDED("false") + DRI_CONF_ALLOW_GLSL_EXTENSION_DIRECTIVE_MIDSHADER("false") DRI_CONF_OPT_BEGIN_B(shader_precompile, "true") DRI_CONF_DESC(en, "Perform code generation at shader link time.") @@ -95,12 +91,11 @@ DRI_CONF_END #include "intel_batchbuffer.h" #include "intel_buffers.h" #include "intel_bufmgr.h" -#include "intel_chipset.h" #include "intel_fbo.h" #include "intel_mipmap_tree.h" #include "intel_screen.h" #include "intel_tex.h" -#include "intel_regions.h" +#include "intel_image.h" #include "brw_context.h" @@ -124,7 +119,7 @@ aub_dump_bmp(struct gl_context *ctx) { struct gl_framebuffer *fb = ctx->DrawBuffer; - for (int i = 0; i < fb->_NumColorDrawBuffers; i++) { + for (unsigned i = 0; i < fb->_NumColorDrawBuffers; i++) { struct intel_renderbuffer *irb = intel_renderbuffer(fb->_ColorDrawBuffers[i]); @@ -140,14 +135,13 @@ aub_dump_bmp(struct gl_context *ctx) continue; } - assert(irb->mt->region->pitch % irb->mt->region->cpp == 0); - drm_intel_gem_bo_aub_dump_bmp(irb->mt->region->bo, + drm_intel_gem_bo_aub_dump_bmp(irb->mt->bo, irb->draw_x, irb->draw_y, irb->Base.Base.Width, irb->Base.Base.Height, format, - irb->mt->region->pitch, + irb->mt->pitch, 0); } } @@ -179,10 +173,10 @@ intel_dri2_flush_with_flags(__DRIcontext *cPriv, if (flags & __DRI2_FLUSH_DRAWABLE) intel_resolve_for_dri2_flush(brw, dPriv); - if (reason == __DRI2_THROTTLE_SWAPBUFFER || - reason == __DRI2_THROTTLE_FLUSHFRONT) { - brw->need_throttle = true; - } + if (reason == __DRI2_THROTTLE_SWAPBUFFER) + brw->need_swap_throttle = true; + if (reason == __DRI2_THROTTLE_FLUSHFRONT) + brw->need_flush_throttle = true; intel_batchbuffer_flush(brw); @@ -217,15 +211,27 @@ static struct intel_image_format intel_image_formats[] = { { __DRI_IMAGE_FOURCC_ARGB8888, __DRI_IMAGE_COMPONENTS_RGBA, 1, { { 0, 0, 0, __DRI_IMAGE_FORMAT_ARGB8888, 4 } } }, + { __DRI_IMAGE_FOURCC_ABGR8888, __DRI_IMAGE_COMPONENTS_RGBA, 1, + { { 0, 0, 0, __DRI_IMAGE_FORMAT_ABGR8888, 4 } } }, + { __DRI_IMAGE_FOURCC_SARGB8888, __DRI_IMAGE_COMPONENTS_RGBA, 1, { { 0, 0, 0, __DRI_IMAGE_FORMAT_SARGB8, 4 } } }, { __DRI_IMAGE_FOURCC_XRGB8888, __DRI_IMAGE_COMPONENTS_RGB, 1, { { 0, 0, 0, __DRI_IMAGE_FORMAT_XRGB8888, 4 }, } }, + { __DRI_IMAGE_FOURCC_XBGR8888, __DRI_IMAGE_COMPONENTS_RGB, 1, + { { 0, 0, 0, __DRI_IMAGE_FORMAT_XBGR8888, 4 }, } }, + { __DRI_IMAGE_FOURCC_RGB565, __DRI_IMAGE_COMPONENTS_RGB, 1, { { 0, 0, 0, __DRI_IMAGE_FORMAT_RGB565, 2 } } }, + { __DRI_IMAGE_FOURCC_R8, __DRI_IMAGE_COMPONENTS_R, 1, + { { 0, 0, 0, __DRI_IMAGE_FORMAT_R8, 1 }, } }, + + { __DRI_IMAGE_FOURCC_GR88, __DRI_IMAGE_COMPONENTS_RG, 1, + { { 0, 0, 0, __DRI_IMAGE_FORMAT_GR88, 2 }, } }, + { __DRI_IMAGE_FOURCC_YUV410, __DRI_IMAGE_COMPONENTS_Y_U_V, 3, { { 0, 0, 0, __DRI_IMAGE_FORMAT_R8, 1 }, { 1, 2, 2, __DRI_IMAGE_FORMAT_R8, 1 }, @@ -272,6 +278,18 @@ static struct intel_image_format intel_image_formats[] = { { 0, 1, 0, __DRI_IMAGE_FORMAT_ARGB8888, 4 } } } }; +static void +intel_image_warn_if_unaligned(__DRIimage *image, const char *func) +{ + uint32_t tiling, swizzle; + drm_intel_bo_get_tiling(image->bo, &tiling, &swizzle); + + if (tiling != I915_TILING_NONE && (image->offset & 0xfff)) { + _mesa_warning(NULL, "%s: offset 0x%08x not on tile boundary", + func, image->offset); + } +} + static struct intel_image_format * intel_image_format_lookup(int fourcc) { @@ -287,6 +305,17 @@ intel_image_format_lookup(int fourcc) return f; } +static boolean intel_lookup_fourcc(int dri_format, int *fourcc) +{ + for (unsigned i = 0; i < ARRAY_SIZE(intel_image_formats); i++) { + if (intel_image_formats[i].planes[0].dri_format == dri_format) { + *fourcc = intel_image_formats[i].fourcc; + return true; + } + } + return false; +} + static __DRIimage * intel_allocate_image(int dri_format, void *loaderPrivate) { @@ -313,7 +342,7 @@ intel_allocate_image(int dri_format, void *loaderPrivate) } /** - * Sets up a DRIImage structure to point to our shared image in a region + * Sets up a DRIImage structure to point to a slice out of a miptree. */ static void intel_setup_image_from_mipmap_tree(struct brw_context *brw, __DRIimage *image, @@ -326,22 +355,15 @@ intel_setup_image_from_mipmap_tree(struct brw_context *brw, __DRIimage *image, image->width = minify(mt->physical_width0, level - mt->first_level); image->height = minify(mt->physical_height0, level - mt->first_level); + image->pitch = mt->pitch; image->offset = intel_miptree_get_tile_offsets(mt, level, zoffset, &image->tile_x, &image->tile_y); - intel_region_reference(&image->region, mt->region); -} - -static void -intel_setup_image_from_dimensions(__DRIimage *image) -{ - image->width = image->region->width; - image->height = image->region->height; - image->tile_x = 0; - image->tile_y = 0; - image->has_depthstencil = false; + drm_intel_bo_unreference(image->bo); + image->bo = mt->bo; + drm_intel_bo_reference(mt->bo); } static __DRIimage * @@ -361,17 +383,18 @@ intel_create_image_from_name(__DRIscreen *screen, cpp = 1; else cpp = _mesa_get_format_bytes(image->format); - image->region = intel_region_alloc_for_handle(intelScreen, - cpp, width, height, - pitch * cpp, name, "image"); - if (image->region == NULL) { + + image->width = width; + image->height = height; + image->pitch = pitch * cpp; + image->bo = drm_intel_bo_gem_create_from_name(intelScreen->bufmgr, "image", + name); + if (!image->bo) { free(image); return NULL; } - intel_setup_image_from_dimensions(image); - - return image; + return image; } static __DRIimage * @@ -400,8 +423,12 @@ intel_create_image_from_renderbuffer(__DRIcontext *context, image->format = rb->Format; image->offset = 0; image->data = loaderPrivate; - intel_region_reference(&image->region, irb->mt->region); - intel_setup_image_from_dimensions(image); + drm_intel_bo_unreference(image->bo); + image->bo = irb->mt->bo; + drm_intel_bo_reference(irb->mt->bo); + image->width = rb->Width; + image->height = rb->Height; + image->pitch = irb->mt->pitch; image->dri_format = driGLFormatToImageFormat(image->format); image->has_depthstencil = irb->mt->stencil_mt? true : false; @@ -472,8 +499,8 @@ intel_create_image_from_texture(__DRIcontext *context, int target, static void intel_destroy_image(__DRIimage *image) { - intel_region_release(&image->region); - free(image); + drm_intel_bo_unreference(image->bo); + free(image); } static __DRIimage * @@ -486,6 +513,7 @@ intel_create_image(__DRIscreen *screen, struct intel_screen *intelScreen = screen->driverPrivate; uint32_t tiling; int cpp; + unsigned long pitch; tiling = I915_TILING_X; if (use & __DRI_IMAGE_USE_CURSOR) { @@ -502,14 +530,16 @@ intel_create_image(__DRIscreen *screen, return NULL; cpp = _mesa_get_format_bytes(image->format); - image->region = - intel_region_alloc(intelScreen, tiling, cpp, width, height, true); - if (image->region == NULL) { + image->bo = drm_intel_bo_alloc_tiled(intelScreen->bufmgr, "image", + width, height, cpp, &tiling, + &pitch, 0); + if (image->bo == NULL) { free(image); return NULL; } - - intel_setup_image_from_dimensions(image); + image->width = width; + image->height = height; + image->pitch = pitch; return image; } @@ -519,21 +549,21 @@ intel_query_image(__DRIimage *image, int attrib, int *value) { switch (attrib) { case __DRI_IMAGE_ATTRIB_STRIDE: - *value = image->region->pitch; + *value = image->pitch; return true; case __DRI_IMAGE_ATTRIB_HANDLE: - *value = image->region->bo->handle; + *value = image->bo->handle; return true; case __DRI_IMAGE_ATTRIB_NAME: - return intel_region_flink(image->region, (uint32_t *) value); + return !drm_intel_bo_flink(image->bo, (uint32_t *) value); case __DRI_IMAGE_ATTRIB_FORMAT: *value = image->dri_format; return true; case __DRI_IMAGE_ATTRIB_WIDTH: - *value = image->region->width; + *value = image->width; return true; case __DRI_IMAGE_ATTRIB_HEIGHT: - *value = image->region->height; + *value = image->height; return true; case __DRI_IMAGE_ATTRIB_COMPONENTS: if (image->planar_format == NULL) @@ -541,9 +571,17 @@ intel_query_image(__DRIimage *image, int attrib, int *value) *value = image->planar_format->components; return true; case __DRI_IMAGE_ATTRIB_FD: - if (drm_intel_bo_gem_export_to_prime(image->region->bo, value) == 0) + if (drm_intel_bo_gem_export_to_prime(image->bo, value) == 0) + return true; + return false; + case __DRI_IMAGE_ATTRIB_FOURCC: + if (intel_lookup_fourcc(image->dri_format, value)) return true; return false; + case __DRI_IMAGE_ATTRIB_NUM_PLANES: + *value = 1; + return true; + default: return false; } @@ -558,12 +596,8 @@ intel_dup_image(__DRIimage *orig_image, void *loaderPrivate) if (image == NULL) return NULL; - intel_region_reference(&image->region, orig_image->region); - if (image->region == NULL) { - free(image); - return NULL; - } - + drm_intel_bo_reference(orig_image->bo); + image->bo = orig_image->bo; image->internal_format = orig_image->internal_format; image->planar_format = orig_image->planar_format; image->dri_format = orig_image->dri_format; @@ -571,6 +605,7 @@ intel_dup_image(__DRIimage *orig_image, void *loaderPrivate) image->offset = orig_image->offset; image->width = orig_image->width; image->height = orig_image->height; + image->pitch = orig_image->pitch; image->tile_x = orig_image->tile_x; image->tile_y = orig_image->tile_y; image->has_depthstencil = orig_image->has_depthstencil; @@ -586,7 +621,7 @@ static GLboolean intel_validate_usage(__DRIimage *image, unsigned int use) { if (use & __DRI_IMAGE_USE_CURSOR) { - if (image->region->width != 64 || image->region->height != 64) + if (image->width != 64 || image->height != 64) return GL_FALSE; } @@ -655,13 +690,16 @@ intel_create_image_from_fds(__DRIscreen *screen, if (image == NULL) return NULL; - image->region = intel_region_alloc_for_fd(intelScreen, - f->planes[0].cpp, width, height, strides[0], - height * strides[0], fds[0], "image"); - if (image->region == NULL) { + image->bo = drm_intel_bo_gem_create_from_prime(intelScreen->bufmgr, + fds[0], + height * strides[0]); + if (image->bo == NULL) { free(image); return NULL; } + image->width = width; + image->height = height; + image->pitch = strides[0]; image->planar_format = f; for (i = 0; i < f->nplanes; i++) { @@ -672,13 +710,9 @@ intel_create_image_from_fds(__DRIscreen *screen, if (f->nplanes == 1) { image->offset = image->offsets[0]; - if (image->region->tiling != I915_TILING_NONE && (image->offset & 0xfff)) - _mesa_warning(NULL, - "intel_create_image_from_fds: offset not on tile boundary"); + intel_image_warn_if_unaligned(image, __func__); } - intel_setup_image_from_dimensions(image); - return image; } @@ -742,8 +776,8 @@ intel_from_planar(__DRIimage *parent, int plane, void *loaderPrivate) if (plane >= f->nplanes) return NULL; - width = parent->region->width >> f->planes[plane].width_shift; - height = parent->region->height >> f->planes[plane].height_shift; + width = parent->width >> f->planes[plane].width_shift; + height = parent->height >> f->planes[plane].height_shift; dri_format = f->planes[plane].dri_format; index = f->planes[plane].buffer_index; offset = parent->offsets[index]; @@ -753,38 +787,27 @@ intel_from_planar(__DRIimage *parent, int plane, void *loaderPrivate) if (image == NULL) return NULL; - if (offset + height * stride > parent->region->bo->size) { + if (offset + height * stride > parent->bo->size) { _mesa_warning(NULL, "intel_create_sub_image: subimage out of bounds"); free(image); return NULL; } - image->region = calloc(sizeof(*image->region), 1); - if (image->region == NULL) { - free(image); - return NULL; - } + image->bo = parent->bo; + drm_intel_bo_reference(parent->bo); - image->region->cpp = _mesa_get_format_bytes(image->format); - image->region->width = width; - image->region->height = height; - image->region->pitch = stride; - image->region->refcount = 1; - image->region->bo = parent->region->bo; - drm_intel_bo_reference(image->region->bo); - image->region->tiling = parent->region->tiling; + image->width = width; + image->height = height; + image->pitch = stride; image->offset = offset; - intel_setup_image_from_dimensions(image); - if (offset & 0xfff) - _mesa_warning(NULL, - "intel_create_sub_image: offset not on tile boundary"); + intel_image_warn_if_unaligned(image, __func__); return image; } static const __DRIimageExtension intelImageExtension = { - .base = { __DRI_IMAGE, 8 }, + .base = { __DRI_IMAGE, 11 }, .createImageFromName = intel_create_image_from_name, .createImageFromRenderbuffer = intel_create_image_from_renderbuffer, @@ -797,7 +820,9 @@ static const __DRIimageExtension intelImageExtension = { .fromPlanar = intel_from_planar, .createImageFromTexture = intel_create_image_from_texture, .createImageFromFds = intel_create_image_from_fds, - .createImageFromDmaBufs = intel_create_image_from_dma_bufs + .createImageFromDmaBufs = intel_create_image_from_dma_bufs, + .blitImage = NULL, + .getCapabilities = NULL }; static int @@ -847,10 +872,6 @@ brw_query_renderer_integer(__DRIscreen *psp, int param, unsigned int *value) case __DRI2_RENDERER_UNIFIED_MEMORY_ARCHITECTURE: value[0] = 1; return 0; - case __DRI2_RENDERER_PREFERRED_PROFILE: - value[0] = (psp->max_gl_core_version != 0) - ? (1U << __DRI_API_OPENGL_CORE) : (1U << __DRI_API_OPENGL); - return 0; default: return driQueryRendererIntegerCommon(psp, param, value); } @@ -891,6 +912,7 @@ static const __DRIrobustnessExtension dri2Robustness = { static const __DRIextension *intelScreenExtensions[] = { &intelTexBufferExtension.base, + &intelFenceExtension.base, &intelFlushExtension.base, &intelImageExtension.base, &intelRendererQueryExtension.base, @@ -900,6 +922,7 @@ static const __DRIextension *intelScreenExtensions[] = { static const __DRIextension *intelRobustScreenExtensions[] = { &intelTexBufferExtension.base, + &intelFenceExtension.base, &intelFlushExtension.base, &intelImageExtension.base, &intelRendererQueryExtension.base, @@ -976,14 +999,13 @@ intelCreateBuffer(__DRIscreen * driScrnPriv, fb->Visual.samples = num_samples; } - if (mesaVis->redBits == 5) + if (mesaVis->redBits == 5) { rgbFormat = MESA_FORMAT_B5G6R5_UNORM; - else if (mesaVis->sRGBCapable) - rgbFormat = MESA_FORMAT_B8G8R8A8_SRGB; - else if (mesaVis->alphaBits == 0) - rgbFormat = MESA_FORMAT_B8G8R8X8_UNORM; - else { - rgbFormat = MESA_FORMAT_B8G8R8A8_SRGB; + } else { + if (mesaVis->alphaBits == 0) + rgbFormat = MESA_FORMAT_B8G8R8X8_SRGB; + else + rgbFormat = MESA_FORMAT_B8G8R8A8_SRGB; fb->Visual.sRGBCapable = true; } @@ -1102,6 +1124,50 @@ intel_detect_swizzling(struct intel_screen *screen) return true; } +static int +intel_detect_timestamp(struct intel_screen *screen) +{ + uint64_t dummy = 0, last = 0; + int upper, lower, loops; + + /* On 64bit systems, some old kernels trigger a hw bug resulting in the + * TIMESTAMP register being shifted and the low 32bits always zero. + * + * More recent kernels offer an interface to read the full 36bits + * everywhere. + */ + if (drm_intel_reg_read(screen->bufmgr, TIMESTAMP | 1, &dummy) == 0) + return 3; + + /* Determine if we have a 32bit or 64bit kernel by inspecting the + * upper 32bits for a rapidly changing timestamp. + */ + if (drm_intel_reg_read(screen->bufmgr, TIMESTAMP, &last)) + return 0; + + upper = lower = 0; + for (loops = 0; loops < 10; loops++) { + /* The TIMESTAMP should change every 80ns, so several round trips + * through the kernel should be enough to advance it. + */ + if (drm_intel_reg_read(screen->bufmgr, TIMESTAMP, &dummy)) + return 0; + + upper += (dummy >> 32) != (last >> 32); + if (upper > 1) /* beware 32bit counter overflow */ + return 2; /* upper dword holds the low 32bits of the timestamp */ + + lower += (dummy & 0xffffffff) != (last & 0xffffffff); + if (lower > 1) + return 1; /* timestamp is unshifted */ + + last = dummy; + } + + /* No advancement? No timestamp! */ + return 0; +} + /** * Return array of MSAA modes supported by the hardware. The array is * zero-terminated and sorted in decreasing order. @@ -1109,12 +1175,15 @@ intel_detect_swizzling(struct intel_screen *screen) const int* intel_supported_msaa_modes(const struct intel_screen *screen) { + static const int gen9_modes[] = {16, 8, 4, 2, 0, -1}; static const int gen8_modes[] = {8, 4, 2, 0, -1}; static const int gen7_modes[] = {8, 4, 0, -1}; static const int gen6_modes[] = {4, 0, -1}; static const int gen4_modes[] = {0, -1}; - if (screen->devinfo->gen >= 8) { + if (screen->devinfo->gen >= 9) { + return gen9_modes; + } else if (screen->devinfo->gen >= 8) { return gen8_modes; } else if (screen->devinfo->gen >= 7) { return gen7_modes; @@ -1130,7 +1199,8 @@ intel_screen_make_configs(__DRIscreen *dri_screen) { static const mesa_format formats[] = { MESA_FORMAT_B5G6R5_UNORM, - MESA_FORMAT_B8G8R8A8_UNORM + MESA_FORMAT_B8G8R8A8_UNORM, + MESA_FORMAT_B8G8R8X8_UNORM }; /* GLX_SWAP_COPY_OML is not supported due to page flipping. */ @@ -1147,7 +1217,7 @@ intel_screen_make_configs(__DRIscreen *dri_screen) __DRIconfig **configs = NULL; /* Generate singlesample configs without accumulation buffer. */ - for (int i = 0; i < ARRAY_SIZE(formats); i++) { + for (unsigned i = 0; i < ARRAY_SIZE(formats); i++) { __DRIconfig **new_configs; int num_depth_stencil_bits = 2; @@ -1184,7 +1254,7 @@ intel_screen_make_configs(__DRIscreen *dri_screen) /* Generate the minimum possible set of configs that include an * accumulation buffer. */ - for (int i = 0; i < ARRAY_SIZE(formats); i++) { + for (unsigned i = 0; i < ARRAY_SIZE(formats); i++) { __DRIconfig **new_configs; if (formats[i] == MESA_FORMAT_B5G6R5_UNORM) { @@ -1216,7 +1286,7 @@ intel_screen_make_configs(__DRIscreen *dri_screen) * supported. Singlebuffer configs are not supported because no one wants * them. */ - for (int i = 0; i < ARRAY_SIZE(formats); i++) { + for (unsigned i = 0; i < ARRAY_SIZE(formats); i++) { if (devinfo->gen < 6) break; @@ -1266,15 +1336,11 @@ set_max_gl_versions(struct intel_screen *screen) __DRIscreen *psp = screen->driScrnPriv; switch (screen->devinfo->gen) { + case 9: case 8: case 7: - psp->max_gl_core_version = 33; - psp->max_gl_compat_version = 30; - psp->max_gl_es1_version = 11; - psp->max_gl_es2_version = 30; - break; case 6: - psp->max_gl_core_version = 31; + psp->max_gl_core_version = 33; psp->max_gl_compat_version = 30; psp->max_gl_es1_version = 11; psp->max_gl_es2_version = 30; @@ -1287,11 +1353,42 @@ set_max_gl_versions(struct intel_screen *screen) psp->max_gl_es2_version = 20; break; default: - assert(!"unrecognized intel_screen::gen"); - break; + unreachable("unrecognized intel_screen::gen"); } } +/** + * Return the revision (generally the revid field of the PCI header) of the + * graphics device. + * + * XXX: This function is useful to keep around even if it is not currently in + * use. It is necessary for new platforms and revision specific workarounds or + * features. Please don't remove it so that we know it at least continues to + * build. + */ +static __attribute__((__unused__)) int +brw_get_revision(int fd) +{ + struct drm_i915_getparam gp; + int revision; + int ret; + + memset(&gp, 0, sizeof(gp)); + gp.param = I915_PARAM_REVISION; + gp.value = &revision; + + ret = drmCommandWriteRead(fd, DRM_I915_GETPARAM, &gp, sizeof(gp)); + if (ret) + revision = -1; + + return revision; +} + +/* Drop when RS headers get pulled to libdrm */ +#ifndef I915_PARAM_HAS_RESOURCE_STREAMER +#define I915_PARAM_HAS_RESOURCE_STREAMER 36 +#endif + /** * This is the driver specific part of the createNewScreen entry point. * Called when using DRI2. @@ -1332,9 +1429,24 @@ __DRIconfig **intelInitScreen2(__DRIscreen *psp) if (!intelScreen->devinfo) return false; + brw_process_intel_debug_variable(); + + if (INTEL_DEBUG & DEBUG_BUFMGR) + dri_bufmgr_set_debug(intelScreen->bufmgr, true); + + if ((INTEL_DEBUG & DEBUG_SHADER_TIME) && intelScreen->devinfo->gen < 7) { + fprintf(stderr, + "shader_time debugging requires gen7 (Ivybridge) or better.\n"); + INTEL_DEBUG &= ~DEBUG_SHADER_TIME; + } + + if (INTEL_DEBUG & DEBUG_AUB) + drm_intel_bufmgr_gem_set_aub_dump(intelScreen->bufmgr, true); + intelScreen->hw_must_use_separate_stencil = intelScreen->devinfo->gen >= 7; intelScreen->hw_has_swizzling = intel_detect_swizzling(intelScreen); + intelScreen->hw_has_timestamp = intel_detect_timestamp(intelScreen); const char *force_msaa = getenv("INTEL_FORCE_MSAA"); if (force_msaa) { @@ -1367,18 +1479,34 @@ __DRIconfig **intelInitScreen2(__DRIscreen *psp) (ret != -1 || errno != EINVAL); } + struct drm_i915_getparam getparam; + getparam.param = I915_PARAM_CMD_PARSER_VERSION; + getparam.value = &intelScreen->cmd_parser_version; + const int ret = drmIoctl(psp->fd, DRM_IOCTL_I915_GETPARAM, &getparam); + if (ret == -1) + intelScreen->cmd_parser_version = 0; + psp->extensions = !intelScreen->has_context_reset_notification ? intelScreenExtensions : intelRobustScreenExtensions; - brw_fs_alloc_reg_sets(intelScreen); - brw_vec4_alloc_reg_set(intelScreen); + intelScreen->compiler = brw_compiler_create(intelScreen, + intelScreen->devinfo); + + if (intelScreen->devinfo->has_resource_streamer) { + int val = -1; + getparam.param = I915_PARAM_HAS_RESOURCE_STREAMER; + getparam.value = &val; + + drmIoctl(psp->fd, DRM_IOCTL_I915_GETPARAM, &getparam); + intelScreen->has_resource_streamer = val > 0; + } return (const __DRIconfig**) intel_screen_make_configs(psp); } struct intel_buffer { __DRIbuffer base; - struct intel_region *region; + drm_intel_bo *bo; }; static __DRIbuffer * @@ -1397,23 +1525,27 @@ intelAllocateBuffer(__DRIscreen *screen, return NULL; /* The front and back buffers are color buffers, which are X tiled. */ - intelBuffer->region = intel_region_alloc(intelScreen, - I915_TILING_X, - format / 8, - width, - height, - true); - - if (intelBuffer->region == NULL) { + uint32_t tiling = I915_TILING_X; + unsigned long pitch; + int cpp = format / 8; + intelBuffer->bo = drm_intel_bo_alloc_tiled(intelScreen->bufmgr, + "intelAllocateBuffer", + width, + height, + cpp, + &tiling, &pitch, + BO_ALLOC_FOR_RENDER); + + if (intelBuffer->bo == NULL) { free(intelBuffer); return NULL; } - intel_region_flink(intelBuffer->region, &intelBuffer->base.name); + drm_intel_bo_flink(intelBuffer->bo, &intelBuffer->base.name); intelBuffer->base.attachment = attachment; - intelBuffer->base.cpp = intelBuffer->region->cpp; - intelBuffer->base.pitch = intelBuffer->region->pitch; + intelBuffer->base.cpp = cpp; + intelBuffer->base.pitch = pitch; return &intelBuffer->base; } @@ -1423,7 +1555,7 @@ intelReleaseBuffer(__DRIscreen *screen, __DRIbuffer *buffer) { struct intel_buffer *intelBuffer = (struct intel_buffer *) buffer; - intel_region_release(&intelBuffer->region); + drm_intel_bo_unreference(intelBuffer->bo); free(intelBuffer); }