X-Git-Url: https://git.libre-soc.org/?a=blobdiff_plain;f=src%2Fmesa%2Fdrivers%2Fdri%2Fi965%2Fintel_screen.c;h=b7d3a408c1f41b0182c8079e48256c9711eb7c68;hb=272f9cfe6a19212354c89dc443959473ac5d398e;hp=1f9b0efa42f0087a8d0e43d22826415a5f4e5323;hpb=24952160fde9bdaaa6da88da1dfef8423b071466;p=mesa.git diff --git a/src/mesa/drivers/dri/i965/intel_screen.c b/src/mesa/drivers/dri/i965/intel_screen.c index 1f9b0efa42f..b7d3a408c1f 100644 --- a/src/mesa/drivers/dri/i965/intel_screen.c +++ b/src/mesa/drivers/dri/i965/intel_screen.c @@ -23,7 +23,7 @@ * SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. */ -#include +#include "drm-uapi/drm_fourcc.h" #include #include #include @@ -34,6 +34,7 @@ #include "main/hash.h" #include "main/fbobject.h" #include "main/version.h" +#include "main/glthread.h" #include "swrast/s_renderbuffer.h" #include "util/ralloc.h" #include "util/disk_cache.h" @@ -45,6 +46,8 @@ #include "util/disk_cache.h" #include "util/xmlpool.h" +#include "common/gen_defines.h" + static const __DRIconfigOptionsExtension brw_config_options = { .base = { __DRI_CONFIG_OPTIONS, 1 }, .xml = @@ -60,6 +63,7 @@ DRI_CONF_BEGIN DRI_CONF_DESC_END DRI_CONF_OPT_END DRI_CONF_MESA_NO_ERROR("false") + DRI_CONF_MESA_GLTHREAD("false") DRI_CONF_SECTION_END DRI_CONF_SECTION_QUALITY @@ -72,7 +76,6 @@ DRI_CONF_BEGIN DRI_CONF_SECTION_END DRI_CONF_SECTION_DEBUG - DRI_CONF_NO_RAST("false") DRI_CONF_ALWAYS_FLUSH_BATCH("false") DRI_CONF_ALWAYS_FLUSH_CACHE("false") DRI_CONF_DISABLE_THROTTLING("false") @@ -85,6 +88,7 @@ DRI_CONF_BEGIN DRI_CONF_ALLOW_GLSL_BUILTIN_VARIABLE_REDECLARATION("false") DRI_CONF_ALLOW_GLSL_CROSS_STAGE_INTERPOLATION_MISMATCH("false") DRI_CONF_ALLOW_HIGHER_COMPAT_VERSION("false") + DRI_CONF_FORCE_COMPAT_PROFILE("false") DRI_CONF_FORCE_GLSL_ABS_SQRT("false") DRI_CONF_OPT_BEGIN_B(shader_precompile, "true") @@ -95,6 +99,8 @@ DRI_CONF_BEGIN DRI_CONF_SECTION_MISCELLANEOUS DRI_CONF_GLSL_ZERO_INIT("false") DRI_CONF_ALLOW_RGB10_CONFIGS("false") + DRI_CONF_ALLOW_RGB565_CONFIGS("true") + DRI_CONF_ALLOW_FP16_CONFIGS("false") DRI_CONF_SECTION_END DRI_CONF_END }; @@ -110,7 +116,7 @@ DRI_CONF_END #include "brw_context.h" -#include "i915_drm.h" +#include "drm-uapi/i915_drm.h" /** * For debugging purposes, this returns a time in seconds. @@ -146,6 +152,8 @@ intel_dri2_flush_with_flags(__DRIcontext *cPriv, struct gl_context *ctx = &brw->ctx; + _mesa_glthread_finish(ctx); + FLUSH_VERTICES(ctx, 0); if (flags & __DRI2_FLUSH_DRAWABLE) @@ -182,103 +190,133 @@ static const struct __DRI2flushExtensionRec intelFlushExtension = { }; static const struct intel_image_format intel_image_formats[] = { - { __DRI_IMAGE_FOURCC_ARGB2101010, __DRI_IMAGE_COMPONENTS_RGBA, 1, + { DRM_FORMAT_ABGR16161616F, __DRI_IMAGE_COMPONENTS_RGBA, 1, + { { 0, 0, 0, __DRI_IMAGE_FORMAT_ABGR16161616F, 8 } } }, + + { DRM_FORMAT_XBGR16161616F, __DRI_IMAGE_COMPONENTS_RGB, 1, + { { 0, 0, 0, __DRI_IMAGE_FORMAT_XBGR16161616F, 8 } } }, + + { DRM_FORMAT_ARGB2101010, __DRI_IMAGE_COMPONENTS_RGBA, 1, { { 0, 0, 0, __DRI_IMAGE_FORMAT_ARGB2101010, 4 } } }, - { __DRI_IMAGE_FOURCC_XRGB2101010, __DRI_IMAGE_COMPONENTS_RGB, 1, + { DRM_FORMAT_XRGB2101010, __DRI_IMAGE_COMPONENTS_RGB, 1, { { 0, 0, 0, __DRI_IMAGE_FORMAT_XRGB2101010, 4 } } }, - { __DRI_IMAGE_FOURCC_ARGB8888, __DRI_IMAGE_COMPONENTS_RGBA, 1, + { DRM_FORMAT_ABGR2101010, __DRI_IMAGE_COMPONENTS_RGBA, 1, + { { 0, 0, 0, __DRI_IMAGE_FORMAT_ABGR2101010, 4 } } }, + + { DRM_FORMAT_XBGR2101010, __DRI_IMAGE_COMPONENTS_RGB, 1, + { { 0, 0, 0, __DRI_IMAGE_FORMAT_XBGR2101010, 4 } } }, + + { DRM_FORMAT_ARGB8888, __DRI_IMAGE_COMPONENTS_RGBA, 1, { { 0, 0, 0, __DRI_IMAGE_FORMAT_ARGB8888, 4 } } }, - { __DRI_IMAGE_FOURCC_ABGR8888, __DRI_IMAGE_COMPONENTS_RGBA, 1, + { DRM_FORMAT_ABGR8888, __DRI_IMAGE_COMPONENTS_RGBA, 1, { { 0, 0, 0, __DRI_IMAGE_FORMAT_ABGR8888, 4 } } }, { __DRI_IMAGE_FOURCC_SARGB8888, __DRI_IMAGE_COMPONENTS_RGBA, 1, { { 0, 0, 0, __DRI_IMAGE_FORMAT_SARGB8, 4 } } }, - { __DRI_IMAGE_FOURCC_XRGB8888, __DRI_IMAGE_COMPONENTS_RGB, 1, + { DRM_FORMAT_XRGB8888, __DRI_IMAGE_COMPONENTS_RGB, 1, { { 0, 0, 0, __DRI_IMAGE_FORMAT_XRGB8888, 4 }, } }, - { __DRI_IMAGE_FOURCC_XBGR8888, __DRI_IMAGE_COMPONENTS_RGB, 1, + { DRM_FORMAT_XBGR8888, __DRI_IMAGE_COMPONENTS_RGB, 1, { { 0, 0, 0, __DRI_IMAGE_FORMAT_XBGR8888, 4 }, } }, - { __DRI_IMAGE_FOURCC_ARGB1555, __DRI_IMAGE_COMPONENTS_RGBA, 1, + { DRM_FORMAT_ARGB1555, __DRI_IMAGE_COMPONENTS_RGBA, 1, { { 0, 0, 0, __DRI_IMAGE_FORMAT_ARGB1555, 2 } } }, - { __DRI_IMAGE_FOURCC_RGB565, __DRI_IMAGE_COMPONENTS_RGB, 1, + { DRM_FORMAT_RGB565, __DRI_IMAGE_COMPONENTS_RGB, 1, { { 0, 0, 0, __DRI_IMAGE_FORMAT_RGB565, 2 } } }, - { __DRI_IMAGE_FOURCC_R8, __DRI_IMAGE_COMPONENTS_R, 1, + { DRM_FORMAT_R8, __DRI_IMAGE_COMPONENTS_R, 1, { { 0, 0, 0, __DRI_IMAGE_FORMAT_R8, 1 }, } }, - { __DRI_IMAGE_FOURCC_R16, __DRI_IMAGE_COMPONENTS_R, 1, + { DRM_FORMAT_R16, __DRI_IMAGE_COMPONENTS_R, 1, { { 0, 0, 0, __DRI_IMAGE_FORMAT_R16, 1 }, } }, - { __DRI_IMAGE_FOURCC_GR88, __DRI_IMAGE_COMPONENTS_RG, 1, + { DRM_FORMAT_GR88, __DRI_IMAGE_COMPONENTS_RG, 1, { { 0, 0, 0, __DRI_IMAGE_FORMAT_GR88, 2 }, } }, - { __DRI_IMAGE_FOURCC_GR1616, __DRI_IMAGE_COMPONENTS_RG, 1, + { DRM_FORMAT_GR1616, __DRI_IMAGE_COMPONENTS_RG, 1, { { 0, 0, 0, __DRI_IMAGE_FORMAT_GR1616, 2 }, } }, - { __DRI_IMAGE_FOURCC_YUV410, __DRI_IMAGE_COMPONENTS_Y_U_V, 3, + { DRM_FORMAT_YUV410, __DRI_IMAGE_COMPONENTS_Y_U_V, 3, { { 0, 0, 0, __DRI_IMAGE_FORMAT_R8, 1 }, { 1, 2, 2, __DRI_IMAGE_FORMAT_R8, 1 }, { 2, 2, 2, __DRI_IMAGE_FORMAT_R8, 1 } } }, - { __DRI_IMAGE_FOURCC_YUV411, __DRI_IMAGE_COMPONENTS_Y_U_V, 3, + { DRM_FORMAT_YUV411, __DRI_IMAGE_COMPONENTS_Y_U_V, 3, { { 0, 0, 0, __DRI_IMAGE_FORMAT_R8, 1 }, { 1, 2, 0, __DRI_IMAGE_FORMAT_R8, 1 }, { 2, 2, 0, __DRI_IMAGE_FORMAT_R8, 1 } } }, - { __DRI_IMAGE_FOURCC_YUV420, __DRI_IMAGE_COMPONENTS_Y_U_V, 3, + { DRM_FORMAT_YUV420, __DRI_IMAGE_COMPONENTS_Y_U_V, 3, { { 0, 0, 0, __DRI_IMAGE_FORMAT_R8, 1 }, { 1, 1, 1, __DRI_IMAGE_FORMAT_R8, 1 }, { 2, 1, 1, __DRI_IMAGE_FORMAT_R8, 1 } } }, - { __DRI_IMAGE_FOURCC_YUV422, __DRI_IMAGE_COMPONENTS_Y_U_V, 3, + { DRM_FORMAT_YUV422, __DRI_IMAGE_COMPONENTS_Y_U_V, 3, { { 0, 0, 0, __DRI_IMAGE_FORMAT_R8, 1 }, { 1, 1, 0, __DRI_IMAGE_FORMAT_R8, 1 }, { 2, 1, 0, __DRI_IMAGE_FORMAT_R8, 1 } } }, - { __DRI_IMAGE_FOURCC_YUV444, __DRI_IMAGE_COMPONENTS_Y_U_V, 3, + { DRM_FORMAT_YUV444, __DRI_IMAGE_COMPONENTS_Y_U_V, 3, { { 0, 0, 0, __DRI_IMAGE_FORMAT_R8, 1 }, { 1, 0, 0, __DRI_IMAGE_FORMAT_R8, 1 }, { 2, 0, 0, __DRI_IMAGE_FORMAT_R8, 1 } } }, - { __DRI_IMAGE_FOURCC_YVU410, __DRI_IMAGE_COMPONENTS_Y_U_V, 3, + { DRM_FORMAT_YVU410, __DRI_IMAGE_COMPONENTS_Y_U_V, 3, { { 0, 0, 0, __DRI_IMAGE_FORMAT_R8, 1 }, { 2, 2, 2, __DRI_IMAGE_FORMAT_R8, 1 }, { 1, 2, 2, __DRI_IMAGE_FORMAT_R8, 1 } } }, - { __DRI_IMAGE_FOURCC_YVU411, __DRI_IMAGE_COMPONENTS_Y_U_V, 3, + { DRM_FORMAT_YVU411, __DRI_IMAGE_COMPONENTS_Y_U_V, 3, { { 0, 0, 0, __DRI_IMAGE_FORMAT_R8, 1 }, { 2, 2, 0, __DRI_IMAGE_FORMAT_R8, 1 }, { 1, 2, 0, __DRI_IMAGE_FORMAT_R8, 1 } } }, - { __DRI_IMAGE_FOURCC_YVU420, __DRI_IMAGE_COMPONENTS_Y_U_V, 3, + { DRM_FORMAT_YVU420, __DRI_IMAGE_COMPONENTS_Y_U_V, 3, { { 0, 0, 0, __DRI_IMAGE_FORMAT_R8, 1 }, { 2, 1, 1, __DRI_IMAGE_FORMAT_R8, 1 }, { 1, 1, 1, __DRI_IMAGE_FORMAT_R8, 1 } } }, - { __DRI_IMAGE_FOURCC_YVU422, __DRI_IMAGE_COMPONENTS_Y_U_V, 3, + { DRM_FORMAT_YVU422, __DRI_IMAGE_COMPONENTS_Y_U_V, 3, { { 0, 0, 0, __DRI_IMAGE_FORMAT_R8, 1 }, { 2, 1, 0, __DRI_IMAGE_FORMAT_R8, 1 }, { 1, 1, 0, __DRI_IMAGE_FORMAT_R8, 1 } } }, - { __DRI_IMAGE_FOURCC_YVU444, __DRI_IMAGE_COMPONENTS_Y_U_V, 3, + { DRM_FORMAT_YVU444, __DRI_IMAGE_COMPONENTS_Y_U_V, 3, { { 0, 0, 0, __DRI_IMAGE_FORMAT_R8, 1 }, { 2, 0, 0, __DRI_IMAGE_FORMAT_R8, 1 }, { 1, 0, 0, __DRI_IMAGE_FORMAT_R8, 1 } } }, - { __DRI_IMAGE_FOURCC_NV12, __DRI_IMAGE_COMPONENTS_Y_UV, 2, + { DRM_FORMAT_NV12, __DRI_IMAGE_COMPONENTS_Y_UV, 2, { { 0, 0, 0, __DRI_IMAGE_FORMAT_R8, 1 }, { 1, 1, 1, __DRI_IMAGE_FORMAT_GR88, 2 } } }, - { __DRI_IMAGE_FOURCC_NV16, __DRI_IMAGE_COMPONENTS_Y_UV, 2, + { DRM_FORMAT_P010, __DRI_IMAGE_COMPONENTS_Y_UV, 2, + { { 0, 0, 0, __DRI_IMAGE_FORMAT_R16, 2 }, + { 1, 1, 1, __DRI_IMAGE_FORMAT_GR1616, 4 } } }, + + { DRM_FORMAT_P012, __DRI_IMAGE_COMPONENTS_Y_UV, 2, + { { 0, 0, 0, __DRI_IMAGE_FORMAT_R16, 2 }, + { 1, 1, 1, __DRI_IMAGE_FORMAT_GR1616, 4 } } }, + + { DRM_FORMAT_P016, __DRI_IMAGE_COMPONENTS_Y_UV, 2, + { { 0, 0, 0, __DRI_IMAGE_FORMAT_R16, 2 }, + { 1, 1, 1, __DRI_IMAGE_FORMAT_GR1616, 4 } } }, + + { DRM_FORMAT_NV16, __DRI_IMAGE_COMPONENTS_Y_UV, 2, { { 0, 0, 0, __DRI_IMAGE_FORMAT_R8, 1 }, { 1, 1, 0, __DRI_IMAGE_FORMAT_GR88, 2 } } }, + { DRM_FORMAT_AYUV, __DRI_IMAGE_COMPONENTS_AYUV, 1, + { { 0, 0, 0, __DRI_IMAGE_FORMAT_ABGR8888, 4 } } }, + + { DRM_FORMAT_XYUV8888, __DRI_IMAGE_COMPONENTS_XYUV, 1, + { { 0, 0, 0, __DRI_IMAGE_FORMAT_XBGR8888, 4 } } }, + /* For YUYV and UYVY buffers, we set up two overlapping DRI images * and treat them as planar buffers in the compositors. * Plane 0 is GR88 and samples YU or YV pairs and places Y into @@ -287,10 +325,10 @@ static const struct intel_image_format intel_image_formats[] = { * V into A. This lets the texture sampler interpolate the Y * components correctly when sampling from plane 0, and interpolate * U and V correctly when sampling from plane 1. */ - { __DRI_IMAGE_FOURCC_YUYV, __DRI_IMAGE_COMPONENTS_Y_XUXV, 2, + { DRM_FORMAT_YUYV, __DRI_IMAGE_COMPONENTS_Y_XUXV, 2, { { 0, 0, 0, __DRI_IMAGE_FORMAT_GR88, 2 }, { 0, 1, 0, __DRI_IMAGE_FORMAT_ARGB8888, 4 } } }, - { __DRI_IMAGE_FOURCC_UYVY, __DRI_IMAGE_COMPONENTS_Y_UXVX, 2, + { DRM_FORMAT_UYVY, __DRI_IMAGE_COMPONENTS_Y_UXVX, 2, { { 0, 0, 0, __DRI_IMAGE_FORMAT_GR88, 2 }, { 0, 1, 0, __DRI_IMAGE_FORMAT_ABGR8888, 4 } } } }; @@ -333,6 +371,10 @@ modifier_is_supported(const struct gen_device_info *devinfo, } mesa_format format = driImageFormatToGLFormat(dri_format); + /* Whether or not we support compression is based on the RGBA non-sRGB + * version of the format. + */ + format = _mesa_format_fallback_rgbx_to_rgba(format); format = _mesa_get_srgb_format_linear(format); if (!isl_format_supports_ccs_e(devinfo, brw_isl_format_for_mesa_format(format))) @@ -386,10 +428,16 @@ intel_image_format_lookup(int fourcc) return NULL; } -static boolean intel_lookup_fourcc(int dri_format, int *fourcc) +static bool +intel_image_get_fourcc(__DRIimage *image, int *fourcc) { + if (image->planar_format) { + *fourcc = image->planar_format->fourcc; + return true; + } + for (unsigned i = 0; i < ARRAY_SIZE(intel_image_formats); i++) { - if (intel_image_formats[i].planes[0].dri_format == dri_format) { + if (intel_image_formats[i].planes[0].dri_format == image->dri_format) { *fourcc = intel_image_formats[i].fourcc; return true; } @@ -440,7 +488,7 @@ intel_setup_image_from_mipmap_tree(struct brw_context *brw, __DRIimage *image, level - mt->first_level); image->height = minify(mt->surf.phys_level0_sa.height, level - mt->first_level); - image->pitch = mt->surf.row_pitch; + image->pitch = mt->surf.row_pitch_B; image->offset = intel_miptree_get_tile_offsets(mt, level, zoffset, &image->tile_x, @@ -516,7 +564,7 @@ intel_create_image_from_renderbuffer(__DRIcontext *context, brw_bo_reference(irb->mt->bo); image->width = rb->Width; image->height = rb->Height; - image->pitch = irb->mt->surf.row_pitch; + image->pitch = irb->mt->surf.row_pitch_B; image->dri_format = driGLFormatToImageFormat(image->format); image->has_depthstencil = irb->mt->stencil_mt? true : false; @@ -576,7 +624,8 @@ intel_create_image_from_texture(__DRIcontext *context, int target, intel_setup_image_from_mipmap_tree(brw, image, iobj->mt, level, zoffset); image->dri_format = driGLFormatToImageFormat(image->format); image->has_depthstencil = iobj->mt->stencil_mt? true : false; - if (image->dri_format == MESA_FORMAT_NONE) { + image->planar_format = iobj->planar_format; + if (image->dri_format == __DRI_IMAGE_FORMAT_NONE) { *error = __DRI_IMAGE_ERROR_BAD_PARAMETER; free(image); return NULL; @@ -705,7 +754,9 @@ intel_create_image_common(__DRIscreen *dri_screen, .samples = 1, .usage = ISL_SURF_USAGE_RENDER_TARGET_BIT | ISL_SURF_USAGE_TEXTURE_BIT | - ISL_SURF_USAGE_STORAGE_BIT, + ISL_SURF_USAGE_STORAGE_BIT | + ((use & __DRI_IMAGE_USE_SCANOUT) ? + ISL_SURF_USAGE_DISPLAY_BIT : 0), .tiling_flags = (1 << mod_info->tiling)); assert(ok); if (!ok) { @@ -722,7 +773,7 @@ intel_create_image_common(__DRIscreen *dri_screen, } } else { assert(mod_info->aux_usage == ISL_AUX_USAGE_NONE); - aux_surf.size = 0; + aux_surf.size_B = 0; } /* We request that the bufmgr zero the buffer for us for two reasons: @@ -735,22 +786,23 @@ intel_create_image_common(__DRIscreen *dri_screen, * in the pass-through state which is what we want. */ image->bo = brw_bo_alloc_tiled(screen->bufmgr, "image", - surf.size + aux_surf.size, + surf.size_B + aux_surf.size_B, + BRW_MEMZONE_OTHER, isl_tiling_to_i915_tiling(mod_info->tiling), - surf.row_pitch, BO_ALLOC_ZEROED); + surf.row_pitch_B, BO_ALLOC_ZEROED); if (image->bo == NULL) { free(image); return NULL; } image->width = width; image->height = height; - image->pitch = surf.row_pitch; + image->pitch = surf.row_pitch_B; image->modifier = modifier; - if (aux_surf.size) { - image->aux_offset = surf.size; - image->aux_pitch = aux_surf.row_pitch; - image->aux_size = aux_surf.size; + if (aux_surf.size_B) { + image->aux_offset = surf.size_B; + image->aux_pitch = aux_surf.row_pitch_B; + image->aux_size = aux_surf.size_B; } return image; @@ -867,7 +919,7 @@ intel_query_image(__DRIimage *image, int attrib, int *value) case __DRI_IMAGE_ATTRIB_FD: return !brw_bo_gem_export_to_prime(image->bo, value); case __DRI_IMAGE_ATTRIB_FOURCC: - return intel_lookup_fourcc(image->dri_format, value); + return intel_image_get_fourcc(image, value); case __DRI_IMAGE_ATTRIB_NUM_PLANES: if (isl_drm_modifier_has_aux(image->modifier)) { assert(!image->planar_format || image->planar_format->nplanes == 1); @@ -938,7 +990,6 @@ intel_dup_image(__DRIimage *orig_image, void *loaderPrivate) image->tile_y = orig_image->tile_y; image->has_depthstencil = orig_image->has_depthstencil; image->data = loaderPrivate; - image->dma_buf_imported = orig_image->dma_buf_imported; image->aux_offset = orig_image->aux_offset; image->aux_pitch = orig_image->aux_pitch; @@ -1079,6 +1130,11 @@ intel_create_image_from_fds_common(__DRIscreen *dri_screen, image->strides[index] = strides[index]; mesa_format format = driImageFormatToGLFormat(f->planes[i].dri_format); + /* The images we will create are actually based on the RGBA non-sRGB + * version of the format. + */ + format = _mesa_format_fallback_rgbx_to_rgba(format); + format = _mesa_get_srgb_format_linear(format); ok = isl_surf_init(&screen->isl_dev, &surf, .dim = ISL_SURF_DIM_2D, @@ -1089,7 +1145,7 @@ intel_create_image_from_fds_common(__DRIscreen *dri_screen, .levels = 1, .array_len = 1, .samples = 1, - .row_pitch = strides[index], + .row_pitch_B = strides[index], .usage = ISL_SURF_USAGE_RENDER_TARGET_BIT | ISL_SURF_USAGE_TEXTURE_BIT | ISL_SURF_USAGE_STORAGE_BIT, @@ -1100,7 +1156,7 @@ intel_create_image_from_fds_common(__DRIscreen *dri_screen, return NULL; } - const int end = offsets[index] + surf.size; + const int end = offsets[index] + surf.size_B; if (size < end) size = end; } @@ -1138,9 +1194,9 @@ intel_create_image_from_fds_common(__DRIscreen *dri_screen, return NULL; } - image->aux_size = aux_surf.size; + image->aux_size = aux_surf.size_B; - const int end = image->aux_offset + aux_surf.size; + const int end = image->aux_offset + aux_surf.size_B; if (size < end) size = end; } else { @@ -1213,7 +1269,6 @@ intel_create_image_from_dma_bufs2(__DRIscreen *dri_screen, return NULL; } - image->dma_buf_imported = true; image->yuv_color_space = yuv_color_space; image->sample_range = sample_range; image->horizontal_siting = horizontal_siting; @@ -1246,24 +1301,60 @@ intel_create_image_from_dma_bufs(__DRIscreen *dri_screen, loaderPrivate); } +static bool +intel_image_format_is_supported(const struct gen_device_info *devinfo, + const struct intel_image_format *fmt) +{ + /* Currently, all formats with an intel_image_format are available on all + * platforms so there's really nothing to check there. + */ + +#ifndef NDEBUG + if (fmt->nplanes == 1) { + mesa_format format = driImageFormatToGLFormat(fmt->planes[0].dri_format); + /* The images we will create are actually based on the RGBA non-sRGB + * version of the format. + */ + format = _mesa_format_fallback_rgbx_to_rgba(format); + format = _mesa_get_srgb_format_linear(format); + enum isl_format isl_format = brw_isl_format_for_mesa_format(format); + assert(isl_format_supports_rendering(devinfo, isl_format)); + } +#endif + + return true; +} + static GLboolean -intel_query_dma_buf_formats(__DRIscreen *screen, int max, +intel_query_dma_buf_formats(__DRIscreen *_screen, int max, int *formats, int *count) { - int i, j = 0; + struct intel_screen *screen = _screen->driverPrivate; + int num_formats = 0, i; - if (max == 0) { - *count = ARRAY_SIZE(intel_image_formats) - 1; /* not SARGB */ - return true; - } + for (i = 0; i < ARRAY_SIZE(intel_image_formats); i++) { + /* These two formats are valid DRI formats but do not exist in + * drm_fourcc.h in the Linux kernel. We don't want to accidentally + * advertise them through the EGL layer. + */ + if (intel_image_formats[i].fourcc == __DRI_IMAGE_FOURCC_SARGB8888 || + intel_image_formats[i].fourcc == __DRI_IMAGE_FOURCC_SABGR8888) + continue; + + if (!intel_image_format_is_supported(&screen->devinfo, + &intel_image_formats[i])) + continue; - for (i = 0; i < (ARRAY_SIZE(intel_image_formats)) && j < max; i++) { - if (intel_image_formats[i].fourcc == __DRI_IMAGE_FOURCC_SARGB8888) - continue; - formats[j++] = intel_image_formats[i].fourcc; + num_formats++; + if (max == 0) + continue; + + formats[num_formats - 1] = intel_image_formats[i].fourcc; + if (num_formats >= max) + break; } - *count = j; + *count = num_formats; return true; } @@ -1281,6 +1372,9 @@ intel_query_dma_buf_modifiers(__DRIscreen *_screen, int fourcc, int max, if (f == NULL) return false; + if (!intel_image_format_is_supported(&screen->devinfo, f)) + return false; + for (i = 0; i < ARRAY_SIZE(supported_modifiers); i++) { uint64_t modifier = supported_modifiers[i].modifier; if (!modifier_is_supported(&screen->devinfo, f, 0, modifier)) @@ -1299,7 +1393,8 @@ intel_query_dma_buf_modifiers(__DRIscreen *_screen, int fourcc, int max, for (i = 0; i < num_mods && i < max; i++) { if (f->components == __DRI_IMAGE_COMPONENTS_Y_U_V || f->components == __DRI_IMAGE_COMPONENTS_Y_UV || - f->components == __DRI_IMAGE_COMPONENTS_Y_XUXV) { + f->components == __DRI_IMAGE_COMPONENTS_Y_XUXV || + f->components == __DRI_IMAGE_COMPONENTS_Y_UXVX) { external_only[i] = GL_TRUE; } else { @@ -1462,14 +1557,14 @@ brw_query_renderer_integer(__DRIscreen *dri_screen, case __DRI2_RENDERER_HAS_CONTEXT_PRIORITY: value[0] = 0; if (brw_hw_context_set_priority(screen->bufmgr, - 0, BRW_CONTEXT_HIGH_PRIORITY) == 0) + 0, GEN_CONTEXT_HIGH_PRIORITY) == 0) value[0] |= __DRI2_RENDERER_HAS_CONTEXT_PRIORITY_HIGH; if (brw_hw_context_set_priority(screen->bufmgr, - 0, BRW_CONTEXT_LOW_PRIORITY) == 0) + 0, GEN_CONTEXT_LOW_PRIORITY) == 0) value[0] |= __DRI2_RENDERER_HAS_CONTEXT_PRIORITY_LOW; /* reset to default last, just in case */ if (brw_hw_context_set_priority(screen->bufmgr, - 0, BRW_CONTEXT_MEDIUM_PRIORITY) == 0) + 0, GEN_CONTEXT_MEDIUM_PRIORITY) == 0) value[0] |= __DRI2_RENDERER_HAS_CONTEXT_PRIORITY_MEDIUM; return 0; case __DRI2_RENDERER_HAS_FRAMEBUFFER_SRGB: @@ -1532,12 +1627,17 @@ static const __DRI2blobExtension intelBlobExtension = { .set_cache_funcs = brw_set_cache_funcs }; +static const __DRImutableRenderBufferDriverExtension intelMutableRenderBufferExtension = { + .base = { __DRI_MUTABLE_RENDER_BUFFER_DRIVER, 1 }, +}; + static const __DRIextension *screenExtensions[] = { &intelTexBufferExtension.base, &intelFenceExtension.base, &intelFlushExtension.base, &intelImageExtension.base, &intelRendererQueryExtension.base, + &intelMutableRenderBufferExtension.base, &dri2ConfigQueryExtension.base, &dri2NoErrorExtension.base, &intelBlobExtension.base, @@ -1550,6 +1650,7 @@ static const __DRIextension *intelRobustScreenExtensions[] = { &intelFlushExtension.base, &intelImageExtension.base, &intelRendererQueryExtension.base, + &intelMutableRenderBufferExtension.base, &dri2ConfigQueryExtension.base, &dri2Robustness.base, &dri2NoErrorExtension.base, @@ -1642,7 +1743,11 @@ intelCreateBuffer(__DRIscreen *dri_screen, fb->Visual.samples = num_samples; } - if (mesaVis->redBits == 10 && mesaVis->alphaBits > 0) { + if (mesaVis->redBits == 16 && mesaVis->alphaBits > 0 && mesaVis->floatMode) { + rgbFormat = MESA_FORMAT_RGBA_FLOAT16; + } else if (mesaVis->redBits == 16 && mesaVis->floatMode) { + rgbFormat = MESA_FORMAT_RGBX_FLOAT16; + } else if (mesaVis->redBits == 10 && mesaVis->alphaBits > 0) { rgbFormat = mesaVis->redMask == 0x3ff00000 ? MESA_FORMAT_B10G10R10A2_UNORM : MESA_FORMAT_R10G10B10A2_UNORM; } else if (mesaVis->redBits == 10) { @@ -1801,7 +1906,17 @@ intel_init_bufmgr(struct intel_screen *screen) if (getenv("INTEL_NO_HW") != NULL) screen->no_hw = true; - screen->bufmgr = brw_bufmgr_init(&screen->devinfo, dri_screen->fd); + bool bo_reuse = false; + int bo_reuse_mode = driQueryOptioni(&screen->optionCache, "bo_reuse"); + switch (bo_reuse_mode) { + case DRI_CONF_BO_REUSE_DISABLED: + break; + case DRI_CONF_BO_REUSE_ALL: + bo_reuse = true; + break; + } + + screen->bufmgr = brw_bufmgr_init(&screen->devinfo, dri_screen->fd, bo_reuse); if (screen->bufmgr == NULL) { fprintf(stderr, "[%s:%u] Error initializing buffer manager.\n", __func__, __LINE__); @@ -1819,24 +1934,32 @@ intel_init_bufmgr(struct intel_screen *screen) static bool intel_detect_swizzling(struct intel_screen *screen) { - struct brw_bo *buffer; - unsigned flags = 0; - uint32_t aligned_pitch; + /* Broadwell PRM says: + * + * "Before Gen8, there was a historical configuration control field to + * swizzle address bit[6] for in X/Y tiling modes. This was set in three + * different places: TILECTL[1:0], ARB_MODE[5:4], and + * DISP_ARB_CTL[14:13]. + * + * For Gen8 and subsequent generations, the swizzle fields are all + * reserved, and the CPU's memory controller performs all address + * swizzling modifications." + */ + if (screen->devinfo.gen >= 8) + return false; + uint32_t tiling = I915_TILING_X; uint32_t swizzle_mode = 0; - - buffer = brw_bo_alloc_tiled_2d(screen->bufmgr, "swizzle test", - 64, 64, 4, tiling, &aligned_pitch, flags); + struct brw_bo *buffer = + brw_bo_alloc_tiled(screen->bufmgr, "swizzle test", 32768, + BRW_MEMZONE_OTHER, tiling, 512, 0); if (buffer == NULL) return false; brw_bo_get_tiling(buffer, &tiling, &swizzle_mode); brw_bo_unreference(buffer); - if (swizzle_mode == I915_BIT_6_SWIZZLE_NONE) - return false; - else - return true; + return swizzle_mode != I915_BIT_6_SWIZZLE_NONE; } static int @@ -1904,11 +2027,11 @@ intel_detect_pipelined_register(struct intel_screen *screen, bool success = false; /* Create a zero'ed temporary buffer for reading our results */ - results = brw_bo_alloc(screen->bufmgr, "registers", 4096, 0); + results = brw_bo_alloc(screen->bufmgr, "registers", 4096, BRW_MEMZONE_OTHER); if (results == NULL) goto err; - bo = brw_bo_alloc(screen->bufmgr, "batchbuffer", 4096, 0); + bo = brw_bo_alloc(screen->bufmgr, "batchbuffer", 4096, BRW_MEMZONE_OTHER); if (bo == NULL) goto err_results; @@ -2048,6 +2171,45 @@ intel_loader_get_cap(const __DRIscreen *dri_screen, enum dri_loader_cap cap) return 0; } +static bool +intel_allowed_format(__DRIscreen *dri_screen, mesa_format format) +{ + struct intel_screen *screen = dri_screen->driverPrivate; + + /* Expose only BGRA ordering if the loader doesn't support RGBA ordering. */ + bool allow_rgba_ordering = intel_loader_get_cap(dri_screen, DRI_LOADER_CAP_RGBA_ORDERING); + if (!allow_rgba_ordering && + (format == MESA_FORMAT_R8G8B8A8_UNORM || + format == MESA_FORMAT_R8G8B8X8_UNORM || + format == MESA_FORMAT_R8G8B8A8_SRGB)) + return false; + + /* Shall we expose 10 bpc formats? */ + bool allow_rgb10_configs = driQueryOptionb(&screen->optionCache, + "allow_rgb10_configs"); + if (!allow_rgb10_configs && + (format == MESA_FORMAT_B10G10R10A2_UNORM || + format == MESA_FORMAT_B10G10R10X2_UNORM)) + return false; + + /* Shall we expose 565 formats? */ + bool allow_rgb565_configs = driQueryOptionb(&screen->optionCache, + "allow_rgb565_configs"); + if (!allow_rgb565_configs && format == MESA_FORMAT_B5G6R5_UNORM) + return false; + + /* Shall we expose fp16 formats? */ + bool allow_fp16_configs = driQueryOptionb(&screen->optionCache, + "allow_fp16_configs"); + allow_fp16_configs &= intel_loader_get_cap(dri_screen, DRI_LOADER_CAP_FP16); + if (!allow_fp16_configs && + (format == MESA_FORMAT_RGBA_FLOAT16 || + format == MESA_FORMAT_RGBX_FLOAT16)) + return false; + + return true; +} + static __DRIconfig** intel_screen_make_configs(__DRIscreen *dri_screen) { @@ -2062,6 +2224,9 @@ intel_screen_make_configs(__DRIscreen *dri_screen) MESA_FORMAT_B10G10R10A2_UNORM, MESA_FORMAT_B10G10R10X2_UNORM, + MESA_FORMAT_RGBA_FLOAT16, + MESA_FORMAT_RGBX_FLOAT16, + /* The 32-bit RGBA format must not precede the 32-bit BGRA format. * Likewise for RGBX and BGRX. Otherwise, the GLX client and the GLX * server may disagree on which format the GLXFBConfig represents, @@ -2082,9 +2247,11 @@ intel_screen_make_configs(__DRIscreen *dri_screen) /* Required by Android, for HAL_PIXEL_FORMAT_RGBX_8888. */ MESA_FORMAT_R8G8B8X8_UNORM, + + MESA_FORMAT_R8G8B8A8_SRGB, }; - /* GLX_SWAP_COPY_OML is not supported due to page flipping. */ + /* __DRI_ATTRIB_SWAP_COPY is not supported due to page flipping. */ static const GLenum back_buffer_modes[] = { __DRI_ATTRIB_SWAP_UNDEFINED, __DRI_ATTRIB_SWAP_NONE }; @@ -2096,25 +2263,16 @@ intel_screen_make_configs(__DRIscreen *dri_screen) uint8_t depth_bits[4], stencil_bits[4]; __DRIconfig **configs = NULL; - /* Expose only BGRA ordering if the loader doesn't support RGBA ordering. */ - unsigned num_formats; - if (intel_loader_get_cap(dri_screen, DRI_LOADER_CAP_RGBA_ORDERING)) - num_formats = ARRAY_SIZE(formats); - else - num_formats = ARRAY_SIZE(formats) - 2; /* all - RGBA_ORDERING formats */ - - /* Shall we expose 10 bpc formats? */ - bool allow_rgb10_configs = driQueryOptionb(&screen->optionCache, - "allow_rgb10_configs"); + unsigned num_formats = ARRAY_SIZE(formats); - /* Generate singlesample configs without accumulation buffer. */ + /* Generate singlesample configs, each without accumulation buffer + * and with EGL_MUTABLE_RENDER_BUFFER_BIT_KHR. + */ for (unsigned i = 0; i < num_formats; i++) { __DRIconfig **new_configs; int num_depth_stencil_bits = 2; - if (!allow_rgb10_configs && - (formats[i] == MESA_FORMAT_B10G10R10A2_UNORM || - formats[i] == MESA_FORMAT_B10G10R10X2_UNORM)) + if (!intel_allowed_format(dri_screen, formats[i])) continue; /* Starting with DRI2 protocol version 1.1 we can request a depth/stencil @@ -2143,7 +2301,8 @@ intel_screen_make_configs(__DRIscreen *dri_screen) num_depth_stencil_bits, back_buffer_modes, 2, singlesample_samples, 1, - false, false); + false, false, + /*mutable_render_buffer*/ true); configs = driConcatConfigs(configs, new_configs); } @@ -2153,9 +2312,7 @@ intel_screen_make_configs(__DRIscreen *dri_screen) for (unsigned i = 0; i < num_formats; i++) { __DRIconfig **new_configs; - if (!allow_rgb10_configs && - (formats[i] == MESA_FORMAT_B10G10R10A2_UNORM || - formats[i] == MESA_FORMAT_B10G10R10X2_UNORM)) + if (!intel_allowed_format(dri_screen, formats[i])) continue; if (formats[i] == MESA_FORMAT_B5G6R5_UNORM) { @@ -2170,7 +2327,7 @@ intel_screen_make_configs(__DRIscreen *dri_screen) depth_bits, stencil_bits, 1, back_buffer_modes, 1, singlesample_samples, 1, - true, false); + true, false, false); configs = driConcatConfigs(configs, new_configs); } @@ -2191,9 +2348,7 @@ intel_screen_make_configs(__DRIscreen *dri_screen) if (devinfo->gen < 6) break; - if (!allow_rgb10_configs && - (formats[i] == MESA_FORMAT_B10G10R10A2_UNORM || - formats[i] == MESA_FORMAT_B10G10R10X2_UNORM)) + if (!intel_allowed_format(dri_screen, formats[i])) continue; __DRIconfig **new_configs; @@ -2237,7 +2392,7 @@ intel_screen_make_configs(__DRIscreen *dri_screen) back_buffer_modes, 1, multisample_samples, num_msaa_modes, - false, false); + false, false, false); configs = driConcatConfigs(configs, new_configs); } @@ -2261,7 +2416,7 @@ set_max_gl_versions(struct intel_screen *screen) case 10: case 9: case 8: - dri_screen->max_gl_core_version = 45; + dri_screen->max_gl_core_version = 46; dri_screen->max_gl_compat_version = 30; dri_screen->max_gl_es1_version = 11; dri_screen->max_gl_es2_version = has_astc ? 32 : 31; @@ -2297,28 +2452,6 @@ set_max_gl_versions(struct intel_screen *screen) } } -/** - * Return the revision (generally the revid field of the PCI header) of the - * graphics device. - */ -int -intel_device_get_revision(int fd) -{ - struct drm_i915_getparam gp; - int revision; - int ret; - - memset(&gp, 0, sizeof(gp)); - gp.param = I915_PARAM_REVISION; - gp.value = &revision; - - ret = drmCommandWriteRead(fd, DRM_I915_GETPARAM, &gp, sizeof(gp)); - if (ret) - revision = -1; - - return revision; -} - static void shader_debug_log_mesa(void *data, const char *fmt, ...) { @@ -2327,10 +2460,10 @@ shader_debug_log_mesa(void *data, const char *fmt, ...) va_start(args, fmt); GLuint msg_id = 0; - _mesa_gl_vdebug(&brw->ctx, &msg_id, - MESA_DEBUG_SOURCE_SHADER_COMPILER, - MESA_DEBUG_TYPE_OTHER, - MESA_DEBUG_SEVERITY_NOTIFICATION, fmt, args); + _mesa_gl_vdebugf(&brw->ctx, &msg_id, + MESA_DEBUG_SOURCE_SHADER_COMPILER, + MESA_DEBUG_TYPE_OTHER, + MESA_DEBUG_SEVERITY_NOTIFICATION, fmt, args); va_end(args); } @@ -2351,65 +2484,14 @@ shader_perf_log_mesa(void *data, const char *fmt, ...) if (brw->perf_debug) { GLuint msg_id = 0; - _mesa_gl_vdebug(&brw->ctx, &msg_id, - MESA_DEBUG_SOURCE_SHADER_COMPILER, - MESA_DEBUG_TYPE_PERFORMANCE, - MESA_DEBUG_SEVERITY_MEDIUM, fmt, args); + _mesa_gl_vdebugf(&brw->ctx, &msg_id, + MESA_DEBUG_SOURCE_SHADER_COMPILER, + MESA_DEBUG_TYPE_PERFORMANCE, + MESA_DEBUG_SEVERITY_MEDIUM, fmt, args); } va_end(args); } -static int -parse_devid_override(const char *devid_override) -{ - static const struct { - const char *name; - int pci_id; - } name_map[] = { - { "brw", 0x2a02 }, - { "g4x", 0x2a42 }, - { "ilk", 0x0042 }, - { "snb", 0x0126 }, - { "ivb", 0x016a }, - { "hsw", 0x0d2e }, - { "byt", 0x0f33 }, - { "bdw", 0x162e }, - { "chv", 0x22B3 }, - { "skl", 0x1912 }, - { "bxt", 0x5A85 }, - { "kbl", 0x5912 }, - { "glk", 0x3185 }, - { "cnl", 0x5a52 }, - }; - - for (unsigned i = 0; i < ARRAY_SIZE(name_map); i++) { - if (!strcmp(name_map[i].name, devid_override)) - return name_map[i].pci_id; - } - - return strtol(devid_override, NULL, 0); -} - -/** - * Get the PCI ID for the device. This can be overridden by setting the - * INTEL_DEVID_OVERRIDE environment variable to the desired ID. - * - * Returns -1 on ioctl failure. - */ -static int -get_pci_device_id(struct intel_screen *screen) -{ - if (geteuid() == getuid()) { - char *devid_override = getenv("INTEL_DEVID_OVERRIDE"); - if (devid_override) { - screen->no_hw = true; - return parse_devid_override(devid_override); - } - } - - return intel_get_integer(screen, I915_PARAM_CHIPSET_ID); -} - /** * This is the driver specific part of the createNewScreen entry point. * Called when using DRI2. @@ -2441,22 +2523,28 @@ __DRIconfig **intelInitScreen2(__DRIscreen *dri_screen) memset(&options, 0, sizeof(options)); driParseOptionInfo(&options, brw_config_options.xml); - driParseConfigFiles(&screen->optionCache, &options, dri_screen->myNum, "i965"); + driParseConfigFiles(&screen->optionCache, &options, dri_screen->myNum, + "i965", NULL); driDestroyOptionCache(&options); screen->driScrnPriv = dri_screen; dri_screen->driverPrivate = (void *) screen; - screen->deviceID = get_pci_device_id(screen); + if (!gen_get_device_info_from_fd(dri_screen->fd, &screen->devinfo)) + return NULL; + + const struct gen_device_info *devinfo = &screen->devinfo; + screen->deviceID = devinfo->chipset_id; + screen->no_hw = devinfo->no_hw; - if (!gen_get_device_info(screen->deviceID, &screen->devinfo)) + if (devinfo->gen >= 12) { + fprintf(stderr, "gen12 and newer are not supported on i965\n"); return NULL; + } if (!intel_init_bufmgr(screen)) return NULL; - const struct gen_device_info *devinfo = &screen->devinfo; - brw_process_intel_debug_variable(); if ((INTEL_DEBUG & DEBUG_SHADER_TIME) && devinfo->gen < 7) { @@ -2761,6 +2849,7 @@ intelAllocateBuffer(__DRIscreen *dri_screen, width, height, cpp, + BRW_MEMZONE_OTHER, I915_TILING_X, &pitch, BO_ALLOC_BUSY);