X-Git-Url: https://git.libre-soc.org/?a=blobdiff_plain;f=src%2Fmesa%2Fdrivers%2Fdri%2Fi965%2Fintel_tex_validate.c;h=0bf0393803fc5867a6f5fadae33906c53c95f6fb;hb=7bfbaf4a5ab580a8661ea99059cb48c64a016ab6;hp=07f317441414ba89490d73ece35b8c09c714a958;hpb=771c2ae0afc485a63e4668f0eb7713ea161f1b97;p=mesa.git

diff --git a/src/mesa/drivers/dri/i965/intel_tex_validate.c b/src/mesa/drivers/dri/i965/intel_tex_validate.c
index 07f31744141..0bf0393803f 100644
--- a/src/mesa/drivers/dri/i965/intel_tex_validate.c
+++ b/src/mesa/drivers/dri/i965/intel_tex_validate.c
@@ -107,11 +107,6 @@ intel_finalize_mipmap_tree(struct brw_context *brw, GLuint unit)
 
    /* Check tree can hold all active levels.  Check tree matches
     * target, imageFormat, etc.
-    *
-    * For pre-gen4, we have to match first_level == tObj->BaseLevel,
-    * because we don't have the control that gen4 does to make min/mag
-    * determination happen at a nonzero (hardware) baselevel.  Because
-    * of that, we just always relayout on baselevel change.
     */
    if (intelObj->mt &&
        (!intel_miptree_match_image(intelObj->mt, &firstImage->base.Base) ||
@@ -142,7 +137,8 @@ intel_finalize_mipmap_tree(struct brw_context *brw, GLuint unit)
                                           depth,
 					  true,
                                           0 /* num_samples */,
-                                          INTEL_MIPTREE_TILING_ANY);
+                                          INTEL_MIPTREE_TILING_ANY,
+                                          false);
       if (!intelObj->mt)
          return false;
    }