X-Git-Url: https://git.libre-soc.org/?a=blobdiff_plain;f=src%2Fmesa%2Fdrivers%2Fdri%2Fintel%2Fintel_context.h;h=c0f07ff1f3c87e559f48f749389e4975e6961363;hb=bdf13dc8324c391b7d34f8bdaea72c4452ab7edb;hp=42db5a7d96deb29974b05f51135cfba5aca23660;hpb=14cec07177f438717cc6fb9252525e16d6b3d8dd;p=mesa.git

diff --git a/src/mesa/drivers/dri/intel/intel_context.h b/src/mesa/drivers/dri/intel/intel_context.h
index 42db5a7d96d..c0f07ff1f3c 100644
--- a/src/mesa/drivers/dri/intel/intel_context.h
+++ b/src/mesa/drivers/dri/intel/intel_context.h
@@ -202,14 +202,30 @@ struct intel_context
       void (*create_constant_surface)(struct brw_context *brw,
 				      drm_intel_bo *bo,
 				      uint32_t offset,
-				      int width,
-				      uint32_t *out_offset);
+				      uint32_t size,
+				      uint32_t *out_offset,
+                                      bool dword_pitch);
       /** \} */
+
+      /**
+       * Send the appropriate state packets to configure depth, stencil, and
+       * HiZ buffers (i965+ only)
+       */
+      void (*emit_depth_stencil_hiz)(struct brw_context *brw,
+                                     struct intel_mipmap_tree *depth_mt,
+                                     uint32_t depth_offset,
+                                     uint32_t depthbuffer_format,
+                                     uint32_t depth_surface_type,
+                                     struct intel_mipmap_tree *stencil_mt,
+                                     bool hiz, bool separate_stencil,
+                                     uint32_t width, uint32_t height,
+                                     uint32_t tile_x, uint32_t tile_y);
+
    } vtbl;
 
    GLbitfield Fallback;  /**< mask of INTEL_FALLBACK_x bits */
    GLuint NewGLState;
-
+ 
    dri_bufmgr *bufmgr;
    unsigned int maxBatchSize;
 
@@ -220,6 +236,7 @@ struct intel_context
    int gt;
    bool needs_ff_sync;
    bool is_haswell;
+   bool is_baytrail;
    bool is_g4x;
    bool is_945;
    bool has_separate_stencil;
@@ -267,6 +284,8 @@ struct intel_context
       char buffer[4096];
    } upload;
 
+   uint32_t max_gtt_map_object_size;
+
    GLuint stats_wm;
 
    /* Offsets of fields within the current vertex:
@@ -285,6 +304,7 @@ struct intel_context
    bool no_rast;
    bool always_flush_batch;
    bool always_flush_cache;
+   bool disable_throttling;
 
    /* State for intelvb.c and inteltris.c.
     */
@@ -325,15 +345,6 @@ struct intel_context
     */
    bool is_front_buffer_reading;
 
-   /**
-    * Count of intel_regions that are mapped.
-    *
-    * This allows us to assert that no batch buffer is emitted if a
-    * region is mapped.
-    */
-   int num_mapped_regions;
-
-   bool use_texture_tiling;
    bool use_early_z;
 
    int driFd;
@@ -428,7 +439,6 @@ extern int INTEL_DEBUG;
 #define DEBUG_BLIT	0x8
 #define DEBUG_MIPTREE   0x10
 #define DEBUG_PERF	0x20
-#define DEBUG_VERBOSE	0x40
 #define DEBUG_BATCH     0x80
 #define DEBUG_PIXEL     0x100
 #define DEBUG_BUFMGR    0x200
@@ -440,16 +450,14 @@ extern int INTEL_DEBUG;
 #define DEBUG_VERTS	0x8000
 #define DEBUG_DRI       0x10000
 #define DEBUG_SF        0x20000
-#define DEBUG_SANITY    0x40000
-#define DEBUG_SLEEP     0x80000
 #define DEBUG_STATS     0x100000
-#define DEBUG_TILE      0x200000
 #define DEBUG_WM        0x400000
 #define DEBUG_URB       0x800000
 #define DEBUG_VS        0x1000000
 #define DEBUG_CLIP      0x2000000
 #define DEBUG_AUB       0x4000000
 #define DEBUG_SHADER_TIME 0x8000000
+#define DEBUG_BLORP     0x10000000
 #define DEBUG_NO16      0x20000000
 
 #ifdef HAVE_ANDROID_PLATFORM