X-Git-Url: https://git.libre-soc.org/?a=blobdiff_plain;f=src%2Fmesa%2Fdrivers%2Fdri%2Fintel%2Fintel_context.h;h=c0f07ff1f3c87e559f48f749389e4975e6961363;hb=bdf13dc8324c391b7d34f8bdaea72c4452ab7edb;hp=b7989dd42f57b8e99cb0e374e2af5b9a07ec3189;hpb=636d01bd61cac83e13c3c64874e7e34e828ca93a;p=mesa.git diff --git a/src/mesa/drivers/dri/intel/intel_context.h b/src/mesa/drivers/dri/intel/intel_context.h index b7989dd42f5..c0f07ff1f3c 100644 --- a/src/mesa/drivers/dri/intel/intel_context.h +++ b/src/mesa/drivers/dri/intel/intel_context.h @@ -30,6 +30,7 @@ #include +#include #include "main/mtypes.h" #include "main/mm.h" @@ -48,7 +49,6 @@ extern "C" { #ifdef __cplusplus #undef virtual -} #endif #include "tnl/t_vertex.h" @@ -87,7 +87,7 @@ typedef void (*intel_point_func) (struct intel_context *, intelVertex *); /*@}*/ extern void intelFallback(struct intel_context *intel, GLbitfield bit, - GLboolean mode); + bool mode); #define FALLBACK( intel, bit, mode ) intelFallback( intel, bit, mode ) @@ -114,6 +114,35 @@ struct intel_sync_object { drm_intel_bo *bo; }; +struct brw_context; + +struct intel_batchbuffer { + /** Current batchbuffer being queued up. */ + drm_intel_bo *bo; + /** Last BO submitted to the hardware. Used for glFinish(). */ + drm_intel_bo *last_bo; + /** BO for post-sync nonzero writes for gen6 workaround. */ + drm_intel_bo *workaround_bo; + bool need_workaround_flush; + + struct cached_batch_item *cached_items; + + uint16_t emit, total; + uint16_t used, reserved_space; + uint32_t *map; + uint32_t *cpu_map; +#define BATCH_SZ (8192*sizeof(uint32_t)) + + uint32_t state_batch_offset; + bool is_blit; + bool needs_sol_reset; + + struct { + uint16_t used; + int reloc_count; + } saved; +}; + /** * intel_context is derived from Mesa's context class: struct gl_context. */ @@ -141,7 +170,7 @@ struct intel_context void (*reduced_primitive_state) (struct intel_context * intel, GLenum rprim); - GLboolean (*check_vertex_size) (struct intel_context * intel, + bool (*check_vertex_size) (struct intel_context * intel, GLuint expected); void (*invalidate_state) (struct intel_context *intel, GLuint new_state); @@ -149,16 +178,54 @@ struct intel_context void (*assert_not_dirty) (struct intel_context *intel); void (*debug_batch)(struct intel_context *intel); - bool (*render_target_supported)(gl_format format); + void (*annotate_aub)(struct intel_context *intel); + bool (*render_target_supported)(struct intel_context *intel, + struct gl_renderbuffer *rb); /** Can HiZ be enabled on a depthbuffer of the given format? */ bool (*is_hiz_depth_format)(struct intel_context *intel, gl_format format); + + /** + * Surface state operations (i965+ only) + * \{ + */ + void (*update_texture_surface)(struct gl_context *ctx, + unsigned unit, + uint32_t *binding_table, + unsigned surf_index); + void (*update_renderbuffer_surface)(struct brw_context *brw, + struct gl_renderbuffer *rb, + unsigned unit); + void (*update_null_renderbuffer_surface)(struct brw_context *brw, + unsigned unit); + void (*create_constant_surface)(struct brw_context *brw, + drm_intel_bo *bo, + uint32_t offset, + uint32_t size, + uint32_t *out_offset, + bool dword_pitch); + /** \} */ + + /** + * Send the appropriate state packets to configure depth, stencil, and + * HiZ buffers (i965+ only) + */ + void (*emit_depth_stencil_hiz)(struct brw_context *brw, + struct intel_mipmap_tree *depth_mt, + uint32_t depth_offset, + uint32_t depthbuffer_format, + uint32_t depth_surface_type, + struct intel_mipmap_tree *stencil_mt, + bool hiz, bool separate_stencil, + uint32_t width, uint32_t height, + uint32_t tile_x, uint32_t tile_y); + } vtbl; GLbitfield Fallback; /**< mask of INTEL_FALLBACK_x bits */ GLuint NewGLState; - + dri_bufmgr *bufmgr; unsigned int maxBatchSize; @@ -166,42 +233,36 @@ struct intel_context * Generation number of the hardware: 2 is 8xx, 3 is 9xx pre-965, 4 is 965. */ int gen; - GLboolean needs_ff_sync; - GLboolean is_g4x; - GLboolean is_945; - GLboolean has_luminance_srgb; - GLboolean has_xrgb_textures; - GLboolean has_separate_stencil; - GLboolean must_use_separate_stencil; - GLboolean has_hiz; + int gt; + bool needs_ff_sync; + bool is_haswell; + bool is_baytrail; + bool is_g4x; + bool is_945; + bool has_separate_stencil; + bool must_use_separate_stencil; + bool has_hiz; + bool has_llc; + bool has_swizzling; int urb_size; - struct intel_batchbuffer { - /** Current batchbuffer being queued up. */ - drm_intel_bo *bo; - /** Last BO submitted to the hardware. Used for glFinish(). */ - drm_intel_bo *last_bo; - /** BO for post-sync nonzero writes for gen6 workaround. */ - drm_intel_bo *workaround_bo; - bool need_workaround_flush; - - struct cached_batch_item *cached_items; - - uint16_t emit, total; - uint16_t used, reserved_space; - uint32_t map[8192]; -#define BATCH_SZ (8192*sizeof(uint32_t)) + drm_intel_context *hw_ctx; - uint32_t state_batch_offset; - bool is_blit; - } batch; + struct intel_batchbuffer batch; drm_intel_bo *first_post_swapbuffers_batch; - GLboolean need_throttle; - GLboolean no_batch_wrap; + bool need_throttle; + bool no_batch_wrap; bool tnl_pipeline_running; /**< Set while i915's _tnl_run_pipeline. */ + /** + * Set if we're either a debug context or the INTEL_DEBUG=perf environment + * variable is set, this is the flag indicating to do expensive work that + * might lead to a perf_debug() call. + */ + bool perf_debug; + struct { GLuint id; @@ -223,6 +284,8 @@ struct intel_context char buffer[4096]; } upload; + uint32_t max_gtt_map_object_size; + GLuint stats_wm; /* Offsets of fields within the current vertex: @@ -236,25 +299,19 @@ struct intel_context GLfloat polygon_offset_scale; /* dependent on depth_scale, bpp */ - GLboolean hw_stencil; - GLboolean hw_stipple; - GLboolean depth_buffer_is_float; - GLboolean no_rast; - GLboolean always_flush_batch; - GLboolean always_flush_cache; - - /* 0 - nonconformant, best performance; - * 1 - fallback to sw for known conformance bugs - * 2 - always fallback to sw - */ - GLuint conformance_mode; + bool hw_stencil; + bool hw_stipple; + bool no_rast; + bool always_flush_batch; + bool always_flush_cache; + bool disable_throttling; /* State for intelvb.c and inteltris.c. */ GLuint RenderIndex; GLmatrix ViewportMatrix; GLenum render_primitive; - GLenum reduced_primitive; + GLenum reduced_primitive; /*< Only gen < 6 */ GLuint vertex_size; GLubyte *verts; /* points to tnl->clipspace.vertex_buf */ @@ -270,7 +327,7 @@ struct intel_context * This is used in the DRI2 case to detect that glFlush should also copy * the contents of the fake front buffer to the real front buffer. */ - GLboolean front_buffer_dirty; + bool front_buffer_dirty; /** * Track whether front-buffer rendering is currently enabled @@ -278,7 +335,7 @@ struct intel_context * A separate flag is used to track this in order to support MRT more * easily. */ - GLboolean is_front_buffer_rendering; + bool is_front_buffer_rendering; /** * Track whether front-buffer is the current read target. * @@ -286,10 +343,9 @@ struct intel_context * be set separately. The DRI2 fake front buffer must be referenced * either way. */ - GLboolean is_front_buffer_reading; + bool is_front_buffer_reading; - GLboolean use_texture_tiling; - GLboolean use_early_z; + bool use_early_z; int driFd; @@ -310,21 +366,6 @@ extern char *__progname; #define SUBPIXEL_X 0.125 #define SUBPIXEL_Y 0.125 -#define ARRAY_SIZE(x) (sizeof(x) / sizeof(x[0])) - -/** - * Align a value up to an alignment value - * - * If \c value is not already aligned to the requested alignment value, it - * will be rounded up. - * - * \param value Value to be rounded - * \param alignment Alignment value to be used. This must be a power of two. - * - * \sa ROUND_DOWN_TO() - */ -#define ALIGN(value, alignment) (((value) + alignment - 1) & ~(alignment - 1)) - /** * Align a value down to an alignment value * @@ -397,8 +438,7 @@ extern int INTEL_DEBUG; #define DEBUG_IOCTL 0x4 #define DEBUG_BLIT 0x8 #define DEBUG_MIPTREE 0x10 -#define DEBUG_FALLBACKS 0x20 -#define DEBUG_VERBOSE 0x40 +#define DEBUG_PERF 0x20 #define DEBUG_BATCH 0x80 #define DEBUG_PIXEL 0x100 #define DEBUG_BUFMGR 0x200 @@ -410,26 +450,59 @@ extern int INTEL_DEBUG; #define DEBUG_VERTS 0x8000 #define DEBUG_DRI 0x10000 #define DEBUG_SF 0x20000 -#define DEBUG_SANITY 0x40000 -#define DEBUG_SLEEP 0x80000 #define DEBUG_STATS 0x100000 -#define DEBUG_TILE 0x200000 -#define DEBUG_SINGLE_THREAD 0x400000 -#define DEBUG_WM 0x800000 -#define DEBUG_URB 0x1000000 -#define DEBUG_VS 0x2000000 -#define DEBUG_CLIP 0x8000000 +#define DEBUG_WM 0x400000 +#define DEBUG_URB 0x800000 +#define DEBUG_VS 0x1000000 +#define DEBUG_CLIP 0x2000000 +#define DEBUG_AUB 0x4000000 +#define DEBUG_SHADER_TIME 0x8000000 +#define DEBUG_BLORP 0x10000000 +#define DEBUG_NO16 0x20000000 + +#ifdef HAVE_ANDROID_PLATFORM +#define LOG_TAG "INTEL-MESA" +#include +#ifndef ALOGW +#define ALOGW LOGW +#endif +#define dbg_printf(...) ALOGW(__VA_ARGS__) +#else +#define dbg_printf(...) printf(__VA_ARGS__) +#endif /* HAVE_ANDROID_PLATFORM */ #define DBG(...) do { \ if (unlikely(INTEL_DEBUG & FILE_DEBUG_FLAG)) \ - printf(__VA_ARGS__); \ + dbg_printf(__VA_ARGS__); \ } while(0) -#define fallback_debug(...) do { \ - if (unlikely(INTEL_DEBUG & DEBUG_FALLBACKS)) \ - printf(__VA_ARGS__); \ +#define perf_debug(...) do { \ + static GLuint msg_id = 0; \ + if (unlikely(INTEL_DEBUG & DEBUG_PERF)) \ + dbg_printf(__VA_ARGS__); \ + if (intel->perf_debug) \ + _mesa_gl_debug(&intel->ctx, &msg_id, \ + MESA_DEBUG_TYPE_PERFORMANCE, \ + MESA_DEBUG_SEVERITY_MEDIUM, \ + __VA_ARGS__); \ } while(0) +#define WARN_ONCE(cond, fmt...) do { \ + if (unlikely(cond)) { \ + static bool _warned = false; \ + static GLuint msg_id = 0; \ + if (!_warned) { \ + fprintf(stderr, "WARNING: "); \ + fprintf(stderr, fmt); \ + _warned = true; \ + \ + _mesa_gl_debug(ctx, &msg_id, \ + MESA_DEBUG_TYPE_OTHER, \ + MESA_DEBUG_SEVERITY_HIGH, fmt); \ + } \ + } \ +} while (0) + #define PCI_CHIP_845_G 0x2562 #define PCI_CHIP_I830_M 0x3577 #define PCI_CHIP_I855_GM 0x3582 @@ -448,15 +521,21 @@ extern int INTEL_DEBUG; * intel_context.c: */ -extern GLboolean intelInitContext(struct intel_context *intel, - int api, - const struct gl_config * mesaVis, - __DRIcontext * driContextPriv, - void *sharedContextPrivate, - struct dd_function_table *functions); +extern bool intelInitContext(struct intel_context *intel, + int api, + unsigned major_version, + unsigned minor_version, + const struct gl_config * mesaVis, + __DRIcontext * driContextPriv, + void *sharedContextPrivate, + struct dd_function_table *functions, + unsigned *dri_ctx_error); extern void intelFinish(struct gl_context * ctx); -extern void intel_flush(struct gl_context * ctx); +extern void intel_flush_rendering_to_batch(struct gl_context *ctx); +extern void _intel_flush(struct gl_context * ctx, const char *file, int line); + +#define intel_flush(ctx) _intel_flush(ctx, __FILE__, __LINE__) extern void intelInitDriverFunctions(struct dd_function_table *functions); @@ -466,7 +545,6 @@ void intel_init_syncobj_functions(struct dd_function_table *functions); /* ================================================================ * intel_state.c: */ -extern void intelInitStateFuncs(struct dd_function_table *functions); #define COMPAREFUNC_ALWAYS 0 #define COMPAREFUNC_NEVER 0x1 @@ -535,8 +613,13 @@ void intel_update_renderbuffers(__DRIcontext *context, __DRIdrawable *drawable); void intel_prepare_render(struct intel_context *intel); +void +intel_downsample_for_dri2_flush(struct intel_context *intel, + __DRIdrawable *drawable); + void i915_set_buf_info_for_region(uint32_t *state, struct intel_region *region, uint32_t buffer_id); +void intel_init_texture_formats(struct gl_context *ctx); /*====================================================================== * Inline conversion functions. @@ -548,10 +631,14 @@ intel_context(struct gl_context * ctx) return (struct intel_context *) ctx; } -static INLINE GLboolean +static INLINE bool is_power_of_two(uint32_t value) { return (value & (value - 1)) == 0; } +#ifdef __cplusplus +} +#endif + #endif