X-Git-Url: https://git.libre-soc.org/?a=blobdiff_plain;f=src%2Fmesa%2Fdrivers%2Fdri%2Fintel%2Fintel_context.h;h=c0f07ff1f3c87e559f48f749389e4975e6961363;hb=bdf13dc8324c391b7d34f8bdaea72c4452ab7edb;hp=ef024b10e96dc6739b2f1e76674a8107b410c4ec;hpb=f172eae8b23d0612865895c52af745021ae20a4c;p=mesa.git diff --git a/src/mesa/drivers/dri/intel/intel_context.h b/src/mesa/drivers/dri/intel/intel_context.h index ef024b10e96..c0f07ff1f3c 100644 --- a/src/mesa/drivers/dri/intel/intel_context.h +++ b/src/mesa/drivers/dri/intel/intel_context.h @@ -49,7 +49,6 @@ extern "C" { #ifdef __cplusplus #undef virtual -} #endif #include "tnl/t_vertex.h" @@ -117,6 +116,33 @@ struct intel_sync_object { struct brw_context; +struct intel_batchbuffer { + /** Current batchbuffer being queued up. */ + drm_intel_bo *bo; + /** Last BO submitted to the hardware. Used for glFinish(). */ + drm_intel_bo *last_bo; + /** BO for post-sync nonzero writes for gen6 workaround. */ + drm_intel_bo *workaround_bo; + bool need_workaround_flush; + + struct cached_batch_item *cached_items; + + uint16_t emit, total; + uint16_t used, reserved_space; + uint32_t *map; + uint32_t *cpu_map; +#define BATCH_SZ (8192*sizeof(uint32_t)) + + uint32_t state_batch_offset; + bool is_blit; + bool needs_sol_reset; + + struct { + uint16_t used; + int reloc_count; + } saved; +}; + /** * intel_context is derived from Mesa's context class: struct gl_context. */ @@ -152,6 +178,7 @@ struct intel_context void (*assert_not_dirty) (struct intel_context *intel); void (*debug_batch)(struct intel_context *intel); + void (*annotate_aub)(struct intel_context *intel); bool (*render_target_supported)(struct intel_context *intel, struct gl_renderbuffer *rb); @@ -159,31 +186,14 @@ struct intel_context bool (*is_hiz_depth_format)(struct intel_context *intel, gl_format format); - /** - * \name HiZ operations - * - * See the following sections of the Sandy Bridge PRM, Volume 1, Part2: - * - 7.5.3.1 Depth Buffer Clear - * - 7.5.3.2 Depth Buffer Resolve - * - 7.5.3.3 Hierarchical Depth Buffer Resolve - * \{ - */ - void (*resolve_hiz_slice)(struct intel_context *intel, - struct intel_mipmap_tree *mt, - uint32_t level, - uint32_t layer); - - void (*resolve_depth_slice)(struct intel_context *intel, - struct intel_mipmap_tree *mt, - uint32_t level, - uint32_t layer); - /** \} */ - /** * Surface state operations (i965+ only) * \{ */ - void (*update_texture_surface)(struct gl_context *ctx, unsigned unit); + void (*update_texture_surface)(struct gl_context *ctx, + unsigned unit, + uint32_t *binding_table, + unsigned surf_index); void (*update_renderbuffer_surface)(struct brw_context *brw, struct gl_renderbuffer *rb, unsigned unit); @@ -191,14 +201,31 @@ struct intel_context unsigned unit); void (*create_constant_surface)(struct brw_context *brw, drm_intel_bo *bo, - int width, - uint32_t *out_offset); + uint32_t offset, + uint32_t size, + uint32_t *out_offset, + bool dword_pitch); /** \} */ + + /** + * Send the appropriate state packets to configure depth, stencil, and + * HiZ buffers (i965+ only) + */ + void (*emit_depth_stencil_hiz)(struct brw_context *brw, + struct intel_mipmap_tree *depth_mt, + uint32_t depth_offset, + uint32_t depthbuffer_format, + uint32_t depth_surface_type, + struct intel_mipmap_tree *stencil_mt, + bool hiz, bool separate_stencil, + uint32_t width, uint32_t height, + uint32_t tile_x, uint32_t tile_y); + } vtbl; GLbitfield Fallback; /**< mask of INTEL_FALLBACK_x bits */ GLuint NewGLState; - + dri_bufmgr *bufmgr; unsigned int maxBatchSize; @@ -208,6 +235,8 @@ struct intel_context int gen; int gt; bool needs_ff_sync; + bool is_haswell; + bool is_baytrail; bool is_g4x; bool is_945; bool has_separate_stencil; @@ -218,37 +247,22 @@ struct intel_context int urb_size; - struct intel_batchbuffer { - /** Current batchbuffer being queued up. */ - drm_intel_bo *bo; - /** Last BO submitted to the hardware. Used for glFinish(). */ - drm_intel_bo *last_bo; - /** BO for post-sync nonzero writes for gen6 workaround. */ - drm_intel_bo *workaround_bo; - bool need_workaround_flush; + drm_intel_context *hw_ctx; - struct cached_batch_item *cached_items; - - uint16_t emit, total; - uint16_t used, reserved_space; - uint32_t map[8192]; -#define BATCH_SZ (8192*sizeof(uint32_t)) - - uint32_t state_batch_offset; - bool is_blit; - bool needs_sol_reset; - - struct { - uint16_t used; - int reloc_count; - } saved; - } batch; + struct intel_batchbuffer batch; drm_intel_bo *first_post_swapbuffers_batch; bool need_throttle; bool no_batch_wrap; bool tnl_pipeline_running; /**< Set while i915's _tnl_run_pipeline. */ + /** + * Set if we're either a debug context or the INTEL_DEBUG=perf environment + * variable is set, this is the flag indicating to do expensive work that + * might lead to a perf_debug() call. + */ + bool perf_debug; + struct { GLuint id; @@ -270,6 +284,8 @@ struct intel_context char buffer[4096]; } upload; + uint32_t max_gtt_map_object_size; + GLuint stats_wm; /* Offsets of fields within the current vertex: @@ -288,12 +304,7 @@ struct intel_context bool no_rast; bool always_flush_batch; bool always_flush_cache; - - /* 0 - nonconformant, best performance; - * 1 - fallback to sw for known conformance bugs - * 2 - always fallback to sw - */ - GLuint conformance_mode; + bool disable_throttling; /* State for intelvb.c and inteltris.c. */ @@ -334,15 +345,6 @@ struct intel_context */ bool is_front_buffer_reading; - /** - * Count of intel_regions that are mapped. - * - * This allows us to assert that no batch buffer is emitted if a - * region is mapped. - */ - int num_mapped_regions; - - bool use_texture_tiling; bool use_early_z; int driFd; @@ -364,21 +366,6 @@ extern char *__progname; #define SUBPIXEL_X 0.125 #define SUBPIXEL_Y 0.125 -#define ARRAY_SIZE(x) (sizeof(x) / sizeof(x[0])) - -/** - * Align a value up to an alignment value - * - * If \c value is not already aligned to the requested alignment value, it - * will be rounded up. - * - * \param value Value to be rounded - * \param alignment Alignment value to be used. This must be a power of two. - * - * \sa ROUND_DOWN_TO() - */ -#define ALIGN(value, alignment) (((value) + alignment - 1) & ~(alignment - 1)) - /** * Align a value down to an alignment value * @@ -451,8 +438,7 @@ extern int INTEL_DEBUG; #define DEBUG_IOCTL 0x4 #define DEBUG_BLIT 0x8 #define DEBUG_MIPTREE 0x10 -#define DEBUG_FALLBACKS 0x20 -#define DEBUG_VERBOSE 0x40 +#define DEBUG_PERF 0x20 #define DEBUG_BATCH 0x80 #define DEBUG_PIXEL 0x100 #define DEBUG_BUFMGR 0x200 @@ -464,25 +450,59 @@ extern int INTEL_DEBUG; #define DEBUG_VERTS 0x8000 #define DEBUG_DRI 0x10000 #define DEBUG_SF 0x20000 -#define DEBUG_SANITY 0x40000 -#define DEBUG_SLEEP 0x80000 #define DEBUG_STATS 0x100000 -#define DEBUG_TILE 0x200000 #define DEBUG_WM 0x400000 #define DEBUG_URB 0x800000 #define DEBUG_VS 0x1000000 #define DEBUG_CLIP 0x2000000 +#define DEBUG_AUB 0x4000000 +#define DEBUG_SHADER_TIME 0x8000000 +#define DEBUG_BLORP 0x10000000 +#define DEBUG_NO16 0x20000000 + +#ifdef HAVE_ANDROID_PLATFORM +#define LOG_TAG "INTEL-MESA" +#include +#ifndef ALOGW +#define ALOGW LOGW +#endif +#define dbg_printf(...) ALOGW(__VA_ARGS__) +#else +#define dbg_printf(...) printf(__VA_ARGS__) +#endif /* HAVE_ANDROID_PLATFORM */ #define DBG(...) do { \ if (unlikely(INTEL_DEBUG & FILE_DEBUG_FLAG)) \ - printf(__VA_ARGS__); \ + dbg_printf(__VA_ARGS__); \ } while(0) -#define fallback_debug(...) do { \ - if (unlikely(INTEL_DEBUG & DEBUG_FALLBACKS)) \ - printf(__VA_ARGS__); \ +#define perf_debug(...) do { \ + static GLuint msg_id = 0; \ + if (unlikely(INTEL_DEBUG & DEBUG_PERF)) \ + dbg_printf(__VA_ARGS__); \ + if (intel->perf_debug) \ + _mesa_gl_debug(&intel->ctx, &msg_id, \ + MESA_DEBUG_TYPE_PERFORMANCE, \ + MESA_DEBUG_SEVERITY_MEDIUM, \ + __VA_ARGS__); \ } while(0) +#define WARN_ONCE(cond, fmt...) do { \ + if (unlikely(cond)) { \ + static bool _warned = false; \ + static GLuint msg_id = 0; \ + if (!_warned) { \ + fprintf(stderr, "WARNING: "); \ + fprintf(stderr, fmt); \ + _warned = true; \ + \ + _mesa_gl_debug(ctx, &msg_id, \ + MESA_DEBUG_TYPE_OTHER, \ + MESA_DEBUG_SEVERITY_HIGH, fmt); \ + } \ + } \ +} while (0) + #define PCI_CHIP_845_G 0x2562 #define PCI_CHIP_I830_M 0x3577 #define PCI_CHIP_I855_GM 0x3582 @@ -502,11 +522,14 @@ extern int INTEL_DEBUG; */ extern bool intelInitContext(struct intel_context *intel, - int api, - const struct gl_config * mesaVis, - __DRIcontext * driContextPriv, - void *sharedContextPrivate, - struct dd_function_table *functions); + int api, + unsigned major_version, + unsigned minor_version, + const struct gl_config * mesaVis, + __DRIcontext * driContextPriv, + void *sharedContextPrivate, + struct dd_function_table *functions, + unsigned *dri_ctx_error); extern void intelFinish(struct gl_context * ctx); extern void intel_flush_rendering_to_batch(struct gl_context *ctx); @@ -522,7 +545,6 @@ void intel_init_syncobj_functions(struct dd_function_table *functions); /* ================================================================ * intel_state.c: */ -extern void intelInitStateFuncs(struct dd_function_table *functions); #define COMPAREFUNC_ALWAYS 0 #define COMPAREFUNC_NEVER 0x1 @@ -591,6 +613,10 @@ void intel_update_renderbuffers(__DRIcontext *context, __DRIdrawable *drawable); void intel_prepare_render(struct intel_context *intel); +void +intel_downsample_for_dri2_flush(struct intel_context *intel, + __DRIdrawable *drawable); + void i915_set_buf_info_for_region(uint32_t *state, struct intel_region *region, uint32_t buffer_id); void intel_init_texture_formats(struct gl_context *ctx); @@ -611,4 +637,8 @@ is_power_of_two(uint32_t value) return (value & (value - 1)) == 0; } +#ifdef __cplusplus +} +#endif + #endif