X-Git-Url: https://git.libre-soc.org/?a=blobdiff_plain;f=src%2Fmesa%2Fdrivers%2Fdri%2Fintel%2Fintel_regions.c;h=1172de90b1385776fd188274ea650d225df91c5d;hb=0203136e69bfa711edd69a4f69c4539cd877b5cb;hp=61aefa01b8a184b38e76c6536096e72ee469de37;hpb=f55d0920cd8e504a09e3741716fc47381c03f6ac;p=mesa.git diff --git a/src/mesa/drivers/dri/intel/intel_regions.c b/src/mesa/drivers/dri/intel/intel_regions.c index 61aefa01b8a..1172de90b13 100644 --- a/src/mesa/drivers/dri/intel/intel_regions.c +++ b/src/mesa/drivers/dri/intel/intel_regions.c @@ -42,13 +42,13 @@ #include #include +#include "main/hash.h" #include "intel_context.h" #include "intel_regions.h" #include "intel_blit.h" #include "intel_buffer_objects.h" #include "intel_bufmgr.h" #include "intel_batchbuffer.h" -#include "intel_chipset.h" #define FILE_DEBUG_FLAG DEBUG_REGION @@ -118,8 +118,7 @@ intel_region_map(struct intel_context *intel, struct intel_region *region) if (region->pbo) intel_region_cow(intel, region); - if (region->tiling != I915_TILING_NONE && - intel->intelScreen->kernel_exec_fencing) + if (region->tiling != I915_TILING_NONE) drm_intel_gem_bo_map_gtt(region->buffer); else dri_bo_map(region->buffer, GL_TRUE); @@ -134,8 +133,7 @@ intel_region_unmap(struct intel_context *intel, struct intel_region *region) { _DBG("%s %p\n", __FUNCTION__, region); if (!--region->map_refcount) { - if (region->tiling != I915_TILING_NONE && - intel->intelScreen->kernel_exec_fencing) + if (region->tiling != I915_TILING_NONE) drm_intel_gem_bo_unmap_gtt(region->buffer); else dri_bo_unmap(region->buffer); @@ -166,7 +164,6 @@ intel_region_alloc_internal(struct intel_context *intel, /* Default to no tiling */ region->tiling = I915_TILING_NONE; - region->bit_6_swizzle = I915_BIT_6_SWIZZLE_NONE; _DBG("%s <-- %p\n", __FUNCTION__, region); return region; @@ -175,50 +172,24 @@ intel_region_alloc_internal(struct intel_context *intel, struct intel_region * intel_region_alloc(struct intel_context *intel, uint32_t tiling, - GLuint cpp, GLuint width, GLuint height, GLuint pitch, + GLuint cpp, GLuint width, GLuint height, GLboolean expect_accelerated_upload) { dri_bo *buffer; struct intel_region *region; + unsigned long flags = 0; + unsigned long aligned_pitch; - /* If we're tiled, our allocations are in 8 or 32-row blocks, so - * failure to align our height means that we won't allocate enough pages. - * - * If we're untiled, we still have to align to 2 rows high because the - * data port accesses 2x2 blocks even if the bottom row isn't to be - * rendered, so failure to align means we could walk off the end of the - * GTT and fault. - */ - if (tiling == I915_TILING_X) - height = ALIGN(height, 8); - else if (tiling == I915_TILING_Y) - height = ALIGN(height, 32); - else - height = ALIGN(height, 2); - - /* If we're untiled, we have to align to 2 rows high because the - * data port accesses 2x2 blocks even if the bottom row isn't to be - * rendered, so failure to align means we could walk off the end of the - * GTT and fault. - */ - height = ALIGN(height, 2); - - if (expect_accelerated_upload) { - buffer = drm_intel_bo_alloc_for_render(intel->bufmgr, "region", - pitch * cpp * height, 64); - } else { - buffer = drm_intel_bo_alloc(intel->bufmgr, "region", - pitch * cpp * height, 64); - } + if (expect_accelerated_upload) + flags |= BO_ALLOC_FOR_RENDER; - region = intel_region_alloc_internal(intel, cpp, width, height, - pitch, buffer); + buffer = drm_intel_bo_alloc_tiled(intel->bufmgr, "region", + width, height, cpp, + &tiling, &aligned_pitch, flags); - if (tiling != I915_TILING_NONE) { - assert(((pitch * cpp) & 127) == 0); - drm_intel_bo_set_tiling(buffer, &tiling, pitch * cpp); - drm_intel_bo_get_tiling(buffer, ®ion->tiling, ®ion->bit_6_swizzle); - } + region = intel_region_alloc_internal(intel, cpp, width, height, + aligned_pitch / cpp, buffer); + region->tiling = tiling; return region; } @@ -229,9 +200,24 @@ intel_region_alloc_for_handle(struct intel_context *intel, GLuint width, GLuint height, GLuint pitch, GLuint handle, const char *name) { - struct intel_region *region; + struct intel_region *region, *dummy; dri_bo *buffer; int ret; + uint32_t bit_6_swizzle; + + region = _mesa_HashLookup(intel->intelScreen->named_regions, handle); + if (region != NULL) { + dummy = NULL; + if (region->width != width || region->height != height || + region->cpp != cpp || region->pitch != pitch) { + fprintf(stderr, + "Region for name %d already exists but is not compatible\n", + handle); + return NULL; + } + intel_region_reference(&dummy, region); + return dummy; + } buffer = intel_bo_gem_create_from_name(intel->bufmgr, name, handle); @@ -241,7 +227,7 @@ intel_region_alloc_for_handle(struct intel_context *intel, return region; ret = dri_bo_get_tiling(region->buffer, ®ion->tiling, - ®ion->bit_6_swizzle); + &bit_6_swizzle); if (ret != 0) { fprintf(stderr, "Couldn't get tiling of buffer %d (%s): %s\n", handle, name, strerror(-ret)); @@ -249,6 +235,10 @@ intel_region_alloc_for_handle(struct intel_context *intel, return NULL; } + region->name = handle; + region->screen = intel->intelScreen; + _mesa_HashInsert(intel->intelScreen->named_regions, handle, region); + return region; } @@ -288,10 +278,8 @@ intel_region_release(struct intel_region **region_handle) region->pbo = NULL; dri_bo_unreference(region->buffer); - if (region->classic_map != NULL) { - drmUnmap(region->classic_map, - region->pitch * region->cpp * region->height); - } + if (region->name > 0) + _mesa_HashRemove(region->screen->named_regions, region->name); free(region); } @@ -319,7 +307,7 @@ _mesa_copy_rect(GLubyte * dst, dst += dst_x * cpp; src += src_x * cpp; dst += dst_y * dst_pitch; - src += src_y * dst_pitch; + src += src_y * src_pitch; width *= cpp; if (width == dst_pitch && width == src_pitch) @@ -362,6 +350,8 @@ intel_region_data(struct intel_context *intel, intel_region_cow(intel, dst); } + intel_prepare_render(intel); + _mesa_copy_rect(intel_region_map(intel, dst) + dst_offset, dst->cpp, dst->pitch, @@ -381,8 +371,11 @@ intel_region_copy(struct intel_context *intel, struct intel_region *src, GLuint src_offset, GLuint srcx, GLuint srcy, GLuint width, GLuint height, + GLboolean flip, GLenum logicop) { + uint32_t src_pitch = src->pitch; + _DBG("%s\n", __FUNCTION__); if (intel == NULL) @@ -398,9 +391,12 @@ intel_region_copy(struct intel_context *intel, assert(src->cpp == dst->cpp); + if (flip) + src_pitch = -src_pitch; + return intelEmitCopyBlit(intel, dst->cpp, - src->pitch, src->buffer, src_offset, src->tiling, + src_pitch, src->buffer, src_offset, src->tiling, dst->pitch, dst->buffer, dst_offset, dst->tiling, srcx, srcy, dstx, dsty, width, height, logicop); @@ -443,6 +439,7 @@ intel_region_attach_pbo(struct intel_context *intel, region->pbo->region = region; dri_bo_reference(buffer); region->buffer = buffer; + region->tiling = I915_TILING_NONE; } @@ -483,6 +480,7 @@ intel_region_cow(struct intel_context *intel, struct intel_region *region) /* Now blit from the texture buffer to the new buffer: */ + intel_prepare_render(intel); ok = intelEmitCopyBlit(intel, region->cpp, region->pitch, pbo->buffer, 0, region->tiling,