X-Git-Url: https://git.libre-soc.org/?a=blobdiff_plain;f=src%2Fmesa%2Fdrivers%2Fdri%2Fr200%2Fr200_state_init.c;h=41c3df710e51359a51fb2722184760ff011f1f17;hb=43d66c8c2d4d3d4dee1309856b6ce6c5393682e5;hp=4e8075eabc97649fecb7def04aec30e429ace0ec;hpb=a1af8eec66c5f7ec421e8011b41c1a7c36319f9f;p=mesa.git diff --git a/src/mesa/drivers/dri/r200/r200_state_init.c b/src/mesa/drivers/dri/r200/r200_state_init.c index 4e8075eabc9..41c3df710e5 100644 --- a/src/mesa/drivers/dri/r200/r200_state_init.c +++ b/src/mesa/drivers/dri/r200/r200_state_init.c @@ -28,14 +28,15 @@ WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. /* * Authors: - * Keith Whitwell + * Keith Whitwell */ +#include "main/errors.h" #include "main/glheader.h" #include "main/imports.h" #include "main/enums.h" -#include "main/colormac.h" #include "main/api_arrayelt.h" +#include "main/state.h" #include "swrast/swrast.h" #include "vbo/vbo.h" @@ -49,7 +50,7 @@ WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. #include "r200_state.h" #include "radeon_queryobj.h" -#include "xmlpool.h" +#include "util/xmlpool.h" /* New (1.3) state mechanism. 3 commands (packet, scalar, vector) in * 1.3 cmdbuffers allow all previous state to be updated as well as @@ -165,16 +166,7 @@ static struct { */ static int cmdpkt( r200ContextPtr rmesa, int id ) { - drm_radeon_cmd_header_t h; - - if (rmesa->radeon.radeonScreen->kernel_mm) { - return CP_PACKET0(packet[id].start, packet[id].len - 1); - } else { - h.i = 0; - h.packet.cmd_type = RADEON_CMD_PACKET; - h.packet.packet_id = id; - } - return h.i; + return CP_PACKET0(packet[id].start, packet[id].len - 1); } static int cmdvec( int offset, int stride, int count ) @@ -228,7 +220,7 @@ static int cmdscl2( int offset, int stride, int count ) * If it is active check function returns maximum emit size. */ #define CHECK( NM, FLAG, ADD ) \ -static int check_##NM( GLcontext *ctx, struct radeon_state_atom *atom) \ +static int check_##NM( struct gl_context *ctx, struct radeon_state_atom *atom) \ { \ r200ContextPtr rmesa = R200_CONTEXT(ctx); \ (void) rmesa; \ @@ -236,60 +228,53 @@ static int check_##NM( GLcontext *ctx, struct radeon_state_atom *atom) \ } #define TCL_CHECK( NM, FLAG, ADD ) \ -static int check_##NM( GLcontext *ctx, struct radeon_state_atom *atom) \ +static int check_##NM( struct gl_context *ctx, struct radeon_state_atom *atom) \ { \ r200ContextPtr rmesa = R200_CONTEXT(ctx); \ - return (!rmesa->radeon.TclFallback && !ctx->VertexProgram._Enabled && (FLAG)) ? atom->cmd_size + (ADD) : 0; \ + return (!rmesa->radeon.TclFallback && !_mesa_arb_vertex_program_enabled(ctx) && (FLAG)) ? atom->cmd_size + (ADD) : 0; \ } #define TCL_OR_VP_CHECK( NM, FLAG, ADD ) \ -static int check_##NM( GLcontext *ctx, struct radeon_state_atom *atom ) \ +static int check_##NM( struct gl_context *ctx, struct radeon_state_atom *atom ) \ { \ r200ContextPtr rmesa = R200_CONTEXT(ctx); \ return (!rmesa->radeon.TclFallback && (FLAG)) ? atom->cmd_size + (ADD) : 0; \ } #define VP_CHECK( NM, FLAG, ADD ) \ -static int check_##NM( GLcontext *ctx, struct radeon_state_atom *atom ) \ +static int check_##NM( struct gl_context *ctx, struct radeon_state_atom *atom ) \ { \ r200ContextPtr rmesa = R200_CONTEXT(ctx); \ (void) atom; \ - return (!rmesa->radeon.TclFallback && ctx->VertexProgram._Enabled && (FLAG)) ? atom->cmd_size + (ADD) : 0; \ + return (!rmesa->radeon.TclFallback && _mesa_arb_vertex_program_enabled(ctx) && (FLAG)) ? atom->cmd_size + (ADD) : 0; \ } CHECK( always, GL_TRUE, 0 ) CHECK( always_add4, GL_TRUE, 4 ) CHECK( never, GL_FALSE, 0 ) -CHECK( tex_any, ctx->Texture._EnabledUnits, 0 ) -CHECK( tf, (ctx->Texture._EnabledUnits && !ctx->ATIFragmentShader._Enabled), 0 ); -CHECK( pix_zero, !ctx->ATIFragmentShader._Enabled, 0 ) - CHECK( texenv, (rmesa->state.envneeded & (1 << (atom->idx)) && !ctx->ATIFragmentShader._Enabled), 0 ) -CHECK( afs_pass1, (ctx->ATIFragmentShader._Enabled && (ctx->ATIFragmentShader.Current->NumPasses > 1)), 0 ) -CHECK( afs, ctx->ATIFragmentShader._Enabled, 0 ) +CHECK( tex_any, ctx->Texture._MaxEnabledTexImageUnit != -1, 0 ) +CHECK( tf, (ctx->Texture._MaxEnabledTexImageUnit != -1 && !_mesa_ati_fragment_shader_enabled(ctx)), 0 ); +CHECK( pix_zero, !_mesa_ati_fragment_shader_enabled(ctx), 0 ) +CHECK( texenv, (rmesa->state.envneeded & (1 << (atom->idx)) && !_mesa_ati_fragment_shader_enabled(ctx)), 0 ) +CHECK( afs_pass1, (_mesa_ati_fragment_shader_enabled(ctx) && (ctx->ATIFragmentShader.Current->NumPasses > 1)), 0 ) +CHECK( afs, _mesa_ati_fragment_shader_enabled(ctx), 0 ) CHECK( tex_cube, rmesa->state.texture.unit[atom->idx].unitneeded & TEXTURE_CUBE_BIT, 3 + 3*5 - CUBE_STATE_SIZE ) CHECK( tex_cube_cs, rmesa->state.texture.unit[atom->idx].unitneeded & TEXTURE_CUBE_BIT, 2 + 4*5 - CUBE_STATE_SIZE ) -TCL_CHECK( tcl_fog, ctx->Fog.Enabled, 0 ) TCL_CHECK( tcl_fog_add4, ctx->Fog.Enabled, 4 ) TCL_CHECK( tcl, GL_TRUE, 0 ) TCL_CHECK( tcl_add8, GL_TRUE, 8 ) TCL_CHECK( tcl_add4, GL_TRUE, 4 ) -TCL_CHECK( tcl_tex, rmesa->state.texture.unit[atom->idx].unitneeded, 0 ) -TCL_CHECK( tcl_lighting, ctx->Light.Enabled, 0 ) -TCL_CHECK( tcl_light, ctx->Light.Enabled && ctx->Light.Light[atom->idx].Enabled, 0 ) TCL_CHECK( tcl_tex_add4, rmesa->state.texture.unit[atom->idx].unitneeded, 4 ) TCL_CHECK( tcl_lighting_add4, ctx->Light.Enabled, 4 ) TCL_CHECK( tcl_lighting_add6, ctx->Light.Enabled, 6 ) -TCL_CHECK( tcl_light_add8, ctx->Light.Enabled && ctx->Light.Light[atom->idx].Enabled, 8 ) -TCL_OR_VP_CHECK( tcl_ucp, (ctx->Transform.ClipPlanesEnabled & (1 << (atom->idx))), 0 ) +TCL_CHECK( tcl_light_add6, ctx->Light.Enabled && ctx->Light.Light[atom->idx].Enabled, 6 ) TCL_OR_VP_CHECK( tcl_ucp_add4, (ctx->Transform.ClipPlanesEnabled & (1 << (atom->idx))), 4 ) TCL_OR_VP_CHECK( tcl_or_vp, GL_TRUE, 0 ) TCL_OR_VP_CHECK( tcl_or_vp_add2, GL_TRUE, 2 ) VP_CHECK( tcl_vp, GL_TRUE, 0 ) VP_CHECK( tcl_vp_add4, GL_TRUE, 4 ) -VP_CHECK( tcl_vp_size, ctx->VertexProgram.Current->Base.NumNativeInstructions > 64, 0 ) -VP_CHECK( tcl_vpp_size, ctx->VertexProgram.Current->Base.NumNativeParameters > 96, 0 ) -VP_CHECK( tcl_vp_size_add4, ctx->VertexProgram.Current->Base.NumNativeInstructions > 64, 4 ) -VP_CHECK( tcl_vpp_size_add4, ctx->VertexProgram.Current->Base.NumNativeParameters > 96, 4 ) +VP_CHECK( tcl_vp_size_add4, ctx->VertexProgram.Current->arb.NumNativeInstructions > 64, 4 ) +VP_CHECK( tcl_vpp_size_add4, ctx->VertexProgram.Current->arb.NumNativeParameters > 96, 4 ) #define OUT_VEC(hdr, data) do { \ drm_radeon_cmd_header_t h; \ @@ -308,8 +293,8 @@ VP_CHECK( tcl_vpp_size_add4, ctx->VertexProgram.Current->Base.NumNativeParameter h.i = hdr; \ _start = h.veclinear.addr_lo | (h.veclinear.addr_hi << 8); \ _sz = h.veclinear.count * 4; \ - if (r200->radeon.radeonScreen->kernel_mm && _sz) { \ - BEGIN_BATCH_NO_AUTOSTATE(dwords); \ + if (_sz) { \ + BEGIN_BATCH(dwords); \ OUT_BATCH(CP_PACKET0(RADEON_SE_TCL_STATE_FLUSH, 0)); \ OUT_BATCH(0); \ OUT_BATCH(CP_PACKET0(R200_SE_TCL_VECTOR_INDX_REG, 0)); \ @@ -337,7 +322,7 @@ VP_CHECK( tcl_vpp_size_add4, ctx->VertexProgram.Current->Base.NumNativeParameter OUT_BATCH(CP_PACKET0_ONE(R200_SE_TCL_SCALAR_DATA_REG, h.scalars.count - 1)); \ OUT_BATCH_TABLE((data), h.scalars.count); \ } while(0) -static int check_rrb(GLcontext *ctx, struct radeon_state_atom *atom) +static int check_rrb(struct gl_context *ctx, struct radeon_state_atom *atom) { r200ContextPtr r200 = R200_CONTEXT(ctx); struct radeon_renderbuffer *rrb; @@ -347,43 +332,52 @@ static int check_rrb(GLcontext *ctx, struct radeon_state_atom *atom) return atom->cmd_size; } -static void mtl_emit(GLcontext *ctx, struct radeon_state_atom *atom) +static int check_polygon_stipple(struct gl_context *ctx, + struct radeon_state_atom *atom) +{ + r200ContextPtr r200 = R200_CONTEXT(ctx); + if (r200->hw.set.cmd[SET_RE_CNTL] & R200_STIPPLE_ENABLE) + return atom->cmd_size; + return 0; +} + +static void mtl_emit(struct gl_context *ctx, struct radeon_state_atom *atom) { r200ContextPtr r200 = R200_CONTEXT(ctx); BATCH_LOCALS(&r200->radeon); uint32_t dwords = atom->check(ctx, atom); - BEGIN_BATCH_NO_AUTOSTATE(dwords); + BEGIN_BATCH(dwords); OUT_VEC(atom->cmd[MTL_CMD_0], (atom->cmd+1)); OUT_SCL2(atom->cmd[MTL_CMD_1], (atom->cmd + 18)); END_BATCH(); } -static void lit_emit(GLcontext *ctx, struct radeon_state_atom *atom) +static void lit_emit(struct gl_context *ctx, struct radeon_state_atom *atom) { r200ContextPtr r200 = R200_CONTEXT(ctx); BATCH_LOCALS(&r200->radeon); uint32_t dwords = atom->check(ctx, atom); - BEGIN_BATCH_NO_AUTOSTATE(dwords); + BEGIN_BATCH(dwords); OUT_VEC(atom->cmd[LIT_CMD_0], atom->cmd+1); - OUT_VEC(atom->cmd[LIT_CMD_1], atom->cmd+LIT_CMD_1+1); + OUT_SCL(atom->cmd[LIT_CMD_1], atom->cmd+LIT_CMD_1+1); END_BATCH(); } -static void ptp_emit(GLcontext *ctx, struct radeon_state_atom *atom) +static void ptp_emit(struct gl_context *ctx, struct radeon_state_atom *atom) { r200ContextPtr r200 = R200_CONTEXT(ctx); BATCH_LOCALS(&r200->radeon); uint32_t dwords = atom->check(ctx, atom); - BEGIN_BATCH_NO_AUTOSTATE(dwords); + BEGIN_BATCH(dwords); OUT_VEC(atom->cmd[PTP_CMD_0], atom->cmd+1); OUT_VEC(atom->cmd[PTP_CMD_1], atom->cmd+PTP_CMD_1+1); END_BATCH(); } -static void veclinear_emit(GLcontext *ctx, struct radeon_state_atom *atom) +static void veclinear_emit(struct gl_context *ctx, struct radeon_state_atom *atom) { r200ContextPtr r200 = R200_CONTEXT(ctx); BATCH_LOCALS(&r200->radeon); @@ -392,97 +386,30 @@ static void veclinear_emit(GLcontext *ctx, struct radeon_state_atom *atom) OUT_VECLINEAR(atom->cmd[0], atom->cmd+1); } -static void scl_emit(GLcontext *ctx, struct radeon_state_atom *atom) +static void scl_emit(struct gl_context *ctx, struct radeon_state_atom *atom) { r200ContextPtr r200 = R200_CONTEXT(ctx); BATCH_LOCALS(&r200->radeon); uint32_t dwords = atom->check(ctx, atom); - BEGIN_BATCH_NO_AUTOSTATE(dwords); + BEGIN_BATCH(dwords); OUT_SCL(atom->cmd[0], atom->cmd+1); END_BATCH(); } -static void vec_emit(GLcontext *ctx, struct radeon_state_atom *atom) +static void vec_emit(struct gl_context *ctx, struct radeon_state_atom *atom) { r200ContextPtr r200 = R200_CONTEXT(ctx); BATCH_LOCALS(&r200->radeon); uint32_t dwords = atom->check(ctx, atom); - BEGIN_BATCH_NO_AUTOSTATE(dwords); + BEGIN_BATCH(dwords); OUT_VEC(atom->cmd[0], atom->cmd+1); END_BATCH(); } -static void ctx_emit(GLcontext *ctx, struct radeon_state_atom *atom) -{ - r200ContextPtr r200 = R200_CONTEXT(ctx); - BATCH_LOCALS(&r200->radeon); - struct radeon_renderbuffer *rrb; - uint32_t cbpitch; - uint32_t zbpitch, depth_fmt; - uint32_t dwords = atom->check(ctx, atom); - - /* output the first 7 bytes of context */ - BEGIN_BATCH_NO_AUTOSTATE(dwords); - OUT_BATCH_TABLE(atom->cmd, 5); - - rrb = radeon_get_depthbuffer(&r200->radeon); - if (!rrb) { - OUT_BATCH(0); - OUT_BATCH(0); - } else { - zbpitch = (rrb->pitch / rrb->cpp); - if (r200->using_hyperz) - zbpitch |= RADEON_DEPTH_HYPERZ; - OUT_BATCH_RELOC(0, rrb->bo, 0, 0, RADEON_GEM_DOMAIN_VRAM, 0); - OUT_BATCH(zbpitch); - if (rrb->cpp == 4) - depth_fmt = RADEON_DEPTH_FORMAT_24BIT_INT_Z; - else - depth_fmt = RADEON_DEPTH_FORMAT_16BIT_INT_Z; - atom->cmd[CTX_RB3D_ZSTENCILCNTL] &= ~RADEON_DEPTH_FORMAT_MASK; - atom->cmd[CTX_RB3D_ZSTENCILCNTL] |= depth_fmt; - } - - OUT_BATCH(atom->cmd[CTX_RB3D_ZSTENCILCNTL]); - OUT_BATCH(atom->cmd[CTX_CMD_1]); - OUT_BATCH(atom->cmd[CTX_PP_CNTL]); - - rrb = radeon_get_colorbuffer(&r200->radeon); - if (!rrb || !rrb->bo) { - OUT_BATCH(atom->cmd[CTX_RB3D_CNTL]); - OUT_BATCH(atom->cmd[CTX_RB3D_COLOROFFSET]); - } else { - atom->cmd[CTX_RB3D_CNTL] &= ~(0xf << 10); - if (rrb->cpp == 4) - atom->cmd[CTX_RB3D_CNTL] |= RADEON_COLOR_FORMAT_ARGB8888; - else - atom->cmd[CTX_RB3D_CNTL] |= RADEON_COLOR_FORMAT_RGB565; - - OUT_BATCH(atom->cmd[CTX_RB3D_CNTL]); - OUT_BATCH_RELOC(0, rrb->bo, 0, 0, RADEON_GEM_DOMAIN_VRAM, 0); - } - - OUT_BATCH(atom->cmd[CTX_CMD_2]); - - if (!rrb || !rrb->bo) { - OUT_BATCH(atom->cmd[CTX_RB3D_COLORPITCH]); - } else { - cbpitch = (rrb->pitch / rrb->cpp); - if (rrb->bo->flags & RADEON_BO_FLAGS_MACRO_TILE) - cbpitch |= R200_COLOR_TILE_ENABLE; - OUT_BATCH(cbpitch); - } - - if (atom->cmd_size == CTX_STATE_SIZE_NEWDRM) - OUT_BATCH_TABLE((atom->cmd + 14), 4); - - END_BATCH(); -} - -static int check_always_ctx( GLcontext *ctx, struct radeon_state_atom *atom) +static int check_always_ctx( struct gl_context *ctx, struct radeon_state_atom *atom) { r200ContextPtr r200 = R200_CONTEXT(ctx); struct radeon_renderbuffer *rrb, *drb; @@ -507,7 +434,7 @@ static int check_always_ctx( GLcontext *ctx, struct radeon_state_atom *atom) return dwords; } -static void ctx_emit_cs(GLcontext *ctx, struct radeon_state_atom *atom) +static void ctx_emit_cs(struct gl_context *ctx, struct radeon_state_atom *atom) { r200ContextPtr r200 = R200_CONTEXT(ctx); BATCH_LOCALS(&r200->radeon); @@ -525,14 +452,17 @@ static void ctx_emit_cs(GLcontext *ctx, struct radeon_state_atom *atom) atom->cmd[CTX_RB3D_CNTL] &= ~(0xf << 10); if (rrb->cpp == 4) atom->cmd[CTX_RB3D_CNTL] |= RADEON_COLOR_FORMAT_ARGB8888; - else switch (rrb->base.Format) { - case MESA_FORMAT_RGB565: + else switch (rrb->base.Base.Format) { + case MESA_FORMAT_B5G6R5_UNORM: + case MESA_FORMAT_R5G6B5_UNORM: atom->cmd[CTX_RB3D_CNTL] |= RADEON_COLOR_FORMAT_RGB565; break; - case MESA_FORMAT_ARGB4444: + case MESA_FORMAT_B4G4R4A4_UNORM: + case MESA_FORMAT_A4R4G4B4_UNORM: atom->cmd[CTX_RB3D_CNTL] |= RADEON_COLOR_FORMAT_ARGB4444; break; - case MESA_FORMAT_ARGB1555: + case MESA_FORMAT_B5G5R5A1_UNORM: + case MESA_FORMAT_A1R5G5B5_UNORM: atom->cmd[CTX_RB3D_CNTL] |= RADEON_COLOR_FORMAT_ARGB1555; break; default: @@ -542,6 +472,9 @@ static void ctx_emit_cs(GLcontext *ctx, struct radeon_state_atom *atom) cbpitch = (rrb->pitch / rrb->cpp); if (rrb->bo->flags & RADEON_BO_FLAGS_MACRO_TILE) cbpitch |= R200_COLOR_TILE_ENABLE; + if (rrb->bo->flags & RADEON_BO_FLAGS_MICRO_TILE) + cbpitch |= R200_COLOR_MICROTILE_ENABLE; + drb = radeon_get_depthbuffer(&r200->radeon); if (drb) { @@ -555,7 +488,7 @@ static void ctx_emit_cs(GLcontext *ctx, struct radeon_state_atom *atom) } /* output the first 7 bytes of context */ - BEGIN_BATCH_NO_AUTOSTATE(dwords); + BEGIN_BATCH(dwords); /* In the CS case we need to split this up */ OUT_BATCH(CP_PACKET0(packet[0].start, 3)); @@ -578,7 +511,7 @@ static void ctx_emit_cs(GLcontext *ctx, struct radeon_state_atom *atom) if (rrb) { OUT_BATCH(CP_PACKET0(RADEON_RB3D_COLOROFFSET, 0)); - OUT_BATCH_RELOC(0, rrb->bo, 0, 0, RADEON_GEM_DOMAIN_VRAM, 0); + OUT_BATCH_RELOC(rrb->draw_offset, rrb->bo, rrb->draw_offset, 0, RADEON_GEM_DOMAIN_VRAM, 0); OUT_BATCH(CP_PACKET0(RADEON_RB3D_COLORPITCH, 0)); OUT_BATCH_RELOC(cbpitch, rrb->bo, cbpitch, 0, RADEON_GEM_DOMAIN_VRAM, 0); @@ -591,64 +524,7 @@ static void ctx_emit_cs(GLcontext *ctx, struct radeon_state_atom *atom) END_BATCH(); } -static int get_tex_size(GLcontext* ctx, struct radeon_state_atom *atom) -{ - r200ContextPtr r200 = R200_CONTEXT(ctx); - uint32_t dwords = atom->cmd_size + 2; - int i = atom->idx; - radeonTexObj *t = r200->state.texture.unit[i].texobj; - if (!(t && t->mt && !t->image_override)) - dwords -= 2; - - return dwords; -} - -static int check_tex_pair(GLcontext* ctx, struct radeon_state_atom *atom) -{ - r200ContextPtr r200 = R200_CONTEXT(ctx); - /** XOR is bit flip operation so use it for finding pair */ - if (!(r200->state.texture.unit[atom->idx].unitneeded | r200->state.texture.unit[atom->idx ^ 1].unitneeded)) - return 0; - - return get_tex_size(ctx, atom); -} - -static int check_tex(GLcontext* ctx, struct radeon_state_atom *atom) -{ - r200ContextPtr r200 = R200_CONTEXT(ctx); - if (!(r200->state.texture.unit[atom->idx].unitneeded)) - return 0; - - return get_tex_size(ctx, atom); -} - - -static void tex_emit(GLcontext *ctx, struct radeon_state_atom *atom) -{ - r200ContextPtr r200 = R200_CONTEXT(ctx); - BATCH_LOCALS(&r200->radeon); - uint32_t dwords = atom->check(ctx, atom); - int i = atom->idx; - radeonTexObj *t = r200->state.texture.unit[i].texobj; - - BEGIN_BATCH_NO_AUTOSTATE(dwords); - /* is this ok even with drm older than 1.18? */ - OUT_BATCH_TABLE(atom->cmd, 10); - - if (t && t->mt && !t->image_override) { - OUT_BATCH_RELOC(t->tile_bits, t->mt->bo, get_base_teximage_offset(t), - RADEON_GEM_DOMAIN_GTT|RADEON_GEM_DOMAIN_VRAM, 0, 0); - } else if (!t) { - /* workaround for old CS mechanism */ - OUT_BATCH(r200->radeon.radeonScreen->texOffset[RADEON_LOCAL_TEX_HEAP]); - } else { - OUT_BATCH(t->override_offset); - } - - END_BATCH(); -} - -static int get_tex_mm_size(GLcontext* ctx, struct radeon_state_atom *atom) +static int get_tex_mm_size(struct gl_context* ctx, struct radeon_state_atom *atom) { r200ContextPtr r200 = R200_CONTEXT(ctx); uint32_t dwords = atom->cmd_size + 2; @@ -667,7 +543,7 @@ static int get_tex_mm_size(GLcontext* ctx, struct radeon_state_atom *atom) return dwords; } -static int check_tex_pair_mm(GLcontext* ctx, struct radeon_state_atom *atom) +static int check_tex_pair_mm(struct gl_context* ctx, struct radeon_state_atom *atom) { r200ContextPtr r200 = R200_CONTEXT(ctx); /** XOR is bit flip operation so use it for finding pair */ @@ -677,7 +553,7 @@ static int check_tex_pair_mm(GLcontext* ctx, struct radeon_state_atom *atom) return get_tex_mm_size(ctx, atom); } -static int check_tex_mm(GLcontext* ctx, struct radeon_state_atom *atom) +static int check_tex_mm(struct gl_context* ctx, struct radeon_state_atom *atom) { r200ContextPtr r200 = R200_CONTEXT(ctx); if (!(r200->state.texture.unit[atom->idx].unitneeded)) @@ -687,7 +563,7 @@ static int check_tex_mm(GLcontext* ctx, struct radeon_state_atom *atom) } -static void tex_emit_mm(GLcontext *ctx, struct radeon_state_atom *atom) +static void tex_emit_mm(struct gl_context *ctx, struct radeon_state_atom *atom) { r200ContextPtr r200 = R200_CONTEXT(ctx); BATCH_LOCALS(&r200->radeon); @@ -697,7 +573,7 @@ static void tex_emit_mm(GLcontext *ctx, struct radeon_state_atom *atom) if (!r200->state.texture.unit[i].unitneeded && !(dwords <= atom->cmd_size)) dwords -= 4; - BEGIN_BATCH_NO_AUTOSTATE(dwords); + BEGIN_BATCH(dwords); OUT_BATCH(CP_PACKET0(R200_PP_TXFILTER_0 + (32 * i), 7)); OUT_BATCH_TABLE((atom->cmd + 1), 8); @@ -716,35 +592,7 @@ static void tex_emit_mm(GLcontext *ctx, struct radeon_state_atom *atom) END_BATCH(); } - -static void cube_emit(GLcontext *ctx, struct radeon_state_atom *atom) -{ - r200ContextPtr r200 = R200_CONTEXT(ctx); - BATCH_LOCALS(&r200->radeon); - uint32_t dwords = atom->check(ctx, atom); - int i = atom->idx, j; - radeonTexObj *t = r200->state.texture.unit[i].texobj; - radeon_mipmap_level *lvl; - - if (!(t && !t->image_override)) - dwords = 2; - - BEGIN_BATCH_NO_AUTOSTATE(dwords); - /* XXX that size won't really match with image_override... */ - OUT_BATCH_TABLE(atom->cmd, 2); - - if (t && !t->image_override) { - lvl = &t->mt->levels[0]; - OUT_BATCH_TABLE((atom->cmd + 2), 1); - for (j = 1; j <= 5; j++) { - OUT_BATCH_RELOC(lvl->faces[j].offset, t->mt->bo, lvl->faces[j].offset, - RADEON_GEM_DOMAIN_VRAM, 0, 0); - } - } - END_BATCH(); -} - -static void cube_emit_cs(GLcontext *ctx, struct radeon_state_atom *atom) +static void cube_emit_cs(struct gl_context *ctx, struct radeon_state_atom *atom) { r200ContextPtr r200 = R200_CONTEXT(ctx); BATCH_LOCALS(&r200->radeon); @@ -755,7 +603,7 @@ static void cube_emit_cs(GLcontext *ctx, struct radeon_state_atom *atom) if (!(t && !t->image_override)) dwords = 2; - BEGIN_BATCH_NO_AUTOSTATE(dwords); + BEGIN_BATCH(dwords); OUT_BATCH_TABLE(atom->cmd, 2); if (t && !t->image_override) { @@ -773,23 +621,9 @@ static void cube_emit_cs(GLcontext *ctx, struct radeon_state_atom *atom) */ void r200InitState( r200ContextPtr rmesa ) { - GLcontext *ctx = rmesa->radeon.glCtx; + struct gl_context *ctx = &rmesa->radeon.glCtx; GLuint i; - rmesa->radeon.state.color.clear = 0x00000000; - - switch ( ctx->Visual.depthBits ) { - case 16: - rmesa->radeon.state.depth.clear = 0x0000ffff; - rmesa->radeon.state.stencil.clear = 0x00000000; - break; - case 24: - default: - rmesa->radeon.state.depth.clear = 0x00ffffff; - rmesa->radeon.state.stencil.clear = 0xffff0000; - break; - } - rmesa->radeon.Fallback = 0; rmesa->radeon.hw.max_state_size = 0; @@ -797,8 +631,8 @@ void r200InitState( r200ContextPtr rmesa ) #define ALLOC_STATE( ATOM, CHK, SZ, NM, IDX ) \ do { \ rmesa->hw.ATOM.cmd_size = SZ; \ - rmesa->hw.ATOM.cmd = (GLuint *)CALLOC(SZ * sizeof(int)); \ - rmesa->hw.ATOM.lastcmd = (GLuint *)CALLOC(SZ * sizeof(int)); \ + rmesa->hw.ATOM.cmd = (GLuint *) calloc(SZ, sizeof(int)); \ + rmesa->hw.ATOM.lastcmd = (GLuint *) calloc(SZ, sizeof(int)); \ rmesa->hw.ATOM.name = NM; \ rmesa->hw.ATOM.idx = IDX; \ if (check_##CHK != check_never) { \ @@ -813,20 +647,10 @@ void r200InitState( r200ContextPtr rmesa ) /* Allocate state buffers: */ - if (rmesa->radeon.radeonScreen->drmSupportsBlendColor) - ALLOC_STATE( ctx, always_add4, CTX_STATE_SIZE_NEWDRM, "CTX/context", 0 ); - else - ALLOC_STATE( ctx, always_add4, CTX_STATE_SIZE_OLDDRM, "CTX/context", 0 ); + ALLOC_STATE( ctx, always_add4, CTX_STATE_SIZE_NEWDRM, "CTX/context", 0 ); - if (rmesa->radeon.radeonScreen->kernel_mm) - { - rmesa->hw.ctx.emit = ctx_emit_cs; - rmesa->hw.ctx.check = check_always_ctx; - } - else - { - rmesa->hw.ctx.emit = ctx_emit; - } + rmesa->hw.ctx.emit = ctx_emit_cs; + rmesa->hw.ctx.check = check_always_ctx; ALLOC_STATE( set, always, SET_STATE_SIZE, "SET/setup", 0 ); ALLOC_STATE( lin, always, LIN_STATE_SIZE, "LIN/line", 0 ); ALLOC_STATE( msk, always, MSK_STATE_SIZE, "MSK/mask", 0 ); @@ -840,192 +664,90 @@ void r200InitState( r200ContextPtr rmesa ) ALLOC_STATE( tf, tf, TF_STATE_SIZE, "TF/tfactor", 0 ); { int state_size = TEX_STATE_SIZE_NEWDRM; - if (!rmesa->radeon.radeonScreen->drmSupportsFragShader) { - state_size = TEX_STATE_SIZE_OLDDRM; + if (rmesa->radeon.radeonScreen->chip_family == CHIP_FAMILY_R200) { + /* make sure texture units 0/1 are emitted pair-wise for r200 t0 hang workaround */ + ALLOC_STATE( tex[0], tex_pair_mm, state_size, "TEX/tex-0", 0 ); + ALLOC_STATE( tex[1], tex_pair_mm, state_size, "TEX/tex-1", 1 ); + ALLOC_STATE( tam, tex_any, TAM_STATE_SIZE, "TAM/tam", 0 ); } - if (rmesa->radeon.radeonScreen->drmSupportsFragShader) { - if (rmesa->radeon.radeonScreen->chip_family == CHIP_FAMILY_R200) { - /* make sure texture units 0/1 are emitted pair-wise for r200 t0 hang workaround */ - ALLOC_STATE( tex[0], tex_pair_mm, state_size, "TEX/tex-0", 0 ); - ALLOC_STATE( tex[1], tex_pair_mm, state_size, "TEX/tex-1", 1 ); - ALLOC_STATE( tam, tex_any, TAM_STATE_SIZE, "TAM/tam", 0 ); - } - else { - ALLOC_STATE( tex[0], tex_mm, state_size, "TEX/tex-0", 0 ); - ALLOC_STATE( tex[1], tex_mm, state_size, "TEX/tex-1", 1 ); - ALLOC_STATE( tam, never, TAM_STATE_SIZE, "TAM/tam", 0 ); - } - ALLOC_STATE( tex[2], tex_mm, state_size, "TEX/tex-2", 2 ); - ALLOC_STATE( tex[3], tex_mm, state_size, "TEX/tex-3", 3 ); - ALLOC_STATE( tex[4], tex_mm, state_size, "TEX/tex-4", 4 ); - ALLOC_STATE( tex[5], tex_mm, state_size, "TEX/tex-5", 5 ); - if (!rmesa->radeon.radeonScreen->kernel_mm) - { - if (rmesa->radeon.radeonScreen->chip_family == CHIP_FAMILY_R200) { - rmesa->hw.tex[0].check = check_tex_pair; - rmesa->hw.tex[1].check = check_tex_pair; - } else { - rmesa->hw.tex[0].check = check_tex; - rmesa->hw.tex[1].check = check_tex; - } - rmesa->hw.tex[2].check = check_tex; - rmesa->hw.tex[3].check = check_tex; - rmesa->hw.tex[4].check = check_tex; - rmesa->hw.tex[5].check = check_tex; - } - if (rmesa->radeon.radeonScreen->drmSupportsFragShader) { - ALLOC_STATE( atf, afs, ATF_STATE_SIZE, "ATF/tfactor", 0 ); - ALLOC_STATE( afs[0], afs_pass1, AFS_STATE_SIZE, "AFS/afsinst-0", 0 ); - ALLOC_STATE( afs[1], afs, AFS_STATE_SIZE, "AFS/afsinst-1", 1 ); - } else { - ALLOC_STATE( atf, never, ATF_STATE_SIZE, "ATF/tfactor", 0 ); - ALLOC_STATE( afs[0], never, AFS_STATE_SIZE, "AFS/afsinst-0", 0 ); - ALLOC_STATE( afs[1], never, AFS_STATE_SIZE, "AFS/afsinst-1", 1 ); - } + else { + ALLOC_STATE( tex[0], tex_mm, state_size, "TEX/tex-0", 0 ); + ALLOC_STATE( tex[1], tex_mm, state_size, "TEX/tex-1", 1 ); + ALLOC_STATE( tam, never, TAM_STATE_SIZE, "TAM/tam", 0 ); } + ALLOC_STATE( tex[2], tex_mm, state_size, "TEX/tex-2", 2 ); + ALLOC_STATE( tex[3], tex_mm, state_size, "TEX/tex-3", 3 ); + ALLOC_STATE( tex[4], tex_mm, state_size, "TEX/tex-4", 4 ); + ALLOC_STATE( tex[5], tex_mm, state_size, "TEX/tex-5", 5 ); + ALLOC_STATE( atf, afs, ATF_STATE_SIZE, "ATF/tfactor", 0 ); + ALLOC_STATE( afs[0], afs_pass1, AFS_STATE_SIZE, "AFS/afsinst-0", 0 ); + ALLOC_STATE( afs[1], afs, AFS_STATE_SIZE, "AFS/afsinst-1", 1 ); } - ALLOC_STATE( stp, always, STP_STATE_SIZE, "STP/stp", 0 ); + ALLOC_STATE( stp, polygon_stipple, STP_STATE_SIZE, "STP/stp", 0 ); for (i = 0; i < 6; i++) - if (rmesa->radeon.radeonScreen->kernel_mm) - rmesa->hw.tex[i].emit = tex_emit_mm; - else - rmesa->hw.tex[i].emit = tex_emit; - if (rmesa->radeon.radeonScreen->drmSupportsCubeMapsR200) { - ALLOC_STATE( cube[0], tex_cube, CUBE_STATE_SIZE, "CUBE/tex-0", 0 ); - ALLOC_STATE( cube[1], tex_cube, CUBE_STATE_SIZE, "CUBE/tex-1", 1 ); - ALLOC_STATE( cube[2], tex_cube, CUBE_STATE_SIZE, "CUBE/tex-2", 2 ); - ALLOC_STATE( cube[3], tex_cube, CUBE_STATE_SIZE, "CUBE/tex-3", 3 ); - ALLOC_STATE( cube[4], tex_cube, CUBE_STATE_SIZE, "CUBE/tex-4", 4 ); - ALLOC_STATE( cube[5], tex_cube, CUBE_STATE_SIZE, "CUBE/tex-5", 5 ); - for (i = 0; i < 6; i++) - if (rmesa->radeon.radeonScreen->kernel_mm) { - rmesa->hw.cube[i].emit = cube_emit_cs; - rmesa->hw.cube[i].check = check_tex_cube_cs; - } else - rmesa->hw.cube[i].emit = cube_emit; - } - else { - ALLOC_STATE( cube[0], never, CUBE_STATE_SIZE, "CUBE/tex-0", 0 ); - ALLOC_STATE( cube[1], never, CUBE_STATE_SIZE, "CUBE/tex-1", 1 ); - ALLOC_STATE( cube[2], never, CUBE_STATE_SIZE, "CUBE/tex-2", 2 ); - ALLOC_STATE( cube[3], never, CUBE_STATE_SIZE, "CUBE/tex-3", 3 ); - ALLOC_STATE( cube[4], never, CUBE_STATE_SIZE, "CUBE/tex-4", 4 ); - ALLOC_STATE( cube[5], never, CUBE_STATE_SIZE, "CUBE/tex-5", 5 ); + rmesa->hw.tex[i].emit = tex_emit_mm; + ALLOC_STATE( cube[0], tex_cube, CUBE_STATE_SIZE, "CUBE/tex-0", 0 ); + ALLOC_STATE( cube[1], tex_cube, CUBE_STATE_SIZE, "CUBE/tex-1", 1 ); + ALLOC_STATE( cube[2], tex_cube, CUBE_STATE_SIZE, "CUBE/tex-2", 2 ); + ALLOC_STATE( cube[3], tex_cube, CUBE_STATE_SIZE, "CUBE/tex-3", 3 ); + ALLOC_STATE( cube[4], tex_cube, CUBE_STATE_SIZE, "CUBE/tex-4", 4 ); + ALLOC_STATE( cube[5], tex_cube, CUBE_STATE_SIZE, "CUBE/tex-5", 5 ); + for (i = 0; i < 6; i++) { + rmesa->hw.cube[i].emit = cube_emit_cs; + rmesa->hw.cube[i].check = check_tex_cube_cs; } - if (rmesa->radeon.radeonScreen->drmSupportsVertexProgram) { - ALLOC_STATE( pvs, tcl_vp, PVS_STATE_SIZE, "PVS/pvscntl", 0 ); - if (rmesa->radeon.radeonScreen->kernel_mm) { - ALLOC_STATE( vpi[0], tcl_vp_add4, VPI_STATE_SIZE, "VP/vertexprog-0", 0 ); - ALLOC_STATE( vpi[1], tcl_vp_size_add4, VPI_STATE_SIZE, "VP/vertexprog-1", 1 ); - ALLOC_STATE( vpp[0], tcl_vp_add4, VPP_STATE_SIZE, "VPP/vertexparam-0", 0 ); - ALLOC_STATE( vpp[1], tcl_vpp_size_add4, VPP_STATE_SIZE, "VPP/vertexparam-1", 1 ); - } else { - ALLOC_STATE( vpi[0], tcl_vp, VPI_STATE_SIZE, "VP/vertexprog-0", 0 ); - ALLOC_STATE( vpi[1], tcl_vp_size, VPI_STATE_SIZE, "VP/vertexprog-1", 1 ); - ALLOC_STATE( vpp[0], tcl_vp, VPP_STATE_SIZE, "VPP/vertexparam-0", 0 ); - ALLOC_STATE( vpp[1], tcl_vpp_size, VPP_STATE_SIZE, "VPP/vertexparam-1", 1 ); - } - } - else { - ALLOC_STATE( pvs, never, PVS_STATE_SIZE, "PVS/pvscntl", 0 ); - ALLOC_STATE( vpi[0], never, VPI_STATE_SIZE, "VP/vertexprog-0", 0 ); - ALLOC_STATE( vpi[1], never, VPI_STATE_SIZE, "VP/vertexprog-1", 1 ); - ALLOC_STATE( vpp[0], never, VPP_STATE_SIZE, "VPP/vertexparam-0", 0 ); - ALLOC_STATE( vpp[1], never, VPP_STATE_SIZE, "VPP/vertexparam-1", 1 ); - } + ALLOC_STATE( pvs, tcl_vp, PVS_STATE_SIZE, "PVS/pvscntl", 0 ); + ALLOC_STATE( vpi[0], tcl_vp_add4, VPI_STATE_SIZE, "VP/vertexprog-0", 0 ); + ALLOC_STATE( vpi[1], tcl_vp_size_add4, VPI_STATE_SIZE, "VP/vertexprog-1", 1 ); + ALLOC_STATE( vpp[0], tcl_vp_add4, VPP_STATE_SIZE, "VPP/vertexparam-0", 0 ); + ALLOC_STATE( vpp[1], tcl_vpp_size_add4, VPP_STATE_SIZE, "VPP/vertexparam-1", 1 ); + /* FIXME: this atom has two commands, we need only one (ucp_vert_blend) for vp */ ALLOC_STATE( tcl, tcl_or_vp, TCL_STATE_SIZE, "TCL/tcl", 0 ); ALLOC_STATE( msl, tcl, MSL_STATE_SIZE, "MSL/matrix-select", 0 ); ALLOC_STATE( tcg, tcl, TCG_STATE_SIZE, "TCG/texcoordgen", 0 ); - if (rmesa->radeon.radeonScreen->kernel_mm) { - ALLOC_STATE( mtl[0], tcl_lighting_add6, MTL_STATE_SIZE, "MTL0/material0", 0 ); - ALLOC_STATE( mtl[1], tcl_lighting_add6, MTL_STATE_SIZE, "MTL1/material1", 1 ); - ALLOC_STATE( grd, tcl_or_vp_add2, GRD_STATE_SIZE, "GRD/guard-band", 0 ); - ALLOC_STATE( fog, tcl_fog_add4, FOG_STATE_SIZE, "FOG/fog", 0 ); - ALLOC_STATE( glt, tcl_lighting_add4, GLT_STATE_SIZE, "GLT/light-global", 0 ); - ALLOC_STATE( eye, tcl_lighting_add4, EYE_STATE_SIZE, "EYE/eye-vector", 0 ); - ALLOC_STATE( mat[R200_MTX_MV], tcl_add4, MAT_STATE_SIZE, "MAT/modelview", 0 ); - ALLOC_STATE( mat[R200_MTX_IMV], tcl_add4, MAT_STATE_SIZE, "MAT/it-modelview", 0 ); - ALLOC_STATE( mat[R200_MTX_MVP], tcl_add4, MAT_STATE_SIZE, "MAT/modelproject", 0 ); - ALLOC_STATE( mat[R200_MTX_TEX0], tcl_tex_add4, MAT_STATE_SIZE, "MAT/texmat0", 0 ); - ALLOC_STATE( mat[R200_MTX_TEX1], tcl_tex_add4, MAT_STATE_SIZE, "MAT/texmat1", 1 ); - ALLOC_STATE( mat[R200_MTX_TEX2], tcl_tex_add4, MAT_STATE_SIZE, "MAT/texmat2", 2 ); - ALLOC_STATE( mat[R200_MTX_TEX3], tcl_tex_add4, MAT_STATE_SIZE, "MAT/texmat3", 3 ); - ALLOC_STATE( mat[R200_MTX_TEX4], tcl_tex_add4, MAT_STATE_SIZE, "MAT/texmat4", 4 ); - ALLOC_STATE( mat[R200_MTX_TEX5], tcl_tex_add4, MAT_STATE_SIZE, "MAT/texmat5", 5 ); - ALLOC_STATE( ucp[0], tcl_ucp_add4, UCP_STATE_SIZE, "UCP/userclip-0", 0 ); - ALLOC_STATE( ucp[1], tcl_ucp_add4, UCP_STATE_SIZE, "UCP/userclip-1", 1 ); - ALLOC_STATE( ucp[2], tcl_ucp_add4, UCP_STATE_SIZE, "UCP/userclip-2", 2 ); - ALLOC_STATE( ucp[3], tcl_ucp_add4, UCP_STATE_SIZE, "UCP/userclip-3", 3 ); - ALLOC_STATE( ucp[4], tcl_ucp_add4, UCP_STATE_SIZE, "UCP/userclip-4", 4 ); - ALLOC_STATE( ucp[5], tcl_ucp_add4, UCP_STATE_SIZE, "UCP/userclip-5", 5 ); - ALLOC_STATE( lit[0], tcl_light_add8, LIT_STATE_SIZE, "LIT/light-0", 0 ); - ALLOC_STATE( lit[1], tcl_light_add8, LIT_STATE_SIZE, "LIT/light-1", 1 ); - ALLOC_STATE( lit[2], tcl_light_add8, LIT_STATE_SIZE, "LIT/light-2", 2 ); - ALLOC_STATE( lit[3], tcl_light_add8, LIT_STATE_SIZE, "LIT/light-3", 3 ); - ALLOC_STATE( lit[4], tcl_light_add8, LIT_STATE_SIZE, "LIT/light-4", 4 ); - ALLOC_STATE( lit[5], tcl_light_add8, LIT_STATE_SIZE, "LIT/light-5", 5 ); - ALLOC_STATE( lit[6], tcl_light_add8, LIT_STATE_SIZE, "LIT/light-6", 6 ); - ALLOC_STATE( lit[7], tcl_light_add8, LIT_STATE_SIZE, "LIT/light-7", 7 ); - ALLOC_STATE( sci, rrb, SCI_STATE_SIZE, "SCI/scissor", 0 ); - } else { - ALLOC_STATE( mtl[0], tcl_lighting, MTL_STATE_SIZE, "MTL0/material0", 0 ); - ALLOC_STATE( mtl[1], tcl_lighting, MTL_STATE_SIZE, "MTL1/material1", 1 ); - ALLOC_STATE( grd, tcl_or_vp, GRD_STATE_SIZE, "GRD/guard-band", 0 ); - ALLOC_STATE( fog, tcl_fog, FOG_STATE_SIZE, "FOG/fog", 0 ); - ALLOC_STATE( glt, tcl_lighting, GLT_STATE_SIZE, "GLT/light-global", 0 ); - ALLOC_STATE( eye, tcl_lighting, EYE_STATE_SIZE, "EYE/eye-vector", 0 ); - ALLOC_STATE( mat[R200_MTX_MV], tcl, MAT_STATE_SIZE, "MAT/modelview", 0 ); - ALLOC_STATE( mat[R200_MTX_IMV], tcl, MAT_STATE_SIZE, "MAT/it-modelview", 0 ); - ALLOC_STATE( mat[R200_MTX_MVP], tcl, MAT_STATE_SIZE, "MAT/modelproject", 0 ); - ALLOC_STATE( mat[R200_MTX_TEX0], tcl_tex, MAT_STATE_SIZE, "MAT/texmat0", 0 ); - ALLOC_STATE( mat[R200_MTX_TEX1], tcl_tex, MAT_STATE_SIZE, "MAT/texmat1", 1 ); - ALLOC_STATE( mat[R200_MTX_TEX2], tcl_tex, MAT_STATE_SIZE, "MAT/texmat2", 2 ); - ALLOC_STATE( mat[R200_MTX_TEX3], tcl_tex, MAT_STATE_SIZE, "MAT/texmat3", 3 ); - ALLOC_STATE( mat[R200_MTX_TEX4], tcl_tex, MAT_STATE_SIZE, "MAT/texmat4", 4 ); - ALLOC_STATE( mat[R200_MTX_TEX5], tcl_tex, MAT_STATE_SIZE, "MAT/texmat5", 5 ); - ALLOC_STATE( ucp[0], tcl_ucp, UCP_STATE_SIZE, "UCP/userclip-0", 0 ); - ALLOC_STATE( ucp[1], tcl_ucp, UCP_STATE_SIZE, "UCP/userclip-1", 1 ); - ALLOC_STATE( ucp[2], tcl_ucp, UCP_STATE_SIZE, "UCP/userclip-2", 2 ); - ALLOC_STATE( ucp[3], tcl_ucp, UCP_STATE_SIZE, "UCP/userclip-3", 3 ); - ALLOC_STATE( ucp[4], tcl_ucp, UCP_STATE_SIZE, "UCP/userclip-4", 4 ); - ALLOC_STATE( ucp[5], tcl_ucp, UCP_STATE_SIZE, "UCP/userclip-5", 5 ); - ALLOC_STATE( lit[0], tcl_light, LIT_STATE_SIZE, "LIT/light-0", 0 ); - ALLOC_STATE( lit[1], tcl_light, LIT_STATE_SIZE, "LIT/light-1", 1 ); - ALLOC_STATE( lit[2], tcl_light, LIT_STATE_SIZE, "LIT/light-2", 2 ); - ALLOC_STATE( lit[3], tcl_light, LIT_STATE_SIZE, "LIT/light-3", 3 ); - ALLOC_STATE( lit[4], tcl_light, LIT_STATE_SIZE, "LIT/light-4", 4 ); - ALLOC_STATE( lit[5], tcl_light, LIT_STATE_SIZE, "LIT/light-5", 5 ); - ALLOC_STATE( lit[6], tcl_light, LIT_STATE_SIZE, "LIT/light-6", 6 ); - ALLOC_STATE( lit[7], tcl_light, LIT_STATE_SIZE, "LIT/light-7", 7 ); - ALLOC_STATE( sci, never, SCI_STATE_SIZE, "SCI/scissor", 0 ); - } + ALLOC_STATE( mtl[0], tcl_lighting_add6, MTL_STATE_SIZE, "MTL0/material0", 0 ); + ALLOC_STATE( mtl[1], tcl_lighting_add6, MTL_STATE_SIZE, "MTL1/material1", 1 ); + ALLOC_STATE( grd, tcl_or_vp_add2, GRD_STATE_SIZE, "GRD/guard-band", 0 ); + ALLOC_STATE( fog, tcl_fog_add4, FOG_STATE_SIZE, "FOG/fog", 0 ); + ALLOC_STATE( glt, tcl_lighting_add4, GLT_STATE_SIZE, "GLT/light-global", 0 ); + ALLOC_STATE( eye, tcl_lighting_add4, EYE_STATE_SIZE, "EYE/eye-vector", 0 ); + ALLOC_STATE( mat[R200_MTX_MV], tcl_add4, MAT_STATE_SIZE, "MAT/modelview", 0 ); + ALLOC_STATE( mat[R200_MTX_IMV], tcl_add4, MAT_STATE_SIZE, "MAT/it-modelview", 0 ); + ALLOC_STATE( mat[R200_MTX_MVP], tcl_add4, MAT_STATE_SIZE, "MAT/modelproject", 0 ); + ALLOC_STATE( mat[R200_MTX_TEX0], tcl_tex_add4, MAT_STATE_SIZE, "MAT/texmat0", 0 ); + ALLOC_STATE( mat[R200_MTX_TEX1], tcl_tex_add4, MAT_STATE_SIZE, "MAT/texmat1", 1 ); + ALLOC_STATE( mat[R200_MTX_TEX2], tcl_tex_add4, MAT_STATE_SIZE, "MAT/texmat2", 2 ); + ALLOC_STATE( mat[R200_MTX_TEX3], tcl_tex_add4, MAT_STATE_SIZE, "MAT/texmat3", 3 ); + ALLOC_STATE( mat[R200_MTX_TEX4], tcl_tex_add4, MAT_STATE_SIZE, "MAT/texmat4", 4 ); + ALLOC_STATE( mat[R200_MTX_TEX5], tcl_tex_add4, MAT_STATE_SIZE, "MAT/texmat5", 5 ); + ALLOC_STATE( ucp[0], tcl_ucp_add4, UCP_STATE_SIZE, "UCP/userclip-0", 0 ); + ALLOC_STATE( ucp[1], tcl_ucp_add4, UCP_STATE_SIZE, "UCP/userclip-1", 1 ); + ALLOC_STATE( ucp[2], tcl_ucp_add4, UCP_STATE_SIZE, "UCP/userclip-2", 2 ); + ALLOC_STATE( ucp[3], tcl_ucp_add4, UCP_STATE_SIZE, "UCP/userclip-3", 3 ); + ALLOC_STATE( ucp[4], tcl_ucp_add4, UCP_STATE_SIZE, "UCP/userclip-4", 4 ); + ALLOC_STATE( ucp[5], tcl_ucp_add4, UCP_STATE_SIZE, "UCP/userclip-5", 5 ); + ALLOC_STATE( lit[0], tcl_light_add6, LIT_STATE_SIZE, "LIT/light-0", 0 ); + ALLOC_STATE( lit[1], tcl_light_add6, LIT_STATE_SIZE, "LIT/light-1", 1 ); + ALLOC_STATE( lit[2], tcl_light_add6, LIT_STATE_SIZE, "LIT/light-2", 2 ); + ALLOC_STATE( lit[3], tcl_light_add6, LIT_STATE_SIZE, "LIT/light-3", 3 ); + ALLOC_STATE( lit[4], tcl_light_add6, LIT_STATE_SIZE, "LIT/light-4", 4 ); + ALLOC_STATE( lit[5], tcl_light_add6, LIT_STATE_SIZE, "LIT/light-5", 5 ); + ALLOC_STATE( lit[6], tcl_light_add6, LIT_STATE_SIZE, "LIT/light-6", 6 ); + ALLOC_STATE( lit[7], tcl_light_add6, LIT_STATE_SIZE, "LIT/light-7", 7 ); + ALLOC_STATE( sci, rrb, SCI_STATE_SIZE, "SCI/scissor", 0 ); ALLOC_STATE( pix[0], pix_zero, PIX_STATE_SIZE, "PIX/pixstage-0", 0 ); ALLOC_STATE( pix[1], texenv, PIX_STATE_SIZE, "PIX/pixstage-1", 1 ); ALLOC_STATE( pix[2], texenv, PIX_STATE_SIZE, "PIX/pixstage-2", 2 ); ALLOC_STATE( pix[3], texenv, PIX_STATE_SIZE, "PIX/pixstage-3", 3 ); ALLOC_STATE( pix[4], texenv, PIX_STATE_SIZE, "PIX/pixstage-4", 4 ); ALLOC_STATE( pix[5], texenv, PIX_STATE_SIZE, "PIX/pixstage-5", 5 ); - if (rmesa->radeon.radeonScreen->drmSupportsTriPerf) { - ALLOC_STATE( prf, always, PRF_STATE_SIZE, "PRF/performance-tri", 0 ); - } - else { - ALLOC_STATE( prf, never, PRF_STATE_SIZE, "PRF/performance-tri", 0 ); - } - if (rmesa->radeon.radeonScreen->drmSupportsPointSprites) { - ALLOC_STATE( spr, always, SPR_STATE_SIZE, "SPR/pointsprite", 0 ); - if (rmesa->radeon.radeonScreen->kernel_mm) - ALLOC_STATE( ptp, tcl_add8, PTP_STATE_SIZE, "PTP/pointparams", 0 ); - else - ALLOC_STATE( ptp, tcl, PTP_STATE_SIZE, "PTP/pointparams", 0 ); - } - else { - ALLOC_STATE (spr, never, SPR_STATE_SIZE, "SPR/pointsprite", 0 ); - ALLOC_STATE (ptp, never, PTP_STATE_SIZE, "PTP/pointparams", 0 ); - } + ALLOC_STATE( prf, always, PRF_STATE_SIZE, "PRF/performance-tri", 0 ); + ALLOC_STATE( spr, always, SPR_STATE_SIZE, "SPR/pointsprite", 0 ); + ALLOC_STATE( ptp, tcl_add8, PTP_STATE_SIZE, "PTP/pointparams", 0 ); r200SetUpAtomList( rmesa ); @@ -1034,8 +756,7 @@ void r200InitState( r200ContextPtr rmesa ) rmesa->hw.ctx.cmd[CTX_CMD_0] = cmdpkt(rmesa, RADEON_EMIT_PP_MISC); rmesa->hw.ctx.cmd[CTX_CMD_1] = cmdpkt(rmesa, RADEON_EMIT_PP_CNTL); rmesa->hw.ctx.cmd[CTX_CMD_2] = cmdpkt(rmesa, RADEON_EMIT_RB3D_COLORPITCH); - if (rmesa->radeon.radeonScreen->drmSupportsBlendColor) - rmesa->hw.ctx.cmd[CTX_CMD_3] = cmdpkt(rmesa, R200_EMIT_RB3D_BLENDCOLOR); + rmesa->hw.ctx.cmd[CTX_CMD_3] = cmdpkt(rmesa, R200_EMIT_RB3D_BLENDCOLOR); rmesa->hw.lin.cmd[LIN_CMD_0] = cmdpkt(rmesa, RADEON_EMIT_RE_LINE_PATTERN); rmesa->hw.lin.cmd[LIN_CMD_1] = cmdpkt(rmesa, RADEON_EMIT_SE_LINE_WIDTH); rmesa->hw.msk.cmd[MSK_CMD_0] = cmdpkt(rmesa, RADEON_EMIT_RB3D_STENCILREFMASK); @@ -1045,40 +766,24 @@ void r200InitState( r200ContextPtr rmesa ) rmesa->hw.cst.cmd[CST_CMD_0] = cmdpkt(rmesa, R200_EMIT_PP_CNTL_X); rmesa->hw.cst.cmd[CST_CMD_1] = cmdpkt(rmesa, R200_EMIT_RB3D_DEPTHXY_OFFSET); rmesa->hw.cst.cmd[CST_CMD_2] = cmdpkt(rmesa, R200_EMIT_RE_AUX_SCISSOR_CNTL); - rmesa->hw.cst.cmd[CST_CMD_3] = cmdpkt(rmesa, R200_EMIT_RE_SCISSOR_TL_0); rmesa->hw.cst.cmd[CST_CMD_4] = cmdpkt(rmesa, R200_EMIT_SE_VAP_CNTL_STATUS); rmesa->hw.cst.cmd[CST_CMD_5] = cmdpkt(rmesa, R200_EMIT_RE_POINTSIZE); rmesa->hw.cst.cmd[CST_CMD_6] = cmdpkt(rmesa, R200_EMIT_TCL_INPUT_VTX_VECTOR_ADDR_0); rmesa->hw.tam.cmd[TAM_CMD_0] = cmdpkt(rmesa, R200_EMIT_PP_TAM_DEBUG3); rmesa->hw.tf.cmd[TF_CMD_0] = cmdpkt(rmesa, R200_EMIT_TFACTOR_0); - if (rmesa->radeon.radeonScreen->drmSupportsFragShader) { - rmesa->hw.atf.cmd[ATF_CMD_0] = cmdpkt(rmesa, R200_EMIT_ATF_TFACTOR); - rmesa->hw.tex[0].cmd[TEX_CMD_0] = cmdpkt(rmesa, R200_EMIT_PP_TXCTLALL_0); - rmesa->hw.tex[0].cmd[TEX_CMD_1_NEWDRM] = cmdpkt(rmesa, R200_EMIT_PP_TXOFFSET_0); - rmesa->hw.tex[1].cmd[TEX_CMD_0] = cmdpkt(rmesa, R200_EMIT_PP_TXCTLALL_1); - rmesa->hw.tex[1].cmd[TEX_CMD_1_NEWDRM] = cmdpkt(rmesa, R200_EMIT_PP_TXOFFSET_1); - rmesa->hw.tex[2].cmd[TEX_CMD_0] = cmdpkt(rmesa, R200_EMIT_PP_TXCTLALL_2); - rmesa->hw.tex[2].cmd[TEX_CMD_1_NEWDRM] = cmdpkt(rmesa, R200_EMIT_PP_TXOFFSET_2); - rmesa->hw.tex[3].cmd[TEX_CMD_0] = cmdpkt(rmesa, R200_EMIT_PP_TXCTLALL_3); - rmesa->hw.tex[3].cmd[TEX_CMD_1_NEWDRM] = cmdpkt(rmesa, R200_EMIT_PP_TXOFFSET_3); - rmesa->hw.tex[4].cmd[TEX_CMD_0] = cmdpkt(rmesa, R200_EMIT_PP_TXCTLALL_4); - rmesa->hw.tex[4].cmd[TEX_CMD_1_NEWDRM] = cmdpkt(rmesa, R200_EMIT_PP_TXOFFSET_4); - rmesa->hw.tex[5].cmd[TEX_CMD_0] = cmdpkt(rmesa, R200_EMIT_PP_TXCTLALL_5); - rmesa->hw.tex[5].cmd[TEX_CMD_1_NEWDRM] = cmdpkt(rmesa, R200_EMIT_PP_TXOFFSET_5); - } else { - rmesa->hw.tex[0].cmd[TEX_CMD_0] = cmdpkt(rmesa, R200_EMIT_PP_TXFILTER_0); - rmesa->hw.tex[0].cmd[TEX_CMD_1_OLDDRM] = cmdpkt(rmesa, R200_EMIT_PP_TXOFFSET_0); - rmesa->hw.tex[1].cmd[TEX_CMD_0] = cmdpkt(rmesa, R200_EMIT_PP_TXFILTER_1); - rmesa->hw.tex[1].cmd[TEX_CMD_1_OLDDRM] = cmdpkt(rmesa, R200_EMIT_PP_TXOFFSET_1); - rmesa->hw.tex[2].cmd[TEX_CMD_0] = cmdpkt(rmesa, R200_EMIT_PP_TXFILTER_2); - rmesa->hw.tex[2].cmd[TEX_CMD_1_OLDDRM] = cmdpkt(rmesa, R200_EMIT_PP_TXOFFSET_2); - rmesa->hw.tex[3].cmd[TEX_CMD_0] = cmdpkt(rmesa, R200_EMIT_PP_TXFILTER_3); - rmesa->hw.tex[3].cmd[TEX_CMD_1_OLDDRM] = cmdpkt(rmesa, R200_EMIT_PP_TXOFFSET_3); - rmesa->hw.tex[4].cmd[TEX_CMD_0] = cmdpkt(rmesa, R200_EMIT_PP_TXFILTER_4); - rmesa->hw.tex[4].cmd[TEX_CMD_1_OLDDRM] = cmdpkt(rmesa, R200_EMIT_PP_TXOFFSET_4); - rmesa->hw.tex[5].cmd[TEX_CMD_0] = cmdpkt(rmesa, R200_EMIT_PP_TXFILTER_5); - rmesa->hw.tex[5].cmd[TEX_CMD_1_OLDDRM] = cmdpkt(rmesa, R200_EMIT_PP_TXOFFSET_5); - } + rmesa->hw.atf.cmd[ATF_CMD_0] = cmdpkt(rmesa, R200_EMIT_ATF_TFACTOR); + rmesa->hw.tex[0].cmd[TEX_CMD_0] = cmdpkt(rmesa, R200_EMIT_PP_TXCTLALL_0); + rmesa->hw.tex[0].cmd[TEX_CMD_1_NEWDRM] = cmdpkt(rmesa, R200_EMIT_PP_TXOFFSET_0); + rmesa->hw.tex[1].cmd[TEX_CMD_0] = cmdpkt(rmesa, R200_EMIT_PP_TXCTLALL_1); + rmesa->hw.tex[1].cmd[TEX_CMD_1_NEWDRM] = cmdpkt(rmesa, R200_EMIT_PP_TXOFFSET_1); + rmesa->hw.tex[2].cmd[TEX_CMD_0] = cmdpkt(rmesa, R200_EMIT_PP_TXCTLALL_2); + rmesa->hw.tex[2].cmd[TEX_CMD_1_NEWDRM] = cmdpkt(rmesa, R200_EMIT_PP_TXOFFSET_2); + rmesa->hw.tex[3].cmd[TEX_CMD_0] = cmdpkt(rmesa, R200_EMIT_PP_TXCTLALL_3); + rmesa->hw.tex[3].cmd[TEX_CMD_1_NEWDRM] = cmdpkt(rmesa, R200_EMIT_PP_TXOFFSET_3); + rmesa->hw.tex[4].cmd[TEX_CMD_0] = cmdpkt(rmesa, R200_EMIT_PP_TXCTLALL_4); + rmesa->hw.tex[4].cmd[TEX_CMD_1_NEWDRM] = cmdpkt(rmesa, R200_EMIT_PP_TXOFFSET_4); + rmesa->hw.tex[5].cmd[TEX_CMD_0] = cmdpkt(rmesa, R200_EMIT_PP_TXCTLALL_5); + rmesa->hw.tex[5].cmd[TEX_CMD_1_NEWDRM] = cmdpkt(rmesa, R200_EMIT_PP_TXOFFSET_5); rmesa->hw.afs[0].cmd[AFS_CMD_0] = cmdpkt(rmesa, R200_EMIT_PP_AFS_0); rmesa->hw.afs[1].cmd[AFS_CMD_0] = cmdpkt(rmesa, R200_EMIT_PP_AFS_1); rmesa->hw.pvs.cmd[PVS_CMD_0] = cmdpkt(rmesa, R200_EMIT_VAP_PVS_CNTL); @@ -1113,7 +818,6 @@ void r200InitState( r200ContextPtr rmesa ) rmesa->hw.prf.cmd[PRF_CMD_0] = cmdpkt(rmesa, R200_EMIT_PP_TRI_PERF_CNTL); rmesa->hw.spr.cmd[SPR_CMD_0] = cmdpkt(rmesa, R200_EMIT_TCL_POINT_SPRITE_CNTL); - rmesa->hw.sci.cmd[SCI_CMD_0] = CP_PACKET0(R200_RE_AUX_SCISSOR_CNTL, 0); rmesa->hw.sci.cmd[SCI_CMD_1] = CP_PACKET0(R200_RE_TOP_LEFT, 0); rmesa->hw.sci.cmd[SCI_CMD_2] = CP_PACKET0(R200_RE_WIDTH_HEIGHT, 0); @@ -1121,34 +825,30 @@ void r200InitState( r200ContextPtr rmesa ) rmesa->hw.stp.cmd[STP_DATA_0] = 0; rmesa->hw.stp.cmd[STP_CMD_1] = CP_PACKET0_ONE(RADEON_RE_STIPPLE_DATA, 31); - if (rmesa->radeon.radeonScreen->kernel_mm) { - rmesa->hw.mtl[0].emit = mtl_emit; - rmesa->hw.mtl[1].emit = mtl_emit; + rmesa->hw.mtl[0].emit = mtl_emit; + rmesa->hw.mtl[1].emit = mtl_emit; - rmesa->hw.vpi[0].emit = veclinear_emit; - rmesa->hw.vpi[1].emit = veclinear_emit; - rmesa->hw.vpp[0].emit = veclinear_emit; - rmesa->hw.vpp[1].emit = veclinear_emit; + rmesa->hw.vpi[0].emit = veclinear_emit; + rmesa->hw.vpi[1].emit = veclinear_emit; + rmesa->hw.vpp[0].emit = veclinear_emit; + rmesa->hw.vpp[1].emit = veclinear_emit; - rmesa->hw.grd.emit = scl_emit; - rmesa->hw.fog.emit = vec_emit; - rmesa->hw.glt.emit = vec_emit; - rmesa->hw.eye.emit = vec_emit; + rmesa->hw.grd.emit = scl_emit; + rmesa->hw.fog.emit = vec_emit; + rmesa->hw.glt.emit = vec_emit; + rmesa->hw.eye.emit = vec_emit; - for (i = R200_MTX_MV; i <= R200_MTX_TEX5; i++) - rmesa->hw.mat[i].emit = vec_emit; + for (i = R200_MTX_MV; i <= R200_MTX_TEX5; i++) + rmesa->hw.mat[i].emit = vec_emit; - for (i = 0; i < 8; i++) - rmesa->hw.lit[i].emit = lit_emit; + for (i = 0; i < 8; i++) + rmesa->hw.lit[i].emit = lit_emit; - for (i = 0; i < 6; i++) - rmesa->hw.ucp[i].emit = vec_emit; - - rmesa->hw.ptp.emit = ptp_emit; - } + for (i = 0; i < 6; i++) + rmesa->hw.ucp[i].emit = vec_emit; + rmesa->hw.ptp.emit = ptp_emit; - rmesa->hw.mtl[0].cmd[MTL_CMD_0] = cmdvec( R200_VS_MAT_0_EMISS, 1, 16 ); rmesa->hw.mtl[0].cmd[MTL_CMD_1] = @@ -1226,15 +926,13 @@ void r200InitState( r200ContextPtr rmesa ) (R200_BLEND_GL_ONE << R200_SRC_BLEND_SHIFT) | (R200_BLEND_GL_ZERO << R200_DST_BLEND_SHIFT)); - if (rmesa->radeon.radeonScreen->drmSupportsBlendColor) { - rmesa->hw.ctx.cmd[CTX_RB3D_BLENDCOLOR] = 0x00000000; - rmesa->hw.ctx.cmd[CTX_RB3D_ABLENDCNTL] = (R200_COMB_FCN_ADD_CLAMP | + rmesa->hw.ctx.cmd[CTX_RB3D_BLENDCOLOR] = 0x00000000; + rmesa->hw.ctx.cmd[CTX_RB3D_ABLENDCNTL] = (R200_COMB_FCN_ADD_CLAMP | (R200_BLEND_GL_ONE << R200_SRC_BLEND_SHIFT) | (R200_BLEND_GL_ZERO << R200_DST_BLEND_SHIFT)); - rmesa->hw.ctx.cmd[CTX_RB3D_CBLENDCNTL] = (R200_COMB_FCN_ADD_CLAMP | + rmesa->hw.ctx.cmd[CTX_RB3D_CBLENDCNTL] = (R200_COMB_FCN_ADD_CLAMP | (R200_BLEND_GL_ONE << R200_SRC_BLEND_SHIFT) | (R200_BLEND_GL_ZERO << R200_DST_BLEND_SHIFT)); - } rmesa->hw.ctx.cmd[CTX_RB3D_DEPTHOFFSET] = rmesa->radeon.radeonScreen->depthOffset + rmesa->radeon.radeonScreen->fbLocation; @@ -1330,8 +1028,6 @@ void r200InitState( r200ContextPtr rmesa ) rmesa->hw.cst.cmd[CST_PP_CNTL_X] = 0; rmesa->hw.cst.cmd[CST_RB3D_DEPTHXY_OFFSET] = 0; rmesa->hw.cst.cmd[CST_RE_AUX_SCISSOR_CNTL] = 0x0; - rmesa->hw.cst.cmd[CST_RE_SCISSOR_TL_0] = 0; - rmesa->hw.cst.cmd[CST_RE_SCISSOR_BR_0] = 0; rmesa->hw.cst.cmd[CST_SE_VAP_CNTL_STATUS] = #ifdef MESA_BIG_ENDIAN R200_VC_32BIT_SWAP; @@ -1377,17 +1073,11 @@ void r200InitState( r200ContextPtr rmesa ) rmesa->hw.tex[i].cmd[TEX_PP_BORDER_COLOR] = 0; rmesa->hw.tex[i].cmd[TEX_PP_TXFORMAT_X] = (/* R200_TEXCOORD_PROJ | */ - 0x100000); /* Small default bias */ - if (rmesa->radeon.radeonScreen->drmSupportsFragShader) { - rmesa->hw.tex[i].cmd[TEX_PP_TXOFFSET_NEWDRM] = - rmesa->radeon.radeonScreen->texOffset[RADEON_LOCAL_TEX_HEAP]; - rmesa->hw.tex[i].cmd[TEX_PP_CUBIC_FACES] = 0; - rmesa->hw.tex[i].cmd[TEX_PP_TXMULTI_CTL] = 0; - } - else { - rmesa->hw.tex[i].cmd[TEX_PP_TXOFFSET_OLDDRM] = + R200_LOD_BIAS_CORRECTION); /* Small default bias */ + rmesa->hw.tex[i].cmd[TEX_PP_TXOFFSET_NEWDRM] = rmesa->radeon.radeonScreen->texOffset[RADEON_LOCAL_TEX_HEAP]; - } + rmesa->hw.tex[i].cmd[TEX_PP_CUBIC_FACES] = 0; + rmesa->hw.tex[i].cmd[TEX_PP_TXMULTI_CTL] = 0; rmesa->hw.cube[i].cmd[CUBE_PP_CUBIC_FACES] = 0; rmesa->hw.cube[i].cmd[CUBE_PP_CUBIC_OFFSET_F1] = @@ -1602,11 +1292,9 @@ void r200InitState( r200ContextPtr rmesa ) r200LightingSpaceChange( ctx ); - if (rmesa->radeon.radeonScreen->kernel_mm) { - radeon_init_query_stateobj(&rmesa->radeon, R200_QUERYOBJ_CMDSIZE); - rmesa->radeon.query.queryobj.cmd[R200_QUERYOBJ_CMD_0] = CP_PACKET0(RADEON_RB3D_ZPASS_DATA, 0); - rmesa->radeon.query.queryobj.cmd[R200_QUERYOBJ_DATA_0] = 0; - } + radeon_init_query_stateobj(&rmesa->radeon, R200_QUERYOBJ_CMDSIZE); + rmesa->radeon.query.queryobj.cmd[R200_QUERYOBJ_CMD_0] = CP_PACKET0(RADEON_RB3D_ZPASS_DATA, 0); + rmesa->radeon.query.queryobj.cmd[R200_QUERYOBJ_DATA_0] = 0; rmesa->radeon.hw.all_dirty = GL_TRUE;