X-Git-Url: https://git.libre-soc.org/?a=blobdiff_plain;f=src%2Fmesa%2Fdrivers%2Fdri%2Fr200%2Fr200_state_init.c;h=f6afb90d595cb01709c5222f8dbbec4338155401;hb=f9995b30756140724f41daf963fa06167912be7f;hp=e53fd72290c88c02584e3cc832c8a36e048e7a99;hpb=650e02003fbb5511ec758d993b7ec0a302ee2235;p=mesa.git

diff --git a/src/mesa/drivers/dri/r200/r200_state_init.c b/src/mesa/drivers/dri/r200/r200_state_init.c
index e53fd72290c..f6afb90d595 100644
--- a/src/mesa/drivers/dri/r200/r200_state_init.c
+++ b/src/mesa/drivers/dri/r200/r200_state_init.c
@@ -39,7 +39,6 @@ WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
 
 #include "swrast/swrast.h"
 #include "vbo/vbo.h"
-#include "tnl/tnl.h"
 #include "tnl/t_pipeline.h"
 #include "swrast_setup/swrast_setup.h"
 
@@ -48,9 +47,6 @@ WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
 #include "r200_context.h"
 #include "r200_ioctl.h"
 #include "r200_state.h"
-#include "r200_tcl.h"
-#include "r200_tex.h"
-#include "r200_swtcl.h"
 #include "radeon_queryobj.h"
 
 #include "xmlpool.h"
@@ -232,7 +228,7 @@ static int cmdscl2( int offset, int stride, int count )
  * If it is active check function returns maximum emit size.
  */
 #define CHECK( NM, FLAG, ADD )				\
-static int check_##NM( GLcontext *ctx, struct radeon_state_atom *atom) \
+static int check_##NM( struct gl_context *ctx, struct radeon_state_atom *atom) \
 {							\
    r200ContextPtr rmesa = R200_CONTEXT(ctx);		\
    (void) rmesa;					\
@@ -240,21 +236,21 @@ static int check_##NM( GLcontext *ctx, struct radeon_state_atom *atom) \
 }
 
 #define TCL_CHECK( NM, FLAG, ADD )				\
-static int check_##NM( GLcontext *ctx, struct radeon_state_atom *atom) \
+static int check_##NM( struct gl_context *ctx, struct radeon_state_atom *atom) \
 {									\
    r200ContextPtr rmesa = R200_CONTEXT(ctx);				\
    return (!rmesa->radeon.TclFallback && !ctx->VertexProgram._Enabled && (FLAG)) ? atom->cmd_size + (ADD) : 0; \
 }
 
 #define TCL_OR_VP_CHECK( NM, FLAG, ADD )			\
-static int check_##NM( GLcontext *ctx, struct radeon_state_atom *atom ) \
+static int check_##NM( struct gl_context *ctx, struct radeon_state_atom *atom ) \
 {							\
    r200ContextPtr rmesa = R200_CONTEXT(ctx);		\
    return (!rmesa->radeon.TclFallback && (FLAG)) ? atom->cmd_size + (ADD) : 0;	\
 }
 
 #define VP_CHECK( NM, FLAG, ADD )				\
-static int check_##NM( GLcontext *ctx, struct radeon_state_atom *atom ) \
+static int check_##NM( struct gl_context *ctx, struct radeon_state_atom *atom ) \
 {									\
    r200ContextPtr rmesa = R200_CONTEXT(ctx);				\
    (void) atom;								\
@@ -341,7 +337,7 @@ VP_CHECK( tcl_vpp_size_add4, ctx->VertexProgram.Current->Base.NumNativeParameter
     OUT_BATCH(CP_PACKET0_ONE(R200_SE_TCL_SCALAR_DATA_REG, h.scalars.count - 1));	\
     OUT_BATCH_TABLE((data), h.scalars.count);				\
   } while(0)
-static int check_rrb(GLcontext *ctx, struct radeon_state_atom *atom)
+static int check_rrb(struct gl_context *ctx, struct radeon_state_atom *atom)
 {
    r200ContextPtr r200 = R200_CONTEXT(ctx);
    struct radeon_renderbuffer *rrb;
@@ -351,7 +347,16 @@ static int check_rrb(GLcontext *ctx, struct radeon_state_atom *atom)
    return atom->cmd_size;
 }
 
-static void mtl_emit(GLcontext *ctx, struct radeon_state_atom *atom)
+static int check_polygon_stipple(struct gl_context *ctx,
+		struct radeon_state_atom *atom)
+{
+   r200ContextPtr r200 = R200_CONTEXT(ctx);
+   if (r200->hw.set.cmd[SET_RE_CNTL] & R200_STIPPLE_ENABLE)
+	   return atom->cmd_size;
+   return 0;
+}
+
+static void mtl_emit(struct gl_context *ctx, struct radeon_state_atom *atom)
 {
    r200ContextPtr r200 = R200_CONTEXT(ctx);
    BATCH_LOCALS(&r200->radeon);
@@ -363,7 +368,7 @@ static void mtl_emit(GLcontext *ctx, struct radeon_state_atom *atom)
    END_BATCH();
 }
 
-static void lit_emit(GLcontext *ctx, struct radeon_state_atom *atom)
+static void lit_emit(struct gl_context *ctx, struct radeon_state_atom *atom)
 {
    r200ContextPtr r200 = R200_CONTEXT(ctx);
    BATCH_LOCALS(&r200->radeon);
@@ -375,7 +380,7 @@ static void lit_emit(GLcontext *ctx, struct radeon_state_atom *atom)
    END_BATCH();
 }
 
-static void ptp_emit(GLcontext *ctx, struct radeon_state_atom *atom)
+static void ptp_emit(struct gl_context *ctx, struct radeon_state_atom *atom)
 {
    r200ContextPtr r200 = R200_CONTEXT(ctx);
    BATCH_LOCALS(&r200->radeon);
@@ -387,7 +392,7 @@ static void ptp_emit(GLcontext *ctx, struct radeon_state_atom *atom)
    END_BATCH();
 }
 
-static void veclinear_emit(GLcontext *ctx, struct radeon_state_atom *atom)
+static void veclinear_emit(struct gl_context *ctx, struct radeon_state_atom *atom)
 {
    r200ContextPtr r200 = R200_CONTEXT(ctx);
    BATCH_LOCALS(&r200->radeon);
@@ -396,7 +401,7 @@ static void veclinear_emit(GLcontext *ctx, struct radeon_state_atom *atom)
    OUT_VECLINEAR(atom->cmd[0], atom->cmd+1);
 }
 
-static void scl_emit(GLcontext *ctx, struct radeon_state_atom *atom)
+static void scl_emit(struct gl_context *ctx, struct radeon_state_atom *atom)
 {
    r200ContextPtr r200 = R200_CONTEXT(ctx);
    BATCH_LOCALS(&r200->radeon);
@@ -408,7 +413,7 @@ static void scl_emit(GLcontext *ctx, struct radeon_state_atom *atom)
 }
 
 
-static void vec_emit(GLcontext *ctx, struct radeon_state_atom *atom)
+static void vec_emit(struct gl_context *ctx, struct radeon_state_atom *atom)
 {
    r200ContextPtr r200 = R200_CONTEXT(ctx);
    BATCH_LOCALS(&r200->radeon);
@@ -419,7 +424,7 @@ static void vec_emit(GLcontext *ctx, struct radeon_state_atom *atom)
    END_BATCH();
 }
 
-static void ctx_emit(GLcontext *ctx, struct radeon_state_atom *atom)
+static void ctx_emit(struct gl_context *ctx, struct radeon_state_atom *atom)
 {
    r200ContextPtr r200 = R200_CONTEXT(ctx);
    BATCH_LOCALS(&r200->radeon);
@@ -486,7 +491,7 @@ static void ctx_emit(GLcontext *ctx, struct radeon_state_atom *atom)
    END_BATCH();
 }
 
-static int check_always_ctx( GLcontext *ctx, struct radeon_state_atom *atom)
+static int check_always_ctx( struct gl_context *ctx, struct radeon_state_atom *atom)
 {
    r200ContextPtr r200 = R200_CONTEXT(ctx);
    struct radeon_renderbuffer *rrb, *drb;
@@ -511,7 +516,7 @@ static int check_always_ctx( GLcontext *ctx, struct radeon_state_atom *atom)
    return dwords;
 }
 
-static void ctx_emit_cs(GLcontext *ctx, struct radeon_state_atom *atom)
+static void ctx_emit_cs(struct gl_context *ctx, struct radeon_state_atom *atom)
 {
    r200ContextPtr r200 = R200_CONTEXT(ctx);
    BATCH_LOCALS(&r200->radeon);
@@ -595,7 +600,7 @@ static void ctx_emit_cs(GLcontext *ctx, struct radeon_state_atom *atom)
    END_BATCH();
 }
 
-static int get_tex_size(GLcontext* ctx, struct radeon_state_atom *atom)
+static int get_tex_size(struct gl_context* ctx, struct radeon_state_atom *atom)
 {
    r200ContextPtr r200 = R200_CONTEXT(ctx);
    uint32_t dwords = atom->cmd_size + 2;
@@ -607,7 +612,7 @@ static int get_tex_size(GLcontext* ctx, struct radeon_state_atom *atom)
    return dwords;
 }
 
-static int check_tex_pair(GLcontext* ctx, struct radeon_state_atom *atom)
+static int check_tex_pair(struct gl_context* ctx, struct radeon_state_atom *atom)
 {
    r200ContextPtr r200 = R200_CONTEXT(ctx);
    /** XOR is bit flip operation so use it for finding pair */
@@ -617,7 +622,7 @@ static int check_tex_pair(GLcontext* ctx, struct radeon_state_atom *atom)
    return get_tex_size(ctx, atom);
 }
 
-static int check_tex(GLcontext* ctx, struct radeon_state_atom *atom)
+static int check_tex(struct gl_context* ctx, struct radeon_state_atom *atom)
 {
    r200ContextPtr r200 = R200_CONTEXT(ctx);
    if (!(r200->state.texture.unit[atom->idx].unitneeded))
@@ -627,7 +632,7 @@ static int check_tex(GLcontext* ctx, struct radeon_state_atom *atom)
 }
 
 
-static void tex_emit(GLcontext *ctx, struct radeon_state_atom *atom)
+static void tex_emit(struct gl_context *ctx, struct radeon_state_atom *atom)
 {
    r200ContextPtr r200 = R200_CONTEXT(ctx);
    BATCH_LOCALS(&r200->radeon);
@@ -652,7 +657,7 @@ static void tex_emit(GLcontext *ctx, struct radeon_state_atom *atom)
    END_BATCH();
 }
 
-static int get_tex_mm_size(GLcontext* ctx, struct radeon_state_atom *atom)
+static int get_tex_mm_size(struct gl_context* ctx, struct radeon_state_atom *atom)
 {
    r200ContextPtr r200 = R200_CONTEXT(ctx);
    uint32_t dwords = atom->cmd_size + 2;
@@ -671,7 +676,7 @@ static int get_tex_mm_size(GLcontext* ctx, struct radeon_state_atom *atom)
    return dwords;
 }
 
-static int check_tex_pair_mm(GLcontext* ctx, struct radeon_state_atom *atom)
+static int check_tex_pair_mm(struct gl_context* ctx, struct radeon_state_atom *atom)
 {
    r200ContextPtr r200 = R200_CONTEXT(ctx);
    /** XOR is bit flip operation so use it for finding pair */
@@ -681,7 +686,7 @@ static int check_tex_pair_mm(GLcontext* ctx, struct radeon_state_atom *atom)
    return get_tex_mm_size(ctx, atom);
 }
 
-static int check_tex_mm(GLcontext* ctx, struct radeon_state_atom *atom)
+static int check_tex_mm(struct gl_context* ctx, struct radeon_state_atom *atom)
 {
    r200ContextPtr r200 = R200_CONTEXT(ctx);
    if (!(r200->state.texture.unit[atom->idx].unitneeded))
@@ -691,14 +696,15 @@ static int check_tex_mm(GLcontext* ctx, struct radeon_state_atom *atom)
 }
 
 
-static void tex_emit_mm(GLcontext *ctx, struct radeon_state_atom *atom)
+static void tex_emit_mm(struct gl_context *ctx, struct radeon_state_atom *atom)
 {
    r200ContextPtr r200 = R200_CONTEXT(ctx);
    BATCH_LOCALS(&r200->radeon);
    uint32_t dwords = atom->check(ctx, atom);
    int i = atom->idx;
    radeonTexObj *t = r200->state.texture.unit[i].texobj;
-   if (!r200->state.texture.unit[i].unitneeded)
+
+   if (!r200->state.texture.unit[i].unitneeded && !(dwords <= atom->cmd_size))
         dwords -= 4;
    BEGIN_BATCH_NO_AUTOSTATE(dwords);
 
@@ -720,7 +726,7 @@ static void tex_emit_mm(GLcontext *ctx, struct radeon_state_atom *atom)
 }
 
 
-static void cube_emit(GLcontext *ctx, struct radeon_state_atom *atom)
+static void cube_emit(struct gl_context *ctx, struct radeon_state_atom *atom)
 {
    r200ContextPtr r200 = R200_CONTEXT(ctx);
    BATCH_LOCALS(&r200->radeon);
@@ -747,7 +753,7 @@ static void cube_emit(GLcontext *ctx, struct radeon_state_atom *atom)
    END_BATCH();
 }
 
-static void cube_emit_cs(GLcontext *ctx, struct radeon_state_atom *atom)
+static void cube_emit_cs(struct gl_context *ctx, struct radeon_state_atom *atom)
 {
    r200ContextPtr r200 = R200_CONTEXT(ctx);
    BATCH_LOCALS(&r200->radeon);
@@ -776,7 +782,7 @@ static void cube_emit_cs(GLcontext *ctx, struct radeon_state_atom *atom)
  */
 void r200InitState( r200ContextPtr rmesa )
 {
-   GLcontext *ctx = rmesa->radeon.glCtx;
+   struct gl_context *ctx = rmesa->radeon.glCtx;
    GLuint i;
 
    rmesa->radeon.state.color.clear = 0x00000000;
@@ -887,10 +893,11 @@ void r200InitState( r200ContextPtr rmesa )
          }
       }
    }
-   /* polygon stipple is done with irq for non-kms */
-   if (rmesa->radeon.radeonScreen->kernel_mm) {
-       ALLOC_STATE( stp, always, STP_STATE_SIZE, "STP/stp", 0 );
-   }
+
+   if (rmesa->radeon.radeonScreen->kernel_mm)
+	   ALLOC_STATE( stp, polygon_stipple, STP_STATE_SIZE, "STP/stp", 0 );
+   else
+	   ALLOC_STATE( stp, never, STP_STATE_SIZE, "STP/stp", 0 );
 
    for (i = 0; i < 6; i++)
       if (rmesa->radeon.radeonScreen->kernel_mm)
@@ -1122,12 +1129,11 @@ void r200InitState( r200ContextPtr rmesa )
    rmesa->hw.sci.cmd[SCI_CMD_1] = CP_PACKET0(R200_RE_TOP_LEFT, 0);
    rmesa->hw.sci.cmd[SCI_CMD_2] = CP_PACKET0(R200_RE_WIDTH_HEIGHT, 0);
 
-   if (rmesa->radeon.radeonScreen->kernel_mm) {
-
-	rmesa->hw.stp.cmd[STP_CMD_0] = CP_PACKET0(RADEON_RE_STIPPLE_ADDR, 0);
-	rmesa->hw.stp.cmd[STP_DATA_0] = 0;
-	rmesa->hw.stp.cmd[STP_CMD_1] = CP_PACKET0_ONE(RADEON_RE_STIPPLE_DATA, 31);
+   rmesa->hw.stp.cmd[STP_CMD_0] = CP_PACKET0(RADEON_RE_STIPPLE_ADDR, 0);
+   rmesa->hw.stp.cmd[STP_DATA_0] = 0;
+   rmesa->hw.stp.cmd[STP_CMD_1] = CP_PACKET0_ONE(RADEON_RE_STIPPLE_DATA, 31);
 
+   if (rmesa->radeon.radeonScreen->kernel_mm) {
         rmesa->hw.mtl[0].emit = mtl_emit;
         rmesa->hw.mtl[1].emit = mtl_emit;
 
@@ -1383,7 +1389,7 @@ void r200InitState( r200ContextPtr rmesa )
       rmesa->hw.tex[i].cmd[TEX_PP_BORDER_COLOR] = 0;
       rmesa->hw.tex[i].cmd[TEX_PP_TXFORMAT_X] =
          (/* R200_TEXCOORD_PROJ | */
-          0x100000);	/* Small default bias */
+          R200_LOD_BIAS_CORRECTION);	/* Small default bias */
       if (rmesa->radeon.radeonScreen->drmSupportsFragShader) {
 	 rmesa->hw.tex[i].cmd[TEX_PP_TXOFFSET_NEWDRM] =
 	     rmesa->radeon.radeonScreen->texOffset[RADEON_LOCAL_TEX_HEAP];