X-Git-Url: https://git.libre-soc.org/?a=blobdiff_plain;f=src%2Fmesa%2Fdrivers%2Fdri%2Fr300%2Fr300_blit.c;h=9fd8e8fde5fbd6ce4088012a5017b4ed9d2f54da;hb=f9995b30756140724f41daf963fa06167912be7f;hp=54ac2510e7a1f5419e22c4ed772c7ac90dfab5fb;hpb=653a83445f94620673f747a4ace6847a2c7fdb4d;p=mesa.git diff --git a/src/mesa/drivers/dri/r300/r300_blit.c b/src/mesa/drivers/dri/r300/r300_blit.c index 54ac2510e7a..9fd8e8fde5f 100644 --- a/src/mesa/drivers/dri/r300/r300_blit.c +++ b/src/mesa/drivers/dri/r300/r300_blit.c @@ -56,6 +56,7 @@ static void create_vertex_program(struct r300_context *r300) struct r300_vertex_program_compiler compiler; struct rc_instruction *inst; + memset(&compiler, 0, sizeof(compiler)); rc_init(&compiler.Base); inst = rc_insert_new_instruction(&compiler.Base, compiler.Base.Program.Instructions.Prev); @@ -88,6 +89,12 @@ static void create_vertex_program(struct r300_context *r300) compiler.RequiredOutputs = compiler.Base.Program.OutputsWritten = (1 << VERT_RESULT_HPOS) | (1 << VERT_RESULT_TEX0); compiler.SetHwInputOutput = vp_ins_outs; compiler.code = &r300->blit.vp_code; + compiler.Base.is_r500 = r300->radeon.radeonScreen->chip_family >= CHIP_FAMILY_RV515; + compiler.Base.disable_optimizations = 0; + compiler.Base.has_half_swizzles = 0; + compiler.Base.max_temp_regs = 32; + compiler.Base.max_constants = 256; + compiler.Base.max_alu_insts = compiler.Base.is_r500 ? 1024 : 256; r3xx_compile_vertex_program(&compiler); } @@ -97,6 +104,7 @@ static void create_fragment_program(struct r300_context *r300) struct r300_fragment_program_compiler compiler; struct rc_instruction *inst; + memset(&compiler, 0, sizeof(struct r300_fragment_program_compiler)); rc_init(&compiler.Base); inst = rc_insert_new_instruction(&compiler.Base, compiler.Base.Program.Instructions.Prev); @@ -116,7 +124,13 @@ static void create_fragment_program(struct r300_context *r300) compiler.Base.Program.InputsRead = (1 << FRAG_ATTRIB_TEX0); compiler.OutputColor[0] = FRAG_RESULT_COLOR; compiler.OutputDepth = FRAG_RESULT_DEPTH; - compiler.is_r500 = (r300->radeon.radeonScreen->chip_family >= CHIP_FAMILY_RV515); + compiler.enable_shadow_ambient = GL_TRUE; + compiler.Base.is_r500 = (r300->radeon.radeonScreen->chip_family >= CHIP_FAMILY_RV515); + compiler.Base.disable_optimizations = 0; + compiler.Base.has_half_swizzles = 1; + compiler.Base.max_temp_regs = (compiler.Base.is_r500) ? 128 : 32; + compiler.Base.max_constants = compiler.Base.is_r500 ? 256 : 32; + compiler.Base.max_alu_insts = compiler.Base.is_r500 ? 512 : 64; compiler.code = &r300->blit.fp_code; compiler.AllocateHwInputs = fp_allocate_hw_inputs; @@ -125,7 +139,8 @@ static void create_fragment_program(struct r300_context *r300) void r300_blit_init(struct r300_context *r300) { - create_vertex_program(r300); + if (r300->options.hw_tcl_enabled) + create_vertex_program(r300); create_fragment_program(r300); } @@ -137,10 +152,11 @@ static void r300_emit_tx_setup(struct r300_context *r300, unsigned height, unsigned pitch) { + int is_r500 = r300->radeon.radeonScreen->chip_family >= CHIP_FAMILY_RV515; BATCH_LOCALS(&r300->radeon); - assert(width <= 2048); - assert(height <= 2048); + assert(is_r500 ? width <= 4096 : width <= 2048); + assert(is_r500 ? height <= 4096 : height <= 2048); assert(r300TranslateTexFormat(mesa_format) >= 0); assert(offset % 32 == 0); @@ -155,14 +171,17 @@ static void r300_emit_tx_setup(struct r300_context *r300, (0 << 28)); OUT_BATCH_REGVAL(R300_TX_FILTER1_0, 0); OUT_BATCH_REGVAL(R300_TX_SIZE_0, - ((width-1) << R300_TX_WIDTHMASK_SHIFT) | - ((height-1) << R300_TX_HEIGHTMASK_SHIFT) | + (((width - 1) & 0x7ff) << R300_TX_WIDTHMASK_SHIFT) | + (((height - 1) & 0x7ff) << R300_TX_HEIGHTMASK_SHIFT) | (0 << R300_TX_DEPTHMASK_SHIFT) | (0 << R300_TX_MAX_MIP_LEVEL_SHIFT) | R300_TX_SIZE_TXPITCH_EN); OUT_BATCH_REGVAL(R300_TX_FORMAT_0, r300TranslateTexFormat(mesa_format)); - OUT_BATCH_REGVAL(R300_TX_FORMAT2_0, pitch - 1); + OUT_BATCH_REGVAL(R300_TX_FORMAT2_0, + (pitch - 1) | + (is_r500 && width > 2048 ? R500_TXWIDTH_BIT11 : 0) | + (is_r500 && height > 2048 ? R500_TXHEIGHT_BIT11 : 0)); OUT_BATCH_REGSEQ(R300_TX_OFFSET_0, 1); OUT_BATCH_RELOC(0, bo, offset, RADEON_GEM_DOMAIN_GTT|RADEON_GEM_DOMAIN_VRAM, 0, 0); @@ -340,8 +359,14 @@ static void emit_pvs_setup(struct r300_context *r300, static void emit_vap_setup(struct r300_context *r300) { + int tex_offset; BATCH_LOCALS(&r300->radeon); + if (r300->options.hw_tcl_enabled) + tex_offset = 1; + else + tex_offset = 6; + BEGIN_BATCH(12); OUT_BATCH_REGSEQ(R300_SE_VTE_CNTL, 2); OUT_BATCH(R300_VTX_XY_FMT | R300_VTX_Z_FMT); @@ -350,7 +375,7 @@ static void emit_vap_setup(struct r300_context *r300) OUT_BATCH_REGVAL(R300_VAP_PSC_SGN_NORM_CNTL, 0xaaaaaaaa); OUT_BATCH_REGVAL(R300_VAP_PROG_STREAM_CNTL_0, ((R300_DATA_TYPE_FLOAT_2 | (0 << R300_DST_VEC_LOC_SHIFT)) << 0) | - (((1 << R300_DST_VEC_LOC_SHIFT) | R300_DATA_TYPE_FLOAT_2 | R300_LAST_VEC) << 16)); + (((tex_offset << R300_DST_VEC_LOC_SHIFT) | R300_DATA_TYPE_FLOAT_2 | R300_LAST_VEC) << 16)); OUT_BATCH_REGVAL(R300_VAP_PROG_STREAM_CNTL_EXT_0, ((((R300_SWIZZLE_SELECT_X << R300_SWIZZLE_SELECT_X_SHIFT) | (R300_SWIZZLE_SELECT_Y << R300_SWIZZLE_SELECT_Y_SHIFT) | @@ -373,15 +398,16 @@ static GLboolean validate_buffers(struct r300_context *r300, struct radeon_bo *dst_bo) { int ret; - radeon_cs_space_add_persistent_bo(r300->radeon.cmdbuf.cs, - src_bo, RADEON_GEM_DOMAIN_VRAM, 0); - radeon_cs_space_add_persistent_bo(r300->radeon.cmdbuf.cs, - dst_bo, 0, RADEON_GEM_DOMAIN_VRAM); + radeon_cs_space_reset_bos(r300->radeon.cmdbuf.cs); + + ret = radeon_cs_space_check_with_bo(r300->radeon.cmdbuf.cs, + src_bo, RADEON_GEM_DOMAIN_VRAM | RADEON_GEM_DOMAIN_GTT, 0); + if (ret) + return GL_FALSE; ret = radeon_cs_space_check_with_bo(r300->radeon.cmdbuf.cs, - first_elem(&r300->radeon.dma.reserved)->bo, - RADEON_GEM_DOMAIN_GTT, 0); + dst_bo, 0, RADEON_GEM_DOMAIN_VRAM | RADEON_GEM_DOMAIN_GTT); if (ret) return GL_FALSE; @@ -445,7 +471,7 @@ static void other_stuff(struct r300_context *r300) { BATCH_LOCALS(&r300->radeon); - BEGIN_BATCH(15); + BEGIN_BATCH(13); OUT_BATCH_REGVAL(R300_GA_POLY_MODE, R300_GA_POLY_MODE_FRONT_PTYPE_TRI | R300_GA_POLY_MODE_BACK_PTYPE_TRI); OUT_BATCH_REGVAL(R300_SU_CULL_MODE, R300_FRONT_FACE_CCW); @@ -454,9 +480,13 @@ static void other_stuff(struct r300_context *r300) OUT_BATCH_REGSEQ(R300_RB3D_CBLEND, 2); OUT_BATCH(0x0); OUT_BATCH(0x0); - OUT_BATCH_REGVAL(R300_VAP_CLIP_CNTL, R300_CLIP_DISABLE); OUT_BATCH_REGVAL(R300_ZB_CNTL, 0); END_BATCH(); + if (r300->options.hw_tcl_enabled) { + BEGIN_BATCH(2); + OUT_BATCH_REGVAL(R300_VAP_CLIP_CNTL, R300_CLIP_DISABLE); + END_BATCH(); + } } static void emit_cb_setup(struct r300_context *r300, @@ -494,7 +524,7 @@ static void emit_cb_setup(struct r300_context *r300, END_BATCH(); } -static unsigned is_blit_supported(gl_format dst_format) +unsigned r300_check_blit(gl_format dst_format) { switch (dst_format) { case MESA_FORMAT_RGB565: @@ -539,7 +569,7 @@ static unsigned is_blit_supported(gl_format dst_format) * @param[in] height region height * @param[in] flip_y set if y coords of the source image need to be flipped */ -unsigned r300_blit(GLcontext *ctx, +unsigned r300_blit(struct gl_context *ctx, struct radeon_bo *src_bo, intptr_t src_offset, gl_format src_mesaformat, @@ -562,19 +592,13 @@ unsigned r300_blit(GLcontext *ctx, { r300ContextPtr r300 = R300_CONTEXT(ctx); - if (!is_blit_supported(dst_mesaformat)) + if (!r300_check_blit(dst_mesaformat)) return 0; /* Make sure that colorbuffer has even width - hw limitation */ if (dst_pitch % 2 > 0) ++dst_pitch; - /* Rendering to small buffer doesn't work. - * Looks like a hw limitation. - */ - if (dst_pitch < 32) - return 0; - /* Need to clamp the region size to make sure * we don't read outside of the source buffer * or write outside of the destination buffer. @@ -629,7 +653,9 @@ unsigned r300_blit(GLcontext *ctx, r300_emit_rs_setup(r300); } - emit_pvs_setup(r300, r300->blit.vp_code.body.d, 2); + if (r300->options.hw_tcl_enabled) + emit_pvs_setup(r300, r300->blit.vp_code.body.d, 2); + emit_vap_setup(r300); emit_cb_setup(r300, dst_bo, dst_offset, dst_mesaformat, dst_pitch, dst_width, dst_height);