X-Git-Url: https://git.libre-soc.org/?a=blobdiff_plain;f=src%2Fmesa%2Fdrivers%2Fdri%2Fr300%2Fr300_emit.h;h=8e57e354d1dc2e11bf9cbebfdfc3f5c78d9396b8;hb=995135479d5662d1b1970c0f233c3c3d944d8b4d;hp=db43cc3beed47d774ff313d5b34461789b7c68d3;hpb=72cd2c8c0c863873d280a0e49dfa381e5c3236c8;p=mesa.git diff --git a/src/mesa/drivers/dri/r300/r300_emit.h b/src/mesa/drivers/dri/r300/r300_emit.h index db43cc3beed..8e57e354d1d 100644 --- a/src/mesa/drivers/dri/r300/r300_emit.h +++ b/src/mesa/drivers/dri/r300/r300_emit.h @@ -44,19 +44,13 @@ #include "r300_cmdbuf.h" #include "radeon_reg.h" -/* TODO: move these defines (and the ones from DRM) into r300_reg.h and sync up - * with DRM */ -#define CP_PACKET2 (2 << 30) -#define CP_PACKET0(reg, n) (RADEON_CP_PACKET0 | ((n)<<16) | ((reg)>>2)) -#define CP_PACKET3( pkt, n ) \ - (RADEON_CP_PACKET3 | (pkt) | ((n) << 16)) - static INLINE uint32_t cmdpacket0(struct radeon_screen *rscrn, int reg, int count) { if (!rscrn->kernel_mm) { drm_r300_cmd_header_t cmd; + cmd.u = 0; cmd.packet0.cmd_type = R300_CMD_PACKET0; cmd.packet0.count = count; cmd.packet0.reghi = ((unsigned int)reg & 0xFF00) >> 8; @@ -74,6 +68,7 @@ static INLINE uint32_t cmdvpu(struct radeon_screen *rscrn, int addr, int count) { drm_r300_cmd_header_t cmd; + cmd.u = 0; cmd.vpu.cmd_type = R300_CMD_VPU; cmd.vpu.count = count; cmd.vpu.adrhi = ((unsigned int)addr & 0xFF00) >> 8; @@ -87,6 +82,7 @@ static INLINE uint32_t cmdr500fp(struct radeon_screen *rscrn, { drm_r300_cmd_header_t cmd; + cmd.u = 0; cmd.r500fp.cmd_type = R300_CMD_R500FP; cmd.r500fp.count = count; cmd.r500fp.adrhi_flags = ((unsigned int)addr & 0x100) >> 8; @@ -101,17 +97,20 @@ static INLINE uint32_t cmdpacket3(struct radeon_screen *rscrn, int packet) { drm_r300_cmd_header_t cmd; + cmd.u = 0; cmd.packet3.cmd_type = R300_CMD_PACKET3; cmd.packet3.packet = packet; return cmd.u; } -static INLINE uint32_t cmdcpdelay(struct radeon_screen *rscrn, +static INLINE uint32_t cmdcpdelay(struct radeon_screen *rscrn, unsigned short count) { drm_r300_cmd_header_t cmd; + cmd.u = 0; + cmd.delay.cmd_type = R300_CMD_CP_DELAY; cmd.delay.count = count; @@ -123,6 +122,7 @@ static INLINE uint32_t cmdwait(struct radeon_screen *rscrn, { drm_r300_cmd_header_t cmd; + cmd.u = 0; cmd.wait.cmd_type = R300_CMD_WAIT; cmd.wait.flags = flags; @@ -133,117 +133,97 @@ static INLINE uint32_t cmdpacify(struct radeon_screen *rscrn) { drm_r300_cmd_header_t cmd; + cmd.u = 0; cmd.header.cmd_type = R300_CMD_END3D; return cmd.u; } - -/** Single register write to command buffer; requires 2 dwords. */ -#define OUT_BATCH_REGVAL(reg, val) \ - OUT_BATCH(cmdpacket0(b_l_r300->radeon.radeonScreen, (reg), 1)); \ - OUT_BATCH((val)) - -/** Continuous register range write to command buffer; requires 1 dword, - * expects count dwords afterwards for register contents. */ -#define OUT_BATCH_REGSEQ(reg, count) \ - OUT_BATCH(cmdpacket0(b_l_r300->radeon.radeonScreen, (reg), (count))); - -/** Write a 32 bit float to the ring; requires 1 dword. */ -#define OUT_BATCH_FLOAT32(f) \ - OUT_BATCH(r300PackFloat32((f))); - /** * Write the header of a packet3 to the command buffer. * Outputs 2 dwords and expects (num_extra+1) additional dwords afterwards. */ #define OUT_BATCH_PACKET3(packet, num_extra) do {\ - if (!b_l_r300->radeon.radeonScreen->kernel_mm) { \ - OUT_BATCH(cmdpacket3(b_l_r300->radeon.radeonScreen,\ + if (!b_l_rmesa->radeonScreen->kernel_mm) { \ + OUT_BATCH(cmdpacket3(b_l_rmesa->radeonScreen,\ R300_CMD_PACKET3_RAW)); \ - }\ + } else b_l_rmesa->cmdbuf.cs->section_cdw++;\ OUT_BATCH(CP_PACKET3((packet), (num_extra))); \ } while(0) /** * Must be sent to switch to 2d commands */ -void static INLINE end_3d(r300ContextPtr rmesa) +void static INLINE end_3d(radeonContextPtr radeon) { - BATCH_LOCALS(rmesa); + BATCH_LOCALS(radeon); - if (!rmesa->radeon.radeonScreen->kernel_mm) { - BEGIN_BATCH(1); - OUT_BATCH(cmdpacify(rmesa->radeon.radeonScreen)); - END_BATCH(); - } + if (!radeon->radeonScreen->kernel_mm) { + BEGIN_BATCH_NO_AUTOSTATE(1); + OUT_BATCH(cmdpacify(radeon->radeonScreen)); + END_BATCH(); + } } void static INLINE cp_delay(r300ContextPtr rmesa, unsigned short count) { - BATCH_LOCALS(rmesa); + BATCH_LOCALS(&rmesa->radeon); - if (!rmesa->radeon.radeonScreen->kernel_mm) { - BEGIN_BATCH(1); - OUT_BATCH(cmdcpdelay(rmesa->radeon.radeonScreen, count)); - END_BATCH(); - } + if (!rmesa->radeon.radeonScreen->kernel_mm) { + BEGIN_BATCH_NO_AUTOSTATE(1); + OUT_BATCH(cmdcpdelay(rmesa->radeon.radeonScreen, count)); + END_BATCH(); + } } -void static INLINE cp_wait(r300ContextPtr rmesa, unsigned char flags) +void static INLINE cp_wait(radeonContextPtr radeon, unsigned char flags) { - BATCH_LOCALS(rmesa); - uint32_t wait_until; - - if (!rmesa->radeon.radeonScreen->kernel_mm) { - BEGIN_BATCH_NO_AUTOSTATE(1); - OUT_BATCH(cmdwait(rmesa->radeon.radeonScreen, flags)); - END_BATCH(); - } else { - switch(flags) { - case R300_WAIT_2D: - wait_until = (1 << 14); - break; - case R300_WAIT_3D: - wait_until = (1 << 15); - break; - case R300_NEW_WAIT_2D_3D: - wait_until = (1 << 14) | (1 << 15); - break; - case R300_NEW_WAIT_2D_2D_CLEAN: - wait_until = (1 << 14) | (1 << 16) | (1 << 18); - break; - case R300_NEW_WAIT_3D_3D_CLEAN: - wait_until = (1 << 15) | (1 << 17) | (1 << 18); - break; - case R300_NEW_WAIT_2D_2D_CLEAN_3D_3D_CLEAN: - wait_until = (1 << 14) | (1 << 16) | (1 << 18); - wait_until |= (1 << 15) | (1 << 17) | (1 << 18); - break; - default: - return; - } - BEGIN_BATCH_NO_AUTOSTATE(2); - OUT_BATCH(CP_PACKET0(RADEON_WAIT_UNTIL, 0)); - OUT_BATCH(wait_until); - END_BATCH(); - } + BATCH_LOCALS(radeon); + uint32_t wait_until; + + if (!radeon->radeonScreen->kernel_mm) { + BEGIN_BATCH_NO_AUTOSTATE(1); + OUT_BATCH(cmdwait(radeon->radeonScreen, flags)); + END_BATCH(); + } else { + switch(flags) { + case R300_WAIT_2D: + wait_until = (1 << 14); + break; + case R300_WAIT_3D: + wait_until = (1 << 15); + break; + case R300_NEW_WAIT_2D_3D: + wait_until = (1 << 14) | (1 << 15); + break; + case R300_NEW_WAIT_2D_2D_CLEAN: + wait_until = (1 << 14) | (1 << 16) | (1 << 18); + break; + case R300_NEW_WAIT_3D_3D_CLEAN: + wait_until = (1 << 15) | (1 << 17) | (1 << 18); + break; + case R300_NEW_WAIT_2D_2D_CLEAN_3D_3D_CLEAN: + wait_until = (1 << 14) | (1 << 16) | (1 << 18); + wait_until |= (1 << 15) | (1 << 17) | (1 << 18); + break; + default: + return; + } + BEGIN_BATCH_NO_AUTOSTATE(2); + OUT_BATCH(CP_PACKET0(RADEON_WAIT_UNTIL, 0)); + OUT_BATCH(wait_until); + END_BATCH(); + } } -extern int r300EmitArrays(GLcontext * ctx); - -extern void r300ReleaseArrays(GLcontext * ctx); extern int r300PrimitiveType(r300ContextPtr rmesa, int prim); extern int r300NumVerts(r300ContextPtr rmesa, int num_verts, int prim); extern void r300EmitCacheFlush(r300ContextPtr rmesa); -extern GLuint r300VAPInputRoute0(uint32_t * dst, GLvector4f ** attribptr, - int *inputs, GLint * tab, GLuint nr); -extern GLuint r300VAPInputRoute1(uint32_t * dst, int swizzle[][4], GLuint nr); extern GLuint r300VAPInputCntl0(GLcontext * ctx, GLuint InputsRead); extern GLuint r300VAPInputCntl1(GLcontext * ctx, GLuint InputsRead); -extern GLuint r300VAPOutputCntl0(GLcontext * ctx, GLuint OutputsWritten); -extern GLuint r300VAPOutputCntl1(GLcontext * ctx, GLuint OutputsWritten); +extern GLuint r300VAPOutputCntl0(GLcontext * ctx, GLuint vp_writes); +extern GLuint r300VAPOutputCntl1(GLcontext * ctx, GLuint vp_writes); #endif