X-Git-Url: https://git.libre-soc.org/?a=blobdiff_plain;f=src%2Fmesa%2Fdrivers%2Fdri%2Fr600%2Fr700_chip.c;h=4ec2845ab443a7fc53aa81d20985b929fab0da48;hb=cd6a31cd4a9ea6deef4778c2eaef2d47240c3a6e;hp=cefda3ac4bae9431b214e797f8142d08feaa9e89;hpb=7662e3519bef3802024da3050b886068281e02b1;p=mesa.git diff --git a/src/mesa/drivers/dri/r600/r700_chip.c b/src/mesa/drivers/dri/r600/r700_chip.c index cefda3ac4ba..4ec2845ab44 100644 --- a/src/mesa/drivers/dri/r600/r700_chip.c +++ b/src/mesa/drivers/dri/r600/r700_chip.c @@ -39,7 +39,7 @@ #include "radeon_mipmap_tree.h" -static void r700SendTexState(GLcontext *ctx, struct radeon_state_atom *atom) +static void r700SendTexState(struct gl_context *ctx, struct radeon_state_atom *atom) { context_t *context = R700_CONTEXT(ctx); R700_CHIP_CONTEXT *r700 = (R700_CHIP_CONTEXT*)(&context->hw); @@ -104,7 +104,7 @@ static void r700SendTexState(GLcontext *ctx, struct radeon_state_atom *atom) #define SAMPLER_STRIDE 3 -static void r700SendTexSamplerState(GLcontext *ctx, struct radeon_state_atom *atom) +static void r700SendTexSamplerState(struct gl_context *ctx, struct radeon_state_atom *atom) { context_t *context = R700_CONTEXT(ctx); R700_CHIP_CONTEXT *r700 = (R700_CHIP_CONTEXT*)(&context->hw); @@ -141,7 +141,7 @@ static void r700SendTexSamplerState(GLcontext *ctx, struct radeon_state_atom *at } } -static void r700SendTexBorderColorState(GLcontext *ctx, struct radeon_state_atom *atom) +static void r700SendTexBorderColorState(struct gl_context *ctx, struct radeon_state_atom *atom) { context_t *context = R700_CONTEXT(ctx); R700_CHIP_CONTEXT *r700 = (R700_CHIP_CONTEXT*)(&context->hw); @@ -167,13 +167,12 @@ static void r700SendTexBorderColorState(GLcontext *ctx, struct radeon_state_atom } extern int getTypeSize(GLenum type); -static void r700SetupVTXConstants(GLcontext * ctx, +static void r700SetupVTXConstants(struct gl_context * ctx, void * pAos, StreamDesc * pStreamDesc) { context_t *context = R700_CONTEXT(ctx); struct radeon_aos * paos = (struct radeon_aos *)pAos; - unsigned int nVBsize; BATCH_LOCALS(&context->radeon); unsigned int uSQ_VTX_CONSTANT_WORD0_0; @@ -194,18 +193,8 @@ static void r700SetupVTXConstants(GLcontext * ctx, else r700SyncSurf(context, paos->bo, RADEON_GEM_DOMAIN_GTT, 0, VC_ACTION_ENA_bit); - if(0 == pStreamDesc->stride) - { - nVBsize = paos->count * pStreamDesc->size * getTypeSize(pStreamDesc->type); - } - else - { - nVBsize = (paos->count - 1) * pStreamDesc->stride - + pStreamDesc->size * getTypeSize(pStreamDesc->type); - } - uSQ_VTX_CONSTANT_WORD0_0 = paos->offset; - uSQ_VTX_CONSTANT_WORD1_0 = nVBsize - 1; + uSQ_VTX_CONSTANT_WORD1_0 = paos->bo->size - paos->offset - 1; SETfield(uSQ_VTX_CONSTANT_WORD2_0, 0, BASE_ADDRESS_HI_shift, BASE_ADDRESS_HI_mask); /* TODO */ SETfield(uSQ_VTX_CONSTANT_WORD2_0, pStreamDesc->stride, SQ_VTX_CONSTANT_WORD2_0__STRIDE_shift, @@ -254,7 +243,7 @@ static void r700SetupVTXConstants(GLcontext * ctx, } -static void r700SendVTXState(GLcontext *ctx, struct radeon_state_atom *atom) +static void r700SendVTXState(struct gl_context *ctx, struct radeon_state_atom *atom) { context_t *context = R700_CONTEXT(ctx); struct r700_vertex_program *vp = context->selected_vp; @@ -265,17 +254,6 @@ static void r700SendVTXState(GLcontext *ctx, struct radeon_state_atom *atom) if (context->radeon.tcl.aos_count == 0) return; - BEGIN_BATCH_NO_AUTOSTATE(6); - R600_OUT_BATCH(CP_PACKET3(R600_IT_SET_CTL_CONST, 1)); - R600_OUT_BATCH(mmSQ_VTX_BASE_VTX_LOC - ASIC_CTL_CONST_BASE_INDEX); - R600_OUT_BATCH(0); - - R600_OUT_BATCH(CP_PACKET3(R600_IT_SET_CTL_CONST, 1)); - R600_OUT_BATCH(mmSQ_VTX_START_INST_LOC - ASIC_CTL_CONST_BASE_INDEX); - R600_OUT_BATCH(0); - END_BATCH(); - COMMIT_BATCH(); - for(i=0; imesa_program->Base.InputsRead & (1 << i)) { @@ -292,7 +270,7 @@ static void r700SetRenderTarget(context_t *context, int id) R700_CHIP_CONTEXT *r700 = (R700_CHIP_CONTEXT*)(&context->hw); uint32_t format = COLOR_8_8_8_8, comp_swap = SWAP_ALT, number_type = NUMBER_UNORM; struct radeon_renderbuffer *rrb; - unsigned int nPitchInPixel; + unsigned int nPitchInPixel, height; rrb = radeon_get_colorbuffer(&context->radeon); if (!rrb || !rrb->bo) { @@ -305,9 +283,19 @@ static void r700SetRenderTarget(context_t *context, int id) r700->render_target[id].CB_COLOR0_BASE.u32All = context->radeon.state.color.draw_offset / 256; nPitchInPixel = rrb->pitch/rrb->cpp; + + if (context->radeon.radeonScreen->driScreen->dri2.enabled) + { + height = rrb->base.Height; + } + else + { + height = context->radeon.radeonScreen->driScreen->fbHeight; + } + SETfield(r700->render_target[id].CB_COLOR0_SIZE.u32All, (nPitchInPixel/8)-1, PITCH_TILE_MAX_shift, PITCH_TILE_MAX_mask); - SETfield(r700->render_target[id].CB_COLOR0_SIZE.u32All, ( (nPitchInPixel * context->radeon.radeonScreen->driScreen->fbHeight)/64 )-1, + SETfield(r700->render_target[id].CB_COLOR0_SIZE.u32All, ( (nPitchInPixel * height)/64 )-1, SLICE_TILE_MAX_shift, SLICE_TILE_MAX_mask); SETfield(r700->render_target[id].CB_COLOR0_INFO.u32All, ENDIAN_NONE, ENDIAN_shift, ENDIAN_mask); SETfield(r700->render_target[id].CB_COLOR0_INFO.u32All, ARRAY_LINEAR_GENERAL, @@ -523,9 +511,9 @@ static void r700SetRenderTarget(context_t *context, int id) CB_COLOR0_INFO__ARRAY_MODE_shift, CB_COLOR0_INFO__ARRAY_MODE_mask); CLEARbit(r700->render_target[id].CB_COLOR0_INFO.u32All, SOURCE_FORMAT_bit); break; - case MESA_FORMAT_SRGBA8: + case MESA_FORMAT_SARGB8: format = COLOR_8_8_8_8; - comp_swap = SWAP_STD_REV; + comp_swap = SWAP_ALT; number_type = NUMBER_SRGB; SETbit(r700->render_target[id].CB_COLOR0_INFO.u32All, SOURCE_FORMAT_bit); break; @@ -566,7 +554,7 @@ static void r700SetDepthTarget(context_t *context) R700_CHIP_CONTEXT *r700 = (R700_CHIP_CONTEXT*)(&context->hw); struct radeon_renderbuffer *rrb; - unsigned int nPitchInPixel; + unsigned int nPitchInPixel, height; rrb = radeon_get_depthbuffer(&context->radeon); if (!rrb) @@ -582,9 +570,18 @@ static void r700SetDepthTarget(context_t *context) nPitchInPixel = rrb->pitch/rrb->cpp; + if (context->radeon.radeonScreen->driScreen->dri2.enabled) + { + height = rrb->base.Height; + } + else + { + height = context->radeon.radeonScreen->driScreen->fbHeight; + } + SETfield(r700->DB_DEPTH_SIZE.u32All, (nPitchInPixel/8)-1, PITCH_TILE_MAX_shift, PITCH_TILE_MAX_mask); - SETfield(r700->DB_DEPTH_SIZE.u32All, ( (nPitchInPixel * context->radeon.radeonScreen->driScreen->fbHeight)/64 )-1, + SETfield(r700->DB_DEPTH_SIZE.u32All, ( (nPitchInPixel * height)/64 )-1, SLICE_TILE_MAX_shift, SLICE_TILE_MAX_mask); /* size in pixel / 64 - 1 */ if(4 == rrb->cpp) @@ -602,7 +599,7 @@ static void r700SetDepthTarget(context_t *context) /* r700->DB_PREFETCH_LIMIT.bits.DEPTH_HEIGHT_TILE_MAX = (context->currentDraw->h >> 3) - 1; */ /* z buffer sie may much bigger than what need, so use actual used h. */ } -static void r700SendDepthTargetState(GLcontext *ctx, struct radeon_state_atom *atom) +static void r700SendDepthTargetState(struct gl_context *ctx, struct radeon_state_atom *atom) { context_t *context = R700_CONTEXT(ctx); R700_CHIP_CONTEXT *r700 = R700_CONTEXT_STATES(context); @@ -617,18 +614,25 @@ static void r700SendDepthTargetState(GLcontext *ctx, struct radeon_state_atom *a r700SetDepthTarget(context); - BEGIN_BATCH_NO_AUTOSTATE(8 + 2); + BEGIN_BATCH_NO_AUTOSTATE(7 + 2); R600_OUT_BATCH_REGSEQ(DB_DEPTH_SIZE, 2); R600_OUT_BATCH(r700->DB_DEPTH_SIZE.u32All); R600_OUT_BATCH(r700->DB_DEPTH_VIEW.u32All); - R600_OUT_BATCH_REGSEQ(DB_DEPTH_BASE, 2); + R600_OUT_BATCH_REGSEQ(DB_DEPTH_BASE, 1); R600_OUT_BATCH(r700->DB_DEPTH_BASE.u32All); - R600_OUT_BATCH(r700->DB_DEPTH_INFO.u32All); R600_OUT_BATCH_RELOC(r700->DB_DEPTH_BASE.u32All, rrb->bo, r700->DB_DEPTH_BASE.u32All, 0, RADEON_GEM_DOMAIN_VRAM, 0); END_BATCH(); + BEGIN_BATCH_NO_AUTOSTATE(3 + 2); + R600_OUT_BATCH_REGSEQ(DB_DEPTH_INFO, 1); + R600_OUT_BATCH(r700->DB_DEPTH_INFO.u32All); + R600_OUT_BATCH_RELOC(r700->DB_DEPTH_INFO.u32All, + rrb->bo, + r700->DB_DEPTH_INFO.u32All, + 0, RADEON_GEM_DOMAIN_VRAM, 0); + END_BATCH(); if ((context->radeon.radeonScreen->chip_family > CHIP_FAMILY_R600) && (context->radeon.radeonScreen->chip_family < CHIP_FAMILY_RV770)) { @@ -642,7 +646,7 @@ static void r700SendDepthTargetState(GLcontext *ctx, struct radeon_state_atom *a } -static void r700SendRenderTargetState(GLcontext *ctx, struct radeon_state_atom *atom) +static void r700SendRenderTargetState(struct gl_context *ctx, struct radeon_state_atom *atom) { context_t *context = R700_CONTEXT(ctx); R700_CHIP_CONTEXT *r700 = R700_CONTEXT_STATES(context); @@ -687,36 +691,45 @@ static void r700SendRenderTargetState(GLcontext *ctx, struct radeon_state_atom * BEGIN_BATCH_NO_AUTOSTATE(3 + 2); R600_OUT_BATCH_REGSEQ(CB_COLOR0_TILE + (4 * id), 1); R600_OUT_BATCH(r700->render_target[id].CB_COLOR0_TILE.u32All); - R600_OUT_BATCH_RELOC(r700->render_target[id].CB_COLOR0_BASE.u32All, + R600_OUT_BATCH_RELOC(r700->render_target[id].CB_COLOR0_TILE.u32All, rrb->bo, - r700->render_target[id].CB_COLOR0_BASE.u32All, + r700->render_target[id].CB_COLOR0_TILE.u32All, 0, RADEON_GEM_DOMAIN_VRAM, 0); END_BATCH(); BEGIN_BATCH_NO_AUTOSTATE(3 + 2); R600_OUT_BATCH_REGSEQ(CB_COLOR0_FRAG + (4 * id), 1); R600_OUT_BATCH(r700->render_target[id].CB_COLOR0_FRAG.u32All); - R600_OUT_BATCH_RELOC(r700->render_target[id].CB_COLOR0_BASE.u32All, + R600_OUT_BATCH_RELOC(r700->render_target[id].CB_COLOR0_FRAG.u32All, rrb->bo, - r700->render_target[id].CB_COLOR0_BASE.u32All, + r700->render_target[id].CB_COLOR0_FRAG.u32All, 0, RADEON_GEM_DOMAIN_VRAM, 0); END_BATCH(); - BEGIN_BATCH_NO_AUTOSTATE(12); + BEGIN_BATCH_NO_AUTOSTATE(9); R600_OUT_BATCH_REGVAL(CB_COLOR0_SIZE + (4 * id), r700->render_target[id].CB_COLOR0_SIZE.u32All); R600_OUT_BATCH_REGVAL(CB_COLOR0_VIEW + (4 * id), r700->render_target[id].CB_COLOR0_VIEW.u32All); - R600_OUT_BATCH_REGVAL(CB_COLOR0_INFO + (4 * id), r700->render_target[id].CB_COLOR0_INFO.u32All); R600_OUT_BATCH_REGVAL(CB_COLOR0_MASK + (4 * id), r700->render_target[id].CB_COLOR0_MASK.u32All); END_BATCH(); + BEGIN_BATCH_NO_AUTOSTATE(3 + 2); + R600_OUT_BATCH_REGVAL(CB_COLOR0_INFO + (4 * id), r700->render_target[id].CB_COLOR0_INFO.u32All); + R600_OUT_BATCH_RELOC(r700->render_target[id].CB_COLOR0_INFO.u32All, + rrb->bo, + r700->render_target[id].CB_COLOR0_INFO.u32All, + 0, RADEON_GEM_DOMAIN_VRAM, 0); + + END_BATCH(); + COMMIT_BATCH(); } -static void r700SendPSState(GLcontext *ctx, struct radeon_state_atom *atom) +static void r700SendPSState(struct gl_context *ctx, struct radeon_state_atom *atom) { context_t *context = R700_CONTEXT(ctx); R700_CHIP_CONTEXT *r700 = R700_CONTEXT_STATES(context); struct radeon_bo * pbo; + struct radeon_bo * pbo_const; BATCH_LOCALS(&context->radeon); radeon_print(RADEON_STATE, RADEON_VERBOSE, "%s\n", __func__); @@ -746,22 +759,26 @@ static void r700SendPSState(GLcontext *ctx, struct radeon_state_atom *atom) R600_OUT_BATCH_REGVAL(SQ_LOOP_CONST_0, 0x01000FFF); END_BATCH(); + pbo_const = (struct radeon_bo *)r700GetActiveFpShaderConstBo(GL_CONTEXT(context)); + //TODO : set up shader const + COMMIT_BATCH(); } -static void r700SendVSState(GLcontext *ctx, struct radeon_state_atom *atom) +static void r700SendVSState(struct gl_context *ctx, struct radeon_state_atom *atom) { context_t *context = R700_CONTEXT(ctx); R700_CHIP_CONTEXT *r700 = R700_CONTEXT_STATES(context); struct radeon_bo * pbo; + struct radeon_bo * pbo_const; BATCH_LOCALS(&context->radeon); radeon_print(RADEON_STATE, RADEON_VERBOSE, "%s\n", __func__); pbo = (struct radeon_bo *)r700GetActiveVpShaderBo(GL_CONTEXT(context)); if (!pbo) - return; + return; r700SyncSurf(context, pbo, RADEON_GEM_DOMAIN_GTT, 0, SH_ACTION_ENA_bit); @@ -784,10 +801,33 @@ static void r700SendVSState(GLcontext *ctx, struct radeon_state_atom *atom) //R600_OUT_BATCH_REGVAL((SQ_LOOP_CONST_0 + (SQ_LOOP_CONST_vs<2)), 0x0100000F); END_BATCH(); + /* TODO : handle 4 bufs */ + if(GL_TRUE == r700->bShaderUseMemConstant) + { + pbo_const = (struct radeon_bo *)r700GetActiveVpShaderConstBo(GL_CONTEXT(context)); + if(NULL != pbo_const) + { + r700SyncSurf(context, pbo_const, RADEON_GEM_DOMAIN_GTT, 0, SH_ACTION_ENA_bit); /* TODO : Check kc bit. */ + + BEGIN_BATCH_NO_AUTOSTATE(3); + R600_OUT_BATCH_REGVAL(SQ_ALU_CONST_BUFFER_SIZE_VS_0, (r700->vs.num_consts * 4)/16 ); + END_BATCH(); + + BEGIN_BATCH_NO_AUTOSTATE(3 + 2); + R600_OUT_BATCH_REGSEQ(SQ_ALU_CONST_CACHE_VS_0, 1); + R600_OUT_BATCH(r700->vs.SQ_ALU_CONST_CACHE_VS_0.u32All); + R600_OUT_BATCH_RELOC(r700->vs.SQ_ALU_CONST_CACHE_VS_0.u32All, + pbo_const, + r700->vs.SQ_ALU_CONST_CACHE_VS_0.u32All, + RADEON_GEM_DOMAIN_GTT, 0, 0); + END_BATCH(); + } + } + COMMIT_BATCH(); } -static void r700SendFSState(GLcontext *ctx, struct radeon_state_atom *atom) +static void r700SendFSState(struct gl_context *ctx, struct radeon_state_atom *atom) { context_t *context = R700_CONTEXT(ctx); R700_CHIP_CONTEXT *r700 = R700_CONTEXT_STATES(context); @@ -829,7 +869,7 @@ static void r700SendFSState(GLcontext *ctx, struct radeon_state_atom *atom) } -static void r700SendViewportState(GLcontext *ctx, struct radeon_state_atom *atom) +static void r700SendViewportState(struct gl_context *ctx, struct radeon_state_atom *atom) { context_t *context = R700_CONTEXT(ctx); R700_CHIP_CONTEXT *r700 = R700_CONTEXT_STATES(context); @@ -863,7 +903,7 @@ static void r700SendViewportState(GLcontext *ctx, struct radeon_state_atom *atom } -static void r700SendSQConfig(GLcontext *ctx, struct radeon_state_atom *atom) +static void r700SendSQConfig(struct gl_context *ctx, struct radeon_state_atom *atom) { context_t *context = R700_CONTEXT(ctx); R700_CHIP_CONTEXT *r700 = R700_CONTEXT_STATES(context); @@ -900,7 +940,7 @@ static void r700SendSQConfig(GLcontext *ctx, struct radeon_state_atom *atom) COMMIT_BATCH(); } -static void r700SendUCPState(GLcontext *ctx, struct radeon_state_atom *atom) +static void r700SendUCPState(struct gl_context *ctx, struct radeon_state_atom *atom) { context_t *context = R700_CONTEXT(ctx); R700_CHIP_CONTEXT *r700 = R700_CONTEXT_STATES(context); @@ -922,7 +962,7 @@ static void r700SendUCPState(GLcontext *ctx, struct radeon_state_atom *atom) } } -static void r700SendSPIState(GLcontext *ctx, struct radeon_state_atom *atom) +static void r700SendSPIState(struct gl_context *ctx, struct radeon_state_atom *atom) { context_t *context = R700_CONTEXT(ctx); R700_CHIP_CONTEXT *r700 = R700_CONTEXT_STATES(context); @@ -997,7 +1037,7 @@ static void r700SendSPIState(GLcontext *ctx, struct radeon_state_atom *atom) COMMIT_BATCH(); } -static void r700SendVGTState(GLcontext *ctx, struct radeon_state_atom *atom) +static void r700SendVGTState(struct gl_context *ctx, struct radeon_state_atom *atom) { context_t *context = R700_CONTEXT(ctx); R700_CHIP_CONTEXT *r700 = R700_CONTEXT_STATES(context); @@ -1043,7 +1083,7 @@ static void r700SendVGTState(GLcontext *ctx, struct radeon_state_atom *atom) COMMIT_BATCH(); } -static void r700SendSXState(GLcontext *ctx, struct radeon_state_atom *atom) +static void r700SendSXState(struct gl_context *ctx, struct radeon_state_atom *atom) { context_t *context = R700_CONTEXT(ctx); R700_CHIP_CONTEXT *r700 = R700_CONTEXT_STATES(context); @@ -1058,7 +1098,7 @@ static void r700SendSXState(GLcontext *ctx, struct radeon_state_atom *atom) COMMIT_BATCH(); } -static void r700SendDBState(GLcontext *ctx, struct radeon_state_atom *atom) +static void r700SendDBState(struct gl_context *ctx, struct radeon_state_atom *atom) { context_t *context = R700_CONTEXT(ctx); R700_CHIP_CONTEXT *r700 = R700_CONTEXT_STATES(context); @@ -1084,7 +1124,7 @@ static void r700SendDBState(GLcontext *ctx, struct radeon_state_atom *atom) COMMIT_BATCH(); } -static void r700SendStencilState(GLcontext *ctx, struct radeon_state_atom *atom) +static void r700SendStencilState(struct gl_context *ctx, struct radeon_state_atom *atom) { context_t *context = R700_CONTEXT(ctx); R700_CHIP_CONTEXT *r700 = R700_CONTEXT_STATES(context); @@ -1098,7 +1138,7 @@ static void r700SendStencilState(GLcontext *ctx, struct radeon_state_atom *atom) COMMIT_BATCH(); } -static void r700SendCBState(GLcontext *ctx, struct radeon_state_atom *atom) +static void r700SendCBState(struct gl_context *ctx, struct radeon_state_atom *atom) { context_t *context = R700_CONTEXT(ctx); R700_CHIP_CONTEXT *r700 = R700_CONTEXT_STATES(context); @@ -1128,7 +1168,7 @@ static void r700SendCBState(GLcontext *ctx, struct radeon_state_atom *atom) COMMIT_BATCH(); } -static void r700SendCBCLRCMPState(GLcontext *ctx, struct radeon_state_atom *atom) +static void r700SendCBCLRCMPState(struct gl_context *ctx, struct radeon_state_atom *atom) { context_t *context = R700_CONTEXT(ctx); R700_CHIP_CONTEXT *r700 = R700_CONTEXT_STATES(context); @@ -1144,7 +1184,7 @@ static void r700SendCBCLRCMPState(GLcontext *ctx, struct radeon_state_atom *atom COMMIT_BATCH(); } -static void r700SendCBBlendState(GLcontext *ctx, struct radeon_state_atom *atom) +static void r700SendCBBlendState(struct gl_context *ctx, struct radeon_state_atom *atom) { context_t *context = R700_CONTEXT(ctx); R700_CHIP_CONTEXT *r700 = R700_CONTEXT_STATES(context); @@ -1176,7 +1216,7 @@ static void r700SendCBBlendState(GLcontext *ctx, struct radeon_state_atom *atom) COMMIT_BATCH(); } -static void r700SendCBBlendColorState(GLcontext *ctx, struct radeon_state_atom *atom) +static void r700SendCBBlendColorState(struct gl_context *ctx, struct radeon_state_atom *atom) { context_t *context = R700_CONTEXT(ctx); R700_CHIP_CONTEXT *r700 = R700_CONTEXT_STATES(context); @@ -1193,7 +1233,7 @@ static void r700SendCBBlendColorState(GLcontext *ctx, struct radeon_state_atom * COMMIT_BATCH(); } -static void r700SendSUState(GLcontext *ctx, struct radeon_state_atom *atom) +static void r700SendSUState(struct gl_context *ctx, struct radeon_state_atom *atom) { context_t *context = R700_CONTEXT(ctx); R700_CHIP_CONTEXT *r700 = R700_CONTEXT_STATES(context); @@ -1211,7 +1251,7 @@ static void r700SendSUState(GLcontext *ctx, struct radeon_state_atom *atom) } -static void r700SendPolyState(GLcontext *ctx, struct radeon_state_atom *atom) +static void r700SendPolyState(struct gl_context *ctx, struct radeon_state_atom *atom) { context_t *context = R700_CONTEXT(ctx); R700_CHIP_CONTEXT *r700 = R700_CONTEXT_STATES(context); @@ -1231,7 +1271,7 @@ static void r700SendPolyState(GLcontext *ctx, struct radeon_state_atom *atom) } -static void r700SendCLState(GLcontext *ctx, struct radeon_state_atom *atom) +static void r700SendCLState(struct gl_context *ctx, struct radeon_state_atom *atom) { context_t *context = R700_CONTEXT(ctx); R700_CHIP_CONTEXT *r700 = R700_CONTEXT_STATES(context); @@ -1247,7 +1287,7 @@ static void r700SendCLState(GLcontext *ctx, struct radeon_state_atom *atom) COMMIT_BATCH(); } -static void r700SendGBState(GLcontext *ctx, struct radeon_state_atom *atom) +static void r700SendGBState(struct gl_context *ctx, struct radeon_state_atom *atom) { context_t *context = R700_CONTEXT(ctx); R700_CHIP_CONTEXT *r700 = R700_CONTEXT_STATES(context); @@ -1263,7 +1303,7 @@ static void r700SendGBState(GLcontext *ctx, struct radeon_state_atom *atom) COMMIT_BATCH(); } -static void r700SendScissorState(GLcontext *ctx, struct radeon_state_atom *atom) +static void r700SendScissorState(struct gl_context *ctx, struct radeon_state_atom *atom) { context_t *context = R700_CONTEXT(ctx); R700_CHIP_CONTEXT *r700 = R700_CONTEXT_STATES(context); @@ -1296,7 +1336,7 @@ static void r700SendScissorState(GLcontext *ctx, struct radeon_state_atom *atom) COMMIT_BATCH(); } -static void r700SendSCState(GLcontext *ctx, struct radeon_state_atom *atom) +static void r700SendSCState(struct gl_context *ctx, struct radeon_state_atom *atom) { context_t *context = R700_CONTEXT(ctx); R700_CHIP_CONTEXT *r700 = R700_CONTEXT_STATES(context); @@ -1313,7 +1353,7 @@ static void r700SendSCState(GLcontext *ctx, struct radeon_state_atom *atom) COMMIT_BATCH(); } -static void r700SendAAState(GLcontext *ctx, struct radeon_state_atom *atom) +static void r700SendAAState(struct gl_context *ctx, struct radeon_state_atom *atom) { context_t *context = R700_CONTEXT(ctx); R700_CHIP_CONTEXT *r700 = R700_CONTEXT_STATES(context); @@ -1328,7 +1368,7 @@ static void r700SendAAState(GLcontext *ctx, struct radeon_state_atom *atom) COMMIT_BATCH(); } -static void r700SendPSConsts(GLcontext *ctx, struct radeon_state_atom *atom) +static void r700SendPSConsts(struct gl_context *ctx, struct radeon_state_atom *atom) { context_t *context = R700_CONTEXT(ctx); R700_CHIP_CONTEXT *r700 = R700_CONTEXT_STATES(context); @@ -1352,7 +1392,7 @@ static void r700SendPSConsts(GLcontext *ctx, struct radeon_state_atom *atom) COMMIT_BATCH(); } -static void r700SendVSConsts(GLcontext *ctx, struct radeon_state_atom *atom) +static void r700SendVSConsts(struct gl_context *ctx, struct radeon_state_atom *atom) { context_t *context = R700_CONTEXT(ctx); R700_CHIP_CONTEXT *r700 = R700_CONTEXT_STATES(context); @@ -1377,7 +1417,7 @@ static void r700SendVSConsts(GLcontext *ctx, struct radeon_state_atom *atom) COMMIT_BATCH(); } -static void r700SendQueryBegin(GLcontext *ctx, struct radeon_state_atom *atom) +static void r700SendQueryBegin(struct gl_context *ctx, struct radeon_state_atom *atom) { radeonContextPtr radeon = RADEON_CONTEXT(ctx); struct radeon_query_object *query = radeon->query.current; @@ -1395,7 +1435,7 @@ static void r700SendQueryBegin(GLcontext *ctx, struct radeon_state_atom *atom) BEGIN_BATCH_NO_AUTOSTATE(4 + 2); R600_OUT_BATCH(CP_PACKET3(R600_IT_EVENT_WRITE, 2)); - R600_OUT_BATCH(ZPASS_DONE); + R600_OUT_BATCH(R600_EVENT_TYPE(ZPASS_DONE) | R600_EVENT_INDEX(1)); R600_OUT_BATCH(query->curr_offset); /* hw writes qwords */ R600_OUT_BATCH(0x00000000); R600_OUT_BATCH_RELOC(VGT_EVENT_INITIATOR, query->bo, 0, 0, RADEON_GEM_DOMAIN_GTT, 0); @@ -1403,12 +1443,12 @@ static void r700SendQueryBegin(GLcontext *ctx, struct radeon_state_atom *atom) query->emitted_begin = GL_TRUE; } -static int check_always(GLcontext *ctx, struct radeon_state_atom *atom) +static int check_always(struct gl_context *ctx, struct radeon_state_atom *atom) { return atom->cmd_size; } -static int check_cb(GLcontext *ctx, struct radeon_state_atom *atom) +static int check_cb(struct gl_context *ctx, struct radeon_state_atom *atom) { context_t *context = R700_CONTEXT(ctx); int count = 7; @@ -1420,7 +1460,7 @@ static int check_cb(GLcontext *ctx, struct radeon_state_atom *atom) return count; } -static int check_blnd(GLcontext *ctx, struct radeon_state_atom *atom) +static int check_blnd(struct gl_context *ctx, struct radeon_state_atom *atom) { context_t *context = R700_CONTEXT(ctx); R700_CHIP_CONTEXT *r700 = (R700_CHIP_CONTEXT*)(&context->hw); @@ -1445,7 +1485,7 @@ static int check_blnd(GLcontext *ctx, struct radeon_state_atom *atom) return count; } -static int check_ucp(GLcontext *ctx, struct radeon_state_atom *atom) +static int check_ucp(struct gl_context *ctx, struct radeon_state_atom *atom) { context_t *context = R700_CONTEXT(ctx); R700_CHIP_CONTEXT *r700 = (R700_CHIP_CONTEXT*)(&context->hw); @@ -1460,19 +1500,16 @@ static int check_ucp(GLcontext *ctx, struct radeon_state_atom *atom) return count; } -static int check_vtx(GLcontext *ctx, struct radeon_state_atom *atom) +static int check_vtx(struct gl_context *ctx, struct radeon_state_atom *atom) { context_t *context = R700_CONTEXT(ctx); int count = context->radeon.tcl.aos_count * 18; - if (count) - count += 6; - radeon_print(RADEON_STATE, RADEON_TRACE, "%s %d\n", __func__, count); return count; } -static int check_tx(GLcontext *ctx, struct radeon_state_atom *atom) +static int check_tx(struct gl_context *ctx, struct radeon_state_atom *atom) { context_t *context = R700_CONTEXT(ctx); unsigned int i, count = 0; @@ -1489,7 +1526,7 @@ static int check_tx(GLcontext *ctx, struct radeon_state_atom *atom) return count * 31; } -static int check_ps_consts(GLcontext *ctx, struct radeon_state_atom *atom) +static int check_ps_consts(struct gl_context *ctx, struct radeon_state_atom *atom) { context_t *context = R700_CONTEXT(ctx); R700_CHIP_CONTEXT *r700 = (R700_CHIP_CONTEXT*)(&context->hw); @@ -1502,7 +1539,7 @@ static int check_ps_consts(GLcontext *ctx, struct radeon_state_atom *atom) return count; } -static int check_vs_consts(GLcontext *ctx, struct radeon_state_atom *atom) +static int check_vs_consts(struct gl_context *ctx, struct radeon_state_atom *atom) { context_t *context = R700_CONTEXT(ctx); R700_CHIP_CONTEXT *r700 = (R700_CHIP_CONTEXT*)(&context->hw); @@ -1515,7 +1552,7 @@ static int check_vs_consts(GLcontext *ctx, struct radeon_state_atom *atom) return count; } -static int check_queryobj(GLcontext *ctx, struct radeon_state_atom *atom) +static int check_queryobj(struct gl_context *ctx, struct radeon_state_atom *atom) { radeonContextPtr radeon = RADEON_CONTEXT(ctx); struct radeon_query_object *query = radeon->query.current; @@ -1557,45 +1594,55 @@ static void r600_init_query_stateobj(radeonContextPtr radeon, int SZ) void r600InitAtoms(context_t *context) { - radeon_print(RADEON_STATE, RADEON_NORMAL, "%s %p\n", __func__, context); - context->radeon.hw.max_state_size = 10 + 5 + 14; /* start 3d, idle, cb/db flush */ - - /* Setup the atom linked list */ - make_empty_list(&context->radeon.hw.atomlist); - context->radeon.hw.atomlist.name = "atom-list"; - - ALLOC_STATE(sq, always, 34, r700SendSQConfig); - ALLOC_STATE(db, always, 17, r700SendDBState); - ALLOC_STATE(stencil, always, 4, r700SendStencilState); - ALLOC_STATE(db_target, always, 12, r700SendDepthTargetState); - ALLOC_STATE(sc, always, 15, r700SendSCState); - ALLOC_STATE(scissor, always, 22, r700SendScissorState); - ALLOC_STATE(aa, always, 12, r700SendAAState); - ALLOC_STATE(cl, always, 12, r700SendCLState); - ALLOC_STATE(gb, always, 6, r700SendGBState); - ALLOC_STATE(ucp, ucp, (R700_MAX_UCP * 6), r700SendUCPState); - ALLOC_STATE(su, always, 9, r700SendSUState); - ALLOC_STATE(poly, always, 10, r700SendPolyState); - ALLOC_STATE(cb, cb, 18, r700SendCBState); - ALLOC_STATE(clrcmp, always, 6, r700SendCBCLRCMPState); - ALLOC_STATE(cb_target, always, 29, r700SendRenderTargetState); - ALLOC_STATE(blnd, blnd, (6 + (R700_MAX_RENDER_TARGETS * 3)), r700SendCBBlendState); - ALLOC_STATE(blnd_clr, always, 6, r700SendCBBlendColorState); - ALLOC_STATE(sx, always, 9, r700SendSXState); - ALLOC_STATE(vgt, always, 41, r700SendVGTState); - ALLOC_STATE(spi, always, (59 + R700_MAX_SHADER_EXPORTS), r700SendSPIState); - ALLOC_STATE(vpt, always, 16, r700SendViewportState); - ALLOC_STATE(fs, always, 18, r700SendFSState); - ALLOC_STATE(vs, always, 21, r700SendVSState); - ALLOC_STATE(ps, always, 24, r700SendPSState); - ALLOC_STATE(vs_consts, vs_consts, (2 + (R700_MAX_DX9_CONSTS * 4)), r700SendVSConsts); - ALLOC_STATE(ps_consts, ps_consts, (2 + (R700_MAX_DX9_CONSTS * 4)), r700SendPSConsts); - ALLOC_STATE(vtx, vtx, (6 + (VERT_ATTRIB_MAX * 18)), r700SendVTXState); - ALLOC_STATE(tx, tx, (R700_TEXTURE_NUMBERUNITS * 20), r700SendTexState); - ALLOC_STATE(tx_smplr, tx, (R700_TEXTURE_NUMBERUNITS * 5), r700SendTexSamplerState); - ALLOC_STATE(tx_brdr_clr, tx, (R700_TEXTURE_NUMBERUNITS * 6), r700SendTexBorderColorState); - r600_init_query_stateobj(&context->radeon, 6 * 2); - - context->radeon.hw.is_dirty = GL_TRUE; - context->radeon.hw.all_dirty = GL_TRUE; + R700_CHIP_CONTEXT *r700 = (R700_CHIP_CONTEXT*)(&context->hw); + radeon_print(RADEON_STATE, RADEON_NORMAL, "%s %p\n", __func__, context); + context->radeon.hw.max_state_size = 10 + 5 + 14; /* start 3d, idle, cb/db flush */ + + /* Setup the atom linked list */ + make_empty_list(&context->radeon.hw.atomlist); + context->radeon.hw.atomlist.name = "atom-list"; + + ALLOC_STATE(sq, always, 34, r700SendSQConfig); + ALLOC_STATE(db, always, 17, r700SendDBState); + ALLOC_STATE(stencil, always, 4, r700SendStencilState); + ALLOC_STATE(db_target, always, 16, r700SendDepthTargetState); + ALLOC_STATE(sc, always, 15, r700SendSCState); + ALLOC_STATE(scissor, always, 22, r700SendScissorState); + ALLOC_STATE(aa, always, 12, r700SendAAState); + ALLOC_STATE(cl, always, 12, r700SendCLState); + ALLOC_STATE(gb, always, 6, r700SendGBState); + ALLOC_STATE(ucp, ucp, (R700_MAX_UCP * 6), r700SendUCPState); + ALLOC_STATE(su, always, 9, r700SendSUState); + ALLOC_STATE(poly, always, 10, r700SendPolyState); + ALLOC_STATE(cb, cb, 18, r700SendCBState); + ALLOC_STATE(clrcmp, always, 6, r700SendCBCLRCMPState); + ALLOC_STATE(cb_target, always, 31, r700SendRenderTargetState); + ALLOC_STATE(blnd, blnd, (6 + (R700_MAX_RENDER_TARGETS * 3)), r700SendCBBlendState); + ALLOC_STATE(blnd_clr, always, 6, r700SendCBBlendColorState); + ALLOC_STATE(sx, always, 9, r700SendSXState); + ALLOC_STATE(vgt, always, 41, r700SendVGTState); + ALLOC_STATE(spi, always, (59 + R700_MAX_SHADER_EXPORTS), r700SendSPIState); + ALLOC_STATE(vpt, always, 16, r700SendViewportState); + ALLOC_STATE(fs, always, 18, r700SendFSState); + if(GL_TRUE == r700->bShaderUseMemConstant) + { + ALLOC_STATE(vs, always, 36, r700SendVSState); + ALLOC_STATE(ps, always, 24, r700SendPSState); /* TODO : not imp yet, fix later. */ + } + else + { + ALLOC_STATE(vs, always, 21, r700SendVSState); + ALLOC_STATE(ps, always, 24, r700SendPSState); + ALLOC_STATE(vs_consts, vs_consts, (2 + (R700_MAX_DX9_CONSTS * 4)), r700SendVSConsts); + ALLOC_STATE(ps_consts, ps_consts, (2 + (R700_MAX_DX9_CONSTS * 4)), r700SendPSConsts); + } + + ALLOC_STATE(vtx, vtx, (VERT_ATTRIB_MAX * 18), r700SendVTXState); + ALLOC_STATE(tx, tx, (R700_TEXTURE_NUMBERUNITS * 20), r700SendTexState); + ALLOC_STATE(tx_smplr, tx, (R700_TEXTURE_NUMBERUNITS * 5), r700SendTexSamplerState); + ALLOC_STATE(tx_brdr_clr, tx, (R700_TEXTURE_NUMBERUNITS * 6), r700SendTexBorderColorState); + r600_init_query_stateobj(&context->radeon, 6 * 2); + + context->radeon.hw.is_dirty = GL_TRUE; + context->radeon.hw.all_dirty = GL_TRUE; }