X-Git-Url: https://git.libre-soc.org/?a=blobdiff_plain;f=src%2Fmesa%2Fdrivers%2Fdri%2Fradeon%2Fradeon_common.c;h=cc3fed8623d251b3ee3df27031acf17c8d3fbfb5;hb=1837fb8e7c3cef8b9292b68da152d185e7103646;hp=2a2b16a54bd2bba0b9f2744f92ff157e3e6fd37f;hpb=112908c279b0a768eca95a505856a087e479674b;p=mesa.git

diff --git a/src/mesa/drivers/dri/radeon/radeon_common.c b/src/mesa/drivers/dri/radeon/radeon_common.c
index 2a2b16a54bd..cc3fed8623d 100644
--- a/src/mesa/drivers/dri/radeon/radeon_common.c
+++ b/src/mesa/drivers/dri/radeon/radeon_common.c
@@ -50,11 +50,7 @@ WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
 #include "main/renderbuffer.h"
 #include "drivers/common/meta.h"
 
-#include "vblank.h"
-
 #include "radeon_common.h"
-#include "radeon_bocs_wrapper.h"
-#include "radeon_lock.h"
 #include "radeon_drm.h"
 #include "radeon_queryobj.h"
 
@@ -91,24 +87,18 @@ static GLboolean intersect_rect(drm_clip_rect_t * out,
 
 void radeonRecalcScissorRects(radeonContextPtr radeon)
 {
-	drm_clip_rect_t *out;
-	int i;
+	struct gl_context *ctx = radeon->glCtx;
+	drm_clip_rect_t bounds;
 
-	/* Grow cliprect store?
-	 */
-	if (radeon->state.scissor.numAllocedClipRects < radeon->numClipRects) {
-		while (radeon->state.scissor.numAllocedClipRects <
-		       radeon->numClipRects) {
-			radeon->state.scissor.numAllocedClipRects += 1;	/* zero case */
-			radeon->state.scissor.numAllocedClipRects *= 2;
-		}
-
-		if (radeon->state.scissor.pClipRects)
-			FREE(radeon->state.scissor.pClipRects);
+	bounds.x1 = 0;
+	bounds.y1 = 0;
+	bounds.x2 = ctx->DrawBuffer->Width;
+	bounds.x2 = ctx->DrawBuffer->Height;
 
+	if (!radeon->state.scissor.numAllocedClipRects) {
+		radeon->state.scissor.numAllocedClipRects = 1;
 		radeon->state.scissor.pClipRects =
-			MALLOC(radeon->state.scissor.numAllocedClipRects *
-			       sizeof(drm_clip_rect_t));
+			MALLOC(sizeof(drm_clip_rect_t));
 
 		if (radeon->state.scissor.pClipRects == NULL) {
 			radeon->state.scissor.numAllocedClipRects = 0;
@@ -116,67 +106,30 @@ void radeonRecalcScissorRects(radeonContextPtr radeon)
 		}
 	}
 
-	out = radeon->state.scissor.pClipRects;
 	radeon->state.scissor.numClipRects = 0;
-
-	for (i = 0; i < radeon->numClipRects; i++) {
-		if (intersect_rect(out,
-				   &radeon->pClipRects[i],
-				   &radeon->state.scissor.rect)) {
-			radeon->state.scissor.numClipRects++;
-			out++;
-		}
+	if (intersect_rect(radeon->state.scissor.pClipRects,
+			   &bounds,
+			   &radeon->state.scissor.rect)) {
+		radeon->state.scissor.numClipRects = 1;
 	}
 
 	if (radeon->vtbl.update_scissor)
 	   radeon->vtbl.update_scissor(radeon->glCtx);
 }
 
-void radeon_get_cliprects(radeonContextPtr radeon,
-			  struct drm_clip_rect **cliprects,
-			  unsigned int *num_cliprects,
-			  int *x_off, int *y_off)
-{
-	__DRIdrawablePrivate *dPriv = radeon_get_drawable(radeon);
-	struct radeon_framebuffer *rfb = dPriv->driverPrivate;
-
-	if (radeon->constant_cliprect) {
-		radeon->fboRect.x1 = 0;
-		radeon->fboRect.y1 = 0;
-		radeon->fboRect.x2 = radeon->glCtx->DrawBuffer->Width;
-		radeon->fboRect.y2 = radeon->glCtx->DrawBuffer->Height;
-
-		*cliprects = &radeon->fboRect;
-		*num_cliprects = 1;
-		*x_off = 0;
-		*y_off = 0;
-	} else if (radeon->front_cliprects ||
-		   rfb->pf_active || dPriv->numBackClipRects == 0) {
-		*cliprects = dPriv->pClipRects;
-		*num_cliprects = dPriv->numClipRects;
-		*x_off = dPriv->x;
-		*y_off = dPriv->y;
-	} else {
-		*num_cliprects = dPriv->numBackClipRects;
-		*cliprects = dPriv->pBackClipRects;
-		*x_off = dPriv->backX;
-		*y_off = dPriv->backY;
-	}
-}
-
 /**
  * Update cliprects and scissors.
  */
 void radeonSetCliprects(radeonContextPtr radeon)
 {
-	__DRIdrawablePrivate *const drawable = radeon_get_drawable(radeon);
-	__DRIdrawablePrivate *const readable = radeon_get_readable(radeon);
+	__DRIdrawable *const drawable = radeon_get_drawable(radeon);
+	__DRIdrawable *const readable = radeon_get_readable(radeon);
+
+	if(drawable == NULL && readable == NULL)
+		return;
+
 	struct radeon_framebuffer *const draw_rfb = drawable->driverPrivate;
 	struct radeon_framebuffer *const read_rfb = readable->driverPrivate;
-	int x_off, y_off;
-
-	radeon_get_cliprects(radeon, &radeon->pClipRects,
-			     &radeon->numClipRects, &x_off, &y_off);
 
 	if ((draw_rfb->base.Width != drawable->w) ||
 	    (draw_rfb->base.Height != drawable->h)) {
@@ -201,7 +154,7 @@ void radeonSetCliprects(radeonContextPtr radeon)
 
 
 
-void radeonUpdateScissor( GLcontext *ctx )
+void radeonUpdateScissor( struct gl_context *ctx )
 {
 	radeonContextPtr rmesa = RADEON_CONTEXT(ctx);
 	GLint x = ctx->Scissor.X, y = ctx->Scissor.Y;
@@ -227,18 +180,6 @@ void radeonUpdateScissor( GLcontext *ctx )
 		y2 = y + h - 1;
 
 	}
-	if (!rmesa->radeonScreen->kernel_mm) {
-	   /* Fix scissors for dri 1 */
-	   __DRIdrawablePrivate *dPriv = radeon_get_drawable(rmesa);
-	   x1 += dPriv->x;
-	   x2 += dPriv->x + 1;
-	   min_x += dPriv->x;
-	   max_x += dPriv->x + 1;
-	   y1 += dPriv->y;
-	   y2 += dPriv->y + 1;
-	   min_y += dPriv->y;
-	   max_y += dPriv->y + 1;
-	}
 
 	rmesa->state.scissor.rect.x1 = CLAMP(x1,  min_x, max_x);
 	rmesa->state.scissor.rect.y1 = CLAMP(y1,  min_y, max_y);
@@ -252,7 +193,7 @@ void radeonUpdateScissor( GLcontext *ctx )
  * Scissoring
  */
 
-void radeonScissor(GLcontext* ctx, GLint x, GLint y, GLsizei w, GLsizei h)
+void radeonScissor(struct gl_context* ctx, GLint x, GLint y, GLsizei w, GLsizei h)
 {
 	radeonContextPtr radeon = RADEON_CONTEXT(ctx);
 	if (ctx->Scissor.Enabled) {
@@ -266,25 +207,6 @@ void radeonScissor(GLcontext* ctx, GLint x, GLint y, GLsizei w, GLsizei h)
  * SwapBuffers with client-side throttling
  */
 
-static uint32_t radeonGetLastFrame(radeonContextPtr radeon)
-{
-	drm_radeon_getparam_t gp;
-	int ret;
-	uint32_t frame = 0;
-
-	gp.param = RADEON_PARAM_LAST_FRAME;
-	gp.value = (int *)&frame;
-	ret = drmCommandWriteRead(radeon->dri.fd, DRM_RADEON_GETPARAM,
-				  &gp, sizeof(gp));
-	if (ret) {
-		fprintf(stderr, "%s: drmRadeonGetParam: %d\n", __FUNCTION__,
-			ret);
-		exit(1);
-	}
-
-	return frame;
-}
-
 uint32_t radeonGetAge(radeonContextPtr radeon)
 {
 	drm_radeon_getparam_t gp;
@@ -304,349 +226,12 @@ uint32_t radeonGetAge(radeonContextPtr radeon)
 	return age;
 }
 
-static void radeonEmitIrqLocked(radeonContextPtr radeon)
-{
-	drm_radeon_irq_emit_t ie;
-	int ret;
-
-	ie.irq_seq = &radeon->iw.irq_seq;
-	ret = drmCommandWriteRead(radeon->dri.fd, DRM_RADEON_IRQ_EMIT,
-				  &ie, sizeof(ie));
-	if (ret) {
-		fprintf(stderr, "%s: drmRadeonIrqEmit: %d\n", __FUNCTION__,
-			ret);
-		exit(1);
-	}
-}
-
-static void radeonWaitIrq(radeonContextPtr radeon)
-{
-	int ret;
-
-	do {
-		ret = drmCommandWrite(radeon->dri.fd, DRM_RADEON_IRQ_WAIT,
-				      &radeon->iw, sizeof(radeon->iw));
-	} while (ret && (errno == EINTR || errno == EBUSY));
-
-	if (ret) {
-		fprintf(stderr, "%s: drmRadeonIrqWait: %d\n", __FUNCTION__,
-			ret);
-		exit(1);
-	}
-}
-
-static void radeonWaitForFrameCompletion(radeonContextPtr radeon)
-{
-	drm_radeon_sarea_t *sarea = radeon->sarea;
-
-	if (radeon->do_irqs) {
-		if (radeonGetLastFrame(radeon) < sarea->last_frame) {
-			if (!radeon->irqsEmitted) {
-				while (radeonGetLastFrame(radeon) <
-				       sarea->last_frame) ;
-			} else {
-				UNLOCK_HARDWARE(radeon);
-				radeonWaitIrq(radeon);
-				LOCK_HARDWARE(radeon);
-			}
-			radeon->irqsEmitted = 10;
-		}
-
-		if (radeon->irqsEmitted) {
-			radeonEmitIrqLocked(radeon);
-			radeon->irqsEmitted--;
-		}
-	} else {
-		while (radeonGetLastFrame(radeon) < sarea->last_frame) {
-			UNLOCK_HARDWARE(radeon);
-			if (radeon->do_usleeps)
-				DO_USLEEP(1);
-			LOCK_HARDWARE(radeon);
-		}
-	}
-}
-
-/* wait for idle */
-void radeonWaitForIdleLocked(radeonContextPtr radeon)
-{
-	int ret;
-	int i = 0;
-
-	do {
-		ret = drmCommandNone(radeon->dri.fd, DRM_RADEON_CP_IDLE);
-		if (ret)
-			DO_USLEEP(1);
-	} while (ret && ++i < 100);
-
-	if (ret < 0) {
-		UNLOCK_HARDWARE(radeon);
-		fprintf(stderr, "Error: R300 timed out... exiting\n");
-		exit(-1);
-	}
-}
-
-static void radeonWaitForIdle(radeonContextPtr radeon)
-{
-	if (!radeon->radeonScreen->driScreen->dri2.enabled) {
-        LOCK_HARDWARE(radeon);
-	    radeonWaitForIdleLocked(radeon);
-	    UNLOCK_HARDWARE(radeon);
-    }
-}
-
-static void radeon_flip_renderbuffers(struct radeon_framebuffer *rfb)
-{
-	int current_page = rfb->pf_current_page;
-	int next_page = (current_page + 1) % rfb->pf_num_pages;
-	struct gl_renderbuffer *tmp_rb;
-
-	/* Exchange renderbuffers if necessary but make sure their
-	 * reference counts are preserved.
-	 */
-	if (rfb->color_rb[current_page] &&
-	    rfb->base.Attachment[BUFFER_FRONT_LEFT].Renderbuffer !=
-	    &rfb->color_rb[current_page]->base) {
-		tmp_rb = NULL;
-		_mesa_reference_renderbuffer(&tmp_rb,
-					     rfb->base.Attachment[BUFFER_FRONT_LEFT].Renderbuffer);
-		tmp_rb = &rfb->color_rb[current_page]->base;
-		_mesa_reference_renderbuffer(&rfb->base.Attachment[BUFFER_FRONT_LEFT].Renderbuffer, tmp_rb);
-		_mesa_reference_renderbuffer(&tmp_rb, NULL);
-	}
-
-	if (rfb->color_rb[next_page] &&
-	    rfb->base.Attachment[BUFFER_BACK_LEFT].Renderbuffer !=
-	    &rfb->color_rb[next_page]->base) {
-		tmp_rb = NULL;
-		_mesa_reference_renderbuffer(&tmp_rb,
-					     rfb->base.Attachment[BUFFER_BACK_LEFT].Renderbuffer);
-		tmp_rb = &rfb->color_rb[next_page]->base;
-		_mesa_reference_renderbuffer(&rfb->base.Attachment[BUFFER_BACK_LEFT].Renderbuffer, tmp_rb);
-		_mesa_reference_renderbuffer(&tmp_rb, NULL);
-	}
-}
-
-/* Copy the back color buffer to the front color buffer.
- */
-void radeonCopyBuffer( __DRIdrawablePrivate *dPriv,
-		       const drm_clip_rect_t	  *rect)
-{
-	radeonContextPtr rmesa;
-	struct radeon_framebuffer *rfb;
-	GLint nbox, i, ret;
-
-	assert(dPriv);
-	assert(dPriv->driContextPriv);
-	assert(dPriv->driContextPriv->driverPrivate);
-
-	rmesa = (radeonContextPtr) dPriv->driContextPriv->driverPrivate;
-
-	LOCK_HARDWARE(rmesa);
-
-	rfb = dPriv->driverPrivate;
-
-	if ( RADEON_DEBUG & RADEON_IOCTL ) {
-		fprintf( stderr, "\n%s( %p )\n\n", __FUNCTION__, (void *) rmesa->glCtx );
-	}
-
-	nbox = dPriv->numClipRects; /* must be in locked region */
-
-	for ( i = 0 ; i < nbox ; ) {
-		GLint nr = MIN2( i + RADEON_NR_SAREA_CLIPRECTS , nbox );
-		drm_clip_rect_t *box = dPriv->pClipRects;
-		drm_clip_rect_t *b = rmesa->sarea->boxes;
-		GLint n = 0;
-
-		for ( ; i < nr ; i++ ) {
-
-			*b = box[i];
-
-			if (rect)
-			{
-				if (rect->x1 > b->x1)
-					b->x1 = rect->x1;
-				if (rect->y1 > b->y1)
-					b->y1 = rect->y1;
-				if (rect->x2 < b->x2)
-					b->x2 = rect->x2;
-				if (rect->y2 < b->y2)
-					b->y2 = rect->y2;
-
-				if (b->x1 >= b->x2 || b->y1 >= b->y2)
-					continue;
-			}
-
-			b++;
-			n++;
-		}
-		rmesa->sarea->nbox = n;
-
-		if (!n)
-			continue;
-
-		ret = drmCommandNone( rmesa->dri.fd, DRM_RADEON_SWAP );
-
-		if ( ret ) {
-			fprintf( stderr, "DRM_RADEON_SWAP_BUFFERS: return = %d\n", ret );
-			UNLOCK_HARDWARE( rmesa );
-			exit( 1 );
-		}
-	}
-
-	UNLOCK_HARDWARE( rmesa );
-}
-
-static int radeonScheduleSwap(__DRIdrawablePrivate *dPriv, GLboolean *missed_target)
-{
-	radeonContextPtr rmesa;
-
-	rmesa = (radeonContextPtr) dPriv->driContextPriv->driverPrivate;
-	radeon_firevertices(rmesa);
-
-	LOCK_HARDWARE( rmesa );
-
-	if (!dPriv->numClipRects) {
-		UNLOCK_HARDWARE(rmesa);
-		usleep(10000);	/* throttle invisible client 10ms */
-		return 0;
-	}
-
-	radeonWaitForFrameCompletion(rmesa);
-
-	UNLOCK_HARDWARE(rmesa);
-	driWaitForVBlank(dPriv, missed_target);
-
-	return 0;
-}
-
-static GLboolean radeonPageFlip( __DRIdrawablePrivate *dPriv )
-{
-	radeonContextPtr radeon;
-	GLint ret;
-	__DRIscreenPrivate *psp;
-	struct radeon_renderbuffer *rrb;
-	struct radeon_framebuffer *rfb;
-
-	assert(dPriv);
-	assert(dPriv->driContextPriv);
-	assert(dPriv->driContextPriv->driverPrivate);
-
-	radeon = (radeonContextPtr) dPriv->driContextPriv->driverPrivate;
-	rfb = dPriv->driverPrivate;
-	rrb = (void *)rfb->base.Attachment[BUFFER_FRONT_LEFT].Renderbuffer;
-
-	psp = dPriv->driScreenPriv;
-
-	LOCK_HARDWARE(radeon);
-
-	if ( RADEON_DEBUG & RADEON_IOCTL ) {
-		fprintf(stderr, "%s: pfCurrentPage: %d %d\n", __FUNCTION__,
-			radeon->sarea->pfCurrentPage, radeon->sarea->pfState);
-	}
-	drm_clip_rect_t *box = dPriv->pClipRects;
-	drm_clip_rect_t *b = radeon->sarea->boxes;
-	b[0] = box[0];
-	radeon->sarea->nbox = 1;
-
-	ret = drmCommandNone( radeon->dri.fd, DRM_RADEON_FLIP );
-
-	UNLOCK_HARDWARE(radeon);
-
-	if ( ret ) {
-		fprintf( stderr, "DRM_RADEON_FLIP: return = %d\n", ret );
-		return GL_FALSE;
-	}
-
-	if (!rfb->pf_active)
-		return GL_FALSE;
-
-	rfb->pf_current_page = radeon->sarea->pfCurrentPage;
-	radeon_flip_renderbuffers(rfb);
-	radeon_draw_buffer(radeon->glCtx, &rfb->base);
-
-	return GL_TRUE;
-}
-
-
-/**
- * Swap front and back buffer.
- */
-void radeonSwapBuffers(__DRIdrawablePrivate * dPriv)
-{
-	int64_t ust;
-	__DRIscreenPrivate *psp;
-
-	if (dPriv->driContextPriv && dPriv->driContextPriv->driverPrivate) {
-		radeonContextPtr radeon;
-		GLcontext *ctx;
-
-		radeon = (radeonContextPtr) dPriv->driContextPriv->driverPrivate;
-		ctx = radeon->glCtx;
-
-		if (ctx->Visual.doubleBufferMode) {
-			GLboolean missed_target;
-			struct radeon_framebuffer *rfb = dPriv->driverPrivate;
-			_mesa_notifySwapBuffers(ctx);/* flush pending rendering comands */
-
-			radeonScheduleSwap(dPriv, &missed_target);
-
-			if (rfb->pf_active) {
-				radeonPageFlip(dPriv);
-			} else {
-				radeonCopyBuffer(dPriv, NULL);
-			}
-
-			psp = dPriv->driScreenPriv;
-
-			rfb->swap_count++;
-			(*psp->systemTime->getUST)( & ust );
-			if ( missed_target ) {
-				rfb->swap_missed_count++;
-				rfb->swap_missed_ust = ust - rfb->swap_ust;
-			}
-
-			rfb->swap_ust = ust;
-			radeon->hw.all_dirty = GL_TRUE;
-		}
-	} else {
-		/* XXX this shouldn't be an error but we can't handle it for now */
-		_mesa_problem(NULL, "%s: drawable has no context!",
-			      __FUNCTION__);
-	}
-}
-
-void radeonCopySubBuffer(__DRIdrawablePrivate * dPriv,
-			 int x, int y, int w, int h )
-{
-	if (dPriv->driContextPriv && dPriv->driContextPriv->driverPrivate) {
-		radeonContextPtr radeon;
-		GLcontext *ctx;
-
-		radeon = (radeonContextPtr) dPriv->driContextPriv->driverPrivate;
-		ctx = radeon->glCtx;
-
-		if (ctx->Visual.doubleBufferMode) {
-			drm_clip_rect_t rect;
-			rect.x1 = x + dPriv->x;
-			rect.y1 = (dPriv->h - y - h) + dPriv->y;
-			rect.x2 = rect.x1 + w;
-			rect.y2 = rect.y1 + h;
-			_mesa_notifySwapBuffers(ctx);	/* flush pending rendering comands */
-			radeonCopyBuffer(dPriv, &rect);
-		}
-	} else {
-		/* XXX this shouldn't be an error but we can't handle it for now */
-		_mesa_problem(NULL, "%s: drawable has no context!",
-			      __FUNCTION__);
-	}
-}
-
 /**
  * Check if we're about to draw into the front color buffer.
  * If so, set the intel->front_buffer_dirty field to true.
  */
 void
-radeon_check_front_buffer_rendering(GLcontext *ctx)
+radeon_check_front_buffer_rendering(struct gl_context *ctx)
 {
 	radeonContextPtr radeon = RADEON_CONTEXT(ctx);
 	const struct gl_framebuffer *fb = ctx->DrawBuffer;
@@ -662,7 +247,7 @@ radeon_check_front_buffer_rendering(GLcontext *ctx)
 }
 
 
-void radeon_draw_buffer(GLcontext *ctx, struct gl_framebuffer *fb)
+void radeon_draw_buffer(struct gl_context *ctx, struct gl_framebuffer *fb)
 {
 	radeonContextPtr radeon = RADEON_CONTEXT(ctx);
 	struct radeon_renderbuffer *rrbDepth = NULL, *rrbStencil = NULL,
@@ -708,7 +293,6 @@ void radeon_draw_buffer(GLcontext *ctx, struct gl_framebuffer *fb)
 		if (fb->_ColorDrawBufferIndexes[0] == BUFFER_FRONT_LEFT) {
 			rrbColor = radeon_renderbuffer(fb->Attachment[BUFFER_FRONT_LEFT].Renderbuffer);
 			radeon->front_cliprects = GL_TRUE;
-			radeon->front_buffer_dirty = GL_TRUE;
 		} else {
 			rrbColor = radeon_renderbuffer(fb->Attachment[BUFFER_BACK_LEFT].Renderbuffer);
 			radeon->front_cliprects = GL_FALSE;
@@ -818,7 +402,7 @@ void radeon_draw_buffer(GLcontext *ctx, struct gl_framebuffer *fb)
 /**
  * Called via glDrawBuffer.
  */
-void radeonDrawBuffer( GLcontext *ctx, GLenum mode )
+void radeonDrawBuffer( struct gl_context *ctx, GLenum mode )
 {
 	if (RADEON_DEBUG & RADEON_DRI)
 		fprintf(stderr, "%s %s\n", __FUNCTION__,
@@ -845,7 +429,7 @@ void radeonDrawBuffer( GLcontext *ctx, GLenum mode )
 	radeon_draw_buffer(ctx, ctx->DrawBuffer);
 }
 
-void radeonReadBuffer( GLcontext *ctx, GLenum mode )
+void radeonReadBuffer( struct gl_context *ctx, GLenum mode )
 {
 	if ((ctx->DrawBuffer != NULL) && (ctx->DrawBuffer->Name == 0)) {
 		struct radeon_context *const rmesa = RADEON_CONTEXT(ctx);
@@ -869,40 +453,23 @@ void radeonReadBuffer( GLcontext *ctx, GLenum mode )
 	}
 }
 
-
-/* Turn on/off page flipping according to the flags in the sarea:
- */
-void radeonUpdatePageFlipping(radeonContextPtr radeon)
-{
-	struct radeon_framebuffer *rfb = radeon_get_drawable(radeon)->driverPrivate;
-
-	rfb->pf_active = radeon->sarea->pfState;
-	rfb->pf_current_page = radeon->sarea->pfCurrentPage;
-	rfb->pf_num_pages = 2;
-	radeon_flip_renderbuffers(rfb);
-	radeon_draw_buffer(radeon->glCtx, radeon->glCtx->DrawBuffer);
-}
-
 void radeon_window_moved(radeonContextPtr radeon)
 {
 	/* Cliprects has to be updated before doing anything else */
 	radeonSetCliprects(radeon);
-	if (!radeon->radeonScreen->driScreen->dri2.enabled) {
-		radeonUpdatePageFlipping(radeon);
-	}
 }
 
-void radeon_viewport(GLcontext *ctx, GLint x, GLint y, GLsizei width, GLsizei height)
+void radeon_viewport(struct gl_context *ctx, GLint x, GLint y, GLsizei width, GLsizei height)
 {
 	radeonContextPtr radeon = RADEON_CONTEXT(ctx);
 	__DRIcontext *driContext = radeon->dri.context;
-	void (*old_viewport)(GLcontext *ctx, GLint x, GLint y,
+	void (*old_viewport)(struct gl_context *ctx, GLint x, GLint y,
 			     GLsizei w, GLsizei h);
 
 	if (!driContext->driScreenPriv->dri2.enabled)
 		return;
 
-	if (!radeon->meta.internal_viewport_call && ctx->DrawBuffer->Name == 0) {
+	if (ctx->DrawBuffer->Name == 0) {
 		if (radeon->is_front_buffer_rendering) {
 			ctx->Driver.Flush(ctx);
 		}
@@ -918,34 +485,6 @@ void radeon_viewport(GLcontext *ctx, GLint x, GLint y, GLsizei width, GLsizei he
 	ctx->Driver.Viewport = old_viewport;
 }
 
-static void radeon_print_state_atom_prekmm(radeonContextPtr radeon, struct radeon_state_atom *state)
-{
-	int i, j, reg;
-	int dwords = (*state->check) (radeon->glCtx, state);
-	drm_r300_cmd_header_t cmd;
-
-	fprintf(stderr, "  emit %s %d/%d\n", state->name, dwords, state->cmd_size);
-
-	if (radeon_is_debug_enabled(RADEON_STATE, RADEON_TRACE)) {
-		if (dwords > state->cmd_size)
-			dwords = state->cmd_size;
-
-		for (i = 0; i < dwords;) {
-			cmd = *((drm_r300_cmd_header_t *) &state->cmd[i]);
-			reg = (cmd.packet0.reghi << 8) | cmd.packet0.reglo;
-			fprintf(stderr, "      %s[%d]: cmdpacket0 (first reg=0x%04x, count=%d)\n",
-					state->name, i, reg, cmd.packet0.count);
-			++i;
-			for (j = 0; j < cmd.packet0.count && i < dwords; j++) {
-				fprintf(stderr, "      %s[%d]: 0x%04x = %08x\n",
-						state->name, i, reg, state->cmd[i]);
-				reg += 4;
-				++i;
-			}
-		}
-	}
-}
-
 static void radeon_print_state_atom(radeonContextPtr radeon, struct radeon_state_atom *state)
 {
 	int i, j, reg, count;
@@ -954,16 +493,11 @@ static void radeon_print_state_atom(radeonContextPtr radeon, struct radeon_state
 	if (!radeon_is_debug_enabled(RADEON_STATE, RADEON_VERBOSE) )
 		return;
 
-	if (!radeon->radeonScreen->kernel_mm) {
-		radeon_print_state_atom_prekmm(radeon, state);
-		return;
-	}
-
 	dwords = (*state->check) (radeon->glCtx, state);
 
 	fprintf(stderr, "  emit %s %d/%d\n", state->name, dwords, state->cmd_size);
 
-	if (radeon_is_debug_enabled(RADEON_STATE, RADEON_TRACE)) {
+	if (state->cmd && radeon_is_debug_enabled(RADEON_STATE, RADEON_TRACE)) {
 		if (dwords > state->cmd_size)
 			dwords = state->cmd_size;
 		for (i = 0; i < dwords;) {
@@ -1036,10 +570,11 @@ static INLINE void radeon_emit_atom(radeonContextPtr radeon, struct radeon_state
 			OUT_BATCH_TABLE(atom->cmd, dwords);
 			END_BATCH();
 		}
+		atom->dirty = GL_FALSE;
+
 	} else {
 		radeon_print(RADEON_STATE, RADEON_VERBOSE, "  skip state %s\n", atom->name);
 	}
-	atom->dirty = GL_FALSE;
 
 }
 
@@ -1064,7 +599,7 @@ static INLINE void radeonEmitAtoms(radeonContextPtr radeon, GLboolean emitAll)
 	COMMIT_BATCH();
 }
 
-static GLboolean radeon_revalidate_bos(GLcontext *ctx)
+static GLboolean radeon_revalidate_bos(struct gl_context *ctx)
 {
 	radeonContextPtr radeon = RADEON_CONTEXT(ctx);
 	int ret;
@@ -1104,7 +639,7 @@ void radeonEmitState(radeonContextPtr radeon)
 }
 
 
-void radeonFlush(GLcontext *ctx)
+void radeonFlush(struct gl_context *ctx)
 {
 	radeonContextPtr radeon = RADEON_CONTEXT(ctx);
 	if (RADEON_DEBUG & RADEON_IOCTL)
@@ -1130,18 +665,14 @@ flush_front:
 
 		if (screen->dri2.loader && (screen->dri2.loader->base.version >= 2)
 			&& (screen->dri2.loader->flushFrontBuffer != NULL)) {
-			__DRIdrawablePrivate * drawable = radeon_get_drawable(radeon);
-			(*screen->dri2.loader->flushFrontBuffer)(drawable, drawable->loaderPrivate);
+			__DRIdrawable * drawable = radeon_get_drawable(radeon);
 
-			/* Only clear the dirty bit if front-buffer rendering is no longer
-			 * enabled.  This is done so that the dirty bit can only be set in
-			 * glDrawBuffer.  Otherwise the dirty bit would have to be set at
-			 * each of N places that do rendering.  This has worse performances,
-			 * but it is much easier to get correct.
+			/* We set the dirty bit in radeon_prepare_render() if we're
+			 * front buffer rendering once we get there.
 			 */
-			if (!radeon->is_front_buffer_rendering) {
-				radeon->front_buffer_dirty = GL_FALSE;
-			}
+			radeon->front_buffer_dirty = GL_FALSE;
+
+			(*screen->dri2.loader->flushFrontBuffer)(drawable, drawable->loaderPrivate);
 		}
 	}
 }
@@ -1149,36 +680,25 @@ flush_front:
 /* Make sure all commands have been sent to the hardware and have
  * completed processing.
  */
-void radeonFinish(GLcontext * ctx)
+void radeonFinish(struct gl_context * ctx)
 {
 	radeonContextPtr radeon = RADEON_CONTEXT(ctx);
 	struct gl_framebuffer *fb = ctx->DrawBuffer;
+	struct radeon_renderbuffer *rrb;
 	int i;
 
 	if (ctx->Driver.Flush)
 		ctx->Driver.Flush(ctx); /* +r6/r7 */
 
-	if (radeon->radeonScreen->kernel_mm) {
-		for (i = 0; i < fb->_NumColorDrawBuffers; i++) {
-			struct radeon_renderbuffer *rrb;
-			rrb = radeon_renderbuffer(fb->_ColorDrawBuffers[i]);
-			if (rrb && rrb->bo)
-				radeon_bo_wait(rrb->bo);
-		}
-		{
-			struct radeon_renderbuffer *rrb;
-			rrb = radeon_get_depthbuffer(radeon);
-			if (rrb && rrb->bo)
-				radeon_bo_wait(rrb->bo);
-		}
-	} else if (radeon->do_irqs) {
-		LOCK_HARDWARE(radeon);
-		radeonEmitIrqLocked(radeon);
-		UNLOCK_HARDWARE(radeon);
-		radeonWaitIrq(radeon);
-	} else {
-		radeonWaitForIdle(radeon);
+	for (i = 0; i < fb->_NumColorDrawBuffers; i++) {
+		struct radeon_renderbuffer *rrb;
+		rrb = radeon_renderbuffer(fb->_ColorDrawBuffers[i]);
+		if (rrb && rrb->bo)
+			radeon_bo_wait(rrb->bo);
 	}
+	rrb = radeon_get_depthbuffer(radeon);
+	if (rrb && rrb->bo)
+		radeon_bo_wait(rrb->bo);
 }
 
 /* cmdbuffer */
@@ -1196,8 +716,7 @@ int rcommonFlushCmdBufLocked(radeonContextPtr rmesa, const char *caller)
 	rmesa->cmdbuf.flushing = 1;
 
 	if (RADEON_DEBUG & RADEON_IOCTL) {
-		fprintf(stderr, "%s from %s - %i cliprects\n",
-			__FUNCTION__, caller, rmesa->numClipRects);
+		fprintf(stderr, "%s from %s\n", __FUNCTION__, caller);
 	}
 
 	radeonEmitQueryEnd(rmesa->glCtx);
@@ -1222,15 +741,13 @@ int rcommonFlushCmdBuf(radeonContextPtr rmesa, const char *caller)
 
 	radeonReleaseDmaRegions(rmesa);
 
-	LOCK_HARDWARE(rmesa);
 	ret = rcommonFlushCmdBufLocked(rmesa, caller);
-	UNLOCK_HARDWARE(rmesa);
 
 	if (ret) {
 		fprintf(stderr, "drmRadeonCmdBuffer: %d. Kernel failed to "
 				"parse or rejected command stream. See dmesg "
 				"for more info.\n", ret);
-		_mesa_exit(ret);
+		exit(ret);
 	}
 
 	return ret;
@@ -1257,6 +774,8 @@ GLboolean rcommonEnsureCmdBufSpace(radeonContextPtr rmesa, int dwords, const cha
 void rcommonInitCmdBuf(radeonContextPtr rmesa)
 {
 	GLuint size;
+	struct drm_radeon_gem_info mminfo = { 0 };
+
 	/* Initialize command buffer */
 	size = 256 * driQueryOptioni(&rmesa->optionCache,
 				     "command_buffer_size");
@@ -1274,12 +793,8 @@ void rcommonInitCmdBuf(radeonContextPtr rmesa)
 			"Allocating %d bytes command buffer (max state is %d bytes)\n",
 			size * 4, rmesa->hw.max_state_size * 4);
 
-	if (rmesa->radeonScreen->kernel_mm) {
-		int fd = rmesa->radeonScreen->driScreen->fd;
-		rmesa->cmdbuf.csm = radeon_cs_manager_gem_ctor(fd);
-	} else {
-		rmesa->cmdbuf.csm = radeon_cs_manager_legacy_ctor(rmesa);
-	}
+	rmesa->cmdbuf.csm =
+		radeon_cs_manager_gem_ctor(rmesa->radeonScreen->driScreen->fd);
 	if (rmesa->cmdbuf.csm == NULL) {
 		/* FIXME: fatal error */
 		return;
@@ -1291,31 +806,23 @@ void rcommonInitCmdBuf(radeonContextPtr rmesa)
 	radeon_cs_space_set_flush(rmesa->cmdbuf.cs,
 				  (void (*)(void *))rmesa->glCtx->Driver.Flush, rmesa->glCtx);
 
-	if (!rmesa->radeonScreen->kernel_mm) {
-		radeon_cs_set_limit(rmesa->cmdbuf.cs, RADEON_GEM_DOMAIN_VRAM, rmesa->radeonScreen->texSize[0]);
-		radeon_cs_set_limit(rmesa->cmdbuf.cs, RADEON_GEM_DOMAIN_GTT, rmesa->radeonScreen->gartTextures.size);
-	} else {
-		struct drm_radeon_gem_info mminfo = { 0 };
 
-		if (!drmCommandWriteRead(rmesa->dri.fd, DRM_RADEON_GEM_INFO, &mminfo, sizeof(mminfo)))
-		{
-			radeon_cs_set_limit(rmesa->cmdbuf.cs, RADEON_GEM_DOMAIN_VRAM, mminfo.vram_visible);
-			radeon_cs_set_limit(rmesa->cmdbuf.cs, RADEON_GEM_DOMAIN_GTT, mminfo.gart_size);
-		}
+	if (!drmCommandWriteRead(rmesa->dri.fd, DRM_RADEON_GEM_INFO,
+				 &mminfo, sizeof(mminfo))) {
+		radeon_cs_set_limit(rmesa->cmdbuf.cs, RADEON_GEM_DOMAIN_VRAM,
+				    mminfo.vram_visible);
+		radeon_cs_set_limit(rmesa->cmdbuf.cs, RADEON_GEM_DOMAIN_GTT,
+				    mminfo.gart_size);
 	}
-
 }
+
 /**
  * Destroy the command buffer
  */
 void rcommonDestroyCmdBuf(radeonContextPtr rmesa)
 {
 	radeon_cs_destroy(rmesa->cmdbuf.cs);
-	if (rmesa->radeonScreen->driScreen->dri2.enabled || rmesa->radeonScreen->kernel_mm) {
-		radeon_cs_manager_gem_dtor(rmesa->cmdbuf.csm);
-	} else {
-		radeon_cs_manager_legacy_dtor(rmesa->cmdbuf.csm);
-	}
+	radeon_cs_manager_gem_dtor(rmesa->cmdbuf.csm);
 }
 
 void rcommonBeginBatch(radeonContextPtr rmesa, int n,
@@ -1324,11 +831,6 @@ void rcommonBeginBatch(radeonContextPtr rmesa, int n,
 		       const char *function,
 		       int line)
 {
-	if (!rmesa->cmdbuf.cs->cdw && dostate) {
-		radeon_print(RADEON_STATE, RADEON_NORMAL,
-				"Reemit state after flush (from %s)\n", function);
-		radeonEmitState(rmesa);
-	}
 	radeon_cs_begin(rmesa->cmdbuf.cs, n, file, function, line);
 
     radeon_print(RADEON_CS, RADEON_VERBOSE, "BEGIN_BATCH(%d) at %d, from %s:%i\n",
@@ -1336,7 +838,7 @@ void rcommonBeginBatch(radeonContextPtr rmesa, int n,
 
 }
 
-void radeonUserClear(GLcontext *ctx, GLuint mask)
+void radeonUserClear(struct gl_context *ctx, GLuint mask)
 {
    _mesa_meta_Clear(ctx, mask);
 }