X-Git-Url: https://git.libre-soc.org/?a=blobdiff_plain;f=src%2Fmesa%2Fdrivers%2Fdri%2Fradeon%2Fradeon_ioctl.c;h=c23e9c2d2a287134c405de314d355d59b7a3184f;hb=12d924c5ae14a1c6a05a3dcae29b77e7668e227d;hp=a5e4df794153de72a872865fb8fabc7932d67762;hpb=e87320b5e033a911d4ced2d516e479cdf1bc9228;p=mesa.git

diff --git a/src/mesa/drivers/dri/radeon/radeon_ioctl.c b/src/mesa/drivers/dri/radeon/radeon_ioctl.c
index a5e4df79415..c23e9c2d2a2 100644
--- a/src/mesa/drivers/dri/radeon/radeon_ioctl.c
+++ b/src/mesa/drivers/dri/radeon/radeon_ioctl.c
@@ -38,35 +38,19 @@ WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
 #include <errno.h>
 
 #include "main/attrib.h"
-#include "main/enable.h"
-#include "main/blend.h"
 #include "main/bufferobj.h"
-#include "main/buffers.h"
-#include "main/depth.h"
-#include "main/shaders.h"
-#include "main/texstate.h"
-#include "main/varray.h"
-#include "glapi/dispatch.h"
 #include "swrast/swrast.h"
-#include "main/stencil.h"
-#include "main/matrix.h"
 
 #include "main/glheader.h"
 #include "main/imports.h"
 #include "main/simple_list.h"
-#include "swrast/swrast.h"
 
 #include "radeon_context.h"
 #include "radeon_common.h"
-#include "radeon_state.h"
 #include "radeon_ioctl.h"
-#include "radeon_tcl.h"
-#include "radeon_sanity.h"
 
 #define STANDALONE_MMIO
-#include "radeon_macros.h"  /* for INREG() */
 
-#include "drirenderbuffer.h"
 #include "vblank.h"
 
 #define RADEON_TIMEOUT             512
@@ -107,13 +91,15 @@ void radeonSetUpAtomList( r100ContextPtr rmesa )
       insert_at_tail(&rmesa->radeon.hw.atomlist, &rmesa->hw.lit[i]);
    for (i = 0; i < 6; ++i)
       insert_at_tail(&rmesa->radeon.hw.atomlist, &rmesa->hw.ucp[i]);
+   if (rmesa->radeon.radeonScreen->kernel_mm)
+      insert_at_tail(&rmesa->radeon.hw.atomlist, &rmesa->hw.stp);
    insert_at_tail(&rmesa->radeon.hw.atomlist, &rmesa->hw.eye);
    insert_at_tail(&rmesa->radeon.hw.atomlist, &rmesa->hw.grd);
    insert_at_tail(&rmesa->radeon.hw.atomlist, &rmesa->hw.fog);
    insert_at_tail(&rmesa->radeon.hw.atomlist, &rmesa->hw.glt);
 }
 
-void radeonEmitScissor(r100ContextPtr rmesa)
+static void radeonEmitScissor(r100ContextPtr rmesa)
 {
     BATCH_LOCALS(&rmesa->radeon);
     if (!rmesa->radeon.radeonScreen->kernel_mm) {
@@ -127,8 +113,8 @@ void radeonEmitScissor(r100ContextPtr rmesa)
         OUT_BATCH((rmesa->radeon.state.scissor.rect.y1 << 16) |
                   rmesa->radeon.state.scissor.rect.x1);
         OUT_BATCH(CP_PACKET0(RADEON_RE_WIDTH_HEIGHT, 0));
-        OUT_BATCH(((rmesa->radeon.state.scissor.rect.y2 - 1) << 16) |
-                  (rmesa->radeon.state.scissor.rect.x2 - 1));
+        OUT_BATCH(((rmesa->radeon.state.scissor.rect.y2) << 16) |
+                  (rmesa->radeon.state.scissor.rect.x2));
         END_BATCH();
     } else {
         BEGIN_BATCH(2);
@@ -192,7 +178,7 @@ extern void radeonEmitVbufPrim( r100ContextPtr rmesa,
 #endif
 }
 
-void radeonFlushElts( GLcontext *ctx )
+void radeonFlushElts( struct gl_context *ctx )
 {
    r100ContextPtr rmesa = R100_CONTEXT(ctx);
    BATCH_LOCALS(&rmesa->radeon);
@@ -200,7 +186,7 @@ void radeonFlushElts( GLcontext *ctx )
    uint32_t *cmd = (uint32_t *)(rmesa->radeon.cmdbuf.cs->packets + rmesa->tcl.elt_cmd_start);
    int dwords = (rmesa->radeon.cmdbuf.cs->section_ndw - rmesa->radeon.cmdbuf.cs->section_cdw);
 
-   if (RADEON_DEBUG & DEBUG_IOCTL)
+   if (RADEON_DEBUG & RADEON_IOCTL)
       fprintf(stderr, "%s\n", __FUNCTION__);
 
    assert( rmesa->radeon.dma.flush == radeonFlushElts );
@@ -236,7 +222,7 @@ void radeonFlushElts( GLcontext *ctx )
 
    END_BATCH();
 
-   if (RADEON_DEBUG & DEBUG_SYNC) {
+   if (RADEON_DEBUG & RADEON_SYNC) {
       fprintf(stderr, "%s: Syncing\n", __FUNCTION__);
       radeonFinish( rmesa->radeon.glCtx );
    }
@@ -252,7 +238,7 @@ GLushort *radeonAllocEltsOpenEnded( r100ContextPtr rmesa,
    int align_min_nr;
    BATCH_LOCALS(&rmesa->radeon);
 
-   if (RADEON_DEBUG & DEBUG_IOCTL)
+   if (RADEON_DEBUG & RADEON_IOCTL)
       fprintf(stderr, "%s %d prim %x\n", __FUNCTION__, min_nr, primitive);
 
    assert((primitive & RADEON_CP_VC_CNTL_PRIM_WALK_IND));
@@ -273,7 +259,7 @@ GLushort *radeonAllocEltsOpenEnded( r100ContextPtr rmesa,
    } else {
      OUT_BATCH(rmesa->ioctl.vertex_offset);
    }
-   OUT_BATCH(0xffff);
+   OUT_BATCH(rmesa->ioctl.vertex_max);
    OUT_BATCH(vertex_format);
    OUT_BATCH(primitive |
 	     RADEON_CP_VC_CNTL_PRIM_WALK_IND |
@@ -296,7 +282,7 @@ GLushort *radeonAllocEltsOpenEnded( r100ContextPtr rmesa,
 
    retval = (GLushort *)(rmesa->radeon.cmdbuf.cs->packets + rmesa->tcl.elt_cmd_offset);
 
-   if (RADEON_DEBUG & DEBUG_PRIMS)
+   if (RADEON_DEBUG & RADEON_RENDER)
       fprintf(stderr, "%s: header prim %x \n",
 	      __FUNCTION__, primitive);
 
@@ -318,7 +304,7 @@ void radeonEmitVertexAOS( r100ContextPtr rmesa,
 #else
    BATCH_LOCALS(&rmesa->radeon);
 
-   if (RADEON_DEBUG & (DEBUG_PRIMS|DEBUG_IOCTL))
+   if (RADEON_DEBUG & (RADEON_PRIMS|DEBUG_IOCTL))
       fprintf(stderr, "%s:  vertex_size 0x%x offset 0x%x \n",
 	      __FUNCTION__, vertex_size, offset);
 
@@ -342,6 +328,7 @@ void radeonEmitAOS( r100ContextPtr rmesa,
    rmesa->ioctl.bo = rmesa->radeon.tcl.aos[0].bo;
    rmesa->ioctl.vertex_offset =
      (rmesa->radeon.tcl.aos[0].offset + offset * rmesa->radeon.tcl.aos[0].stride * 4);
+   rmesa->ioctl.vertex_max = rmesa->radeon.tcl.aos[0].count;
 #else
    BATCH_LOCALS(&rmesa->radeon);
    uint32_t voffset;
@@ -349,7 +336,7 @@ void radeonEmitAOS( r100ContextPtr rmesa,
    int sz = 1 + (nr >> 1) * 3 + (nr & 1) * 2;
    int i;
 
-   if (RADEON_DEBUG & DEBUG_IOCTL)
+   if (RADEON_DEBUG & RADEON_IOCTL)
       fprintf(stderr, "%s\n", __FUNCTION__);
 
    BEGIN_BATCH(sz+2+(nr * 2));
@@ -445,15 +432,17 @@ void radeonEmitAOS( r100ContextPtr rmesa,
  */
 #define RADEON_MAX_CLEARS	256
 
-static void radeonKernelClear(GLcontext *ctx, GLuint flags)
+static void radeonKernelClear(struct gl_context *ctx, GLuint flags)
 {
      r100ContextPtr rmesa = R100_CONTEXT(ctx);
-   __DRIdrawablePrivate *dPriv = radeon_get_drawable(&rmesa->radeon);
+   __DRIdrawable *dPriv = radeon_get_drawable(&rmesa->radeon);
    drm_radeon_sarea_t *sarea = rmesa->radeon.sarea;
    uint32_t clear;
    GLint ret, i;
    GLint cx, cy, cw, ch;
 
+   radeonEmitState(&rmesa->radeon);
+
    LOCK_HARDWARE( &rmesa->radeon );
 
    /* compute region after locking: */
@@ -566,15 +555,18 @@ static void radeonKernelClear(GLcontext *ctx, GLuint flags)
    UNLOCK_HARDWARE( &rmesa->radeon );
 }
 
-static void radeonClear( GLcontext *ctx, GLbitfield mask )
+static void radeonClear( struct gl_context *ctx, GLbitfield mask )
 {
    r100ContextPtr rmesa = R100_CONTEXT(ctx);
-   __DRIdrawablePrivate *dPriv = radeon_get_drawable(&rmesa->radeon);
+   __DRIdrawable *dPriv = radeon_get_drawable(&rmesa->radeon);
    GLuint flags = 0;
-   GLuint color_mask = 0;
    GLuint orig_mask = mask;
 
-   if ( RADEON_DEBUG & DEBUG_IOCTL ) {
+   if (mask & (BUFFER_BIT_FRONT_LEFT | BUFFER_BIT_FRONT_RIGHT)) {
+      rmesa->radeon.front_buffer_dirty = GL_TRUE;
+   }
+
+   if ( RADEON_DEBUG & RADEON_IOCTL ) {
       fprintf( stderr, "radeonClear\n");
    }
 
@@ -589,13 +581,11 @@ static void radeonClear( GLcontext *ctx, GLbitfield mask )
 
    if ( mask & BUFFER_BIT_FRONT_LEFT ) {
       flags |= RADEON_FRONT;
-      color_mask = rmesa->hw.msk.cmd[MSK_RB3D_PLANEMASK];
       mask &= ~BUFFER_BIT_FRONT_LEFT;
    }
 
    if ( mask & BUFFER_BIT_BACK_LEFT ) {
       flags |= RADEON_BACK;
-      color_mask = rmesa->hw.msk.cmd[MSK_RB3D_PLANEMASK];
       mask &= ~BUFFER_BIT_BACK_LEFT;
    }
 
@@ -610,7 +600,7 @@ static void radeonClear( GLcontext *ctx, GLbitfield mask )
    }
 
    if ( mask ) {
-      if (RADEON_DEBUG & DEBUG_FALLBACKS)
+      if (RADEON_DEBUG & RADEON_FALLBACKS)
 	 fprintf(stderr, "%s: swrast clear, mask: %x\n", __FUNCTION__, mask);
       _swrast_Clear( ctx, mask );
    }
@@ -636,7 +626,7 @@ static void radeonClear( GLcontext *ctx, GLbitfield mask )
    }
 }
 
-void radeonInitIoctlFuncs( GLcontext *ctx )
+void radeonInitIoctlFuncs( struct gl_context *ctx )
 {
     ctx->Driver.Clear = radeonClear;
     ctx->Driver.Finish = radeonFinish;