X-Git-Url: https://git.libre-soc.org/?a=blobdiff_plain;f=src%2Fmesa%2Fdrivers%2Fdri%2Fradeon%2Fradeon_mipmap_tree.c;h=979739d62bef74bef31f5c887f13202c00d7cbf8;hb=e190e8cef2eaeabc16dda0cbd56addcd81968834;hp=a1a523931fb1136e844668961141b17bb904a2ed;hpb=bee9964b29b2428ee75e2d1efc0e1d2c2518a417;p=mesa.git diff --git a/src/mesa/drivers/dri/radeon/radeon_mipmap_tree.c b/src/mesa/drivers/dri/radeon/radeon_mipmap_tree.c index a1a523931fb..979739d62be 100644 --- a/src/mesa/drivers/dri/radeon/radeon_mipmap_tree.c +++ b/src/mesa/drivers/dri/radeon/radeon_mipmap_tree.c @@ -31,54 +31,89 @@ #include #include -#include "main/simple_list.h" -#include "main/texcompress.h" #include "main/teximage.h" #include "main/texobj.h" +#include "main/enums.h" #include "radeon_texture.h" +#include "radeon_tile.h" static unsigned get_aligned_compressed_row_stride( - gl_format format, + mesa_format format, unsigned width, unsigned minStride) { - const unsigned blockSize = _mesa_get_format_bytes(format); - unsigned blockWidth, blockHeight, numXBlocks; + const unsigned blockBytes = _mesa_get_format_bytes(format); + unsigned blockWidth, blockHeight; + unsigned stride; _mesa_get_format_block_size(format, &blockWidth, &blockHeight); - numXBlocks = (width + blockWidth - 1) / blockWidth; - - while (numXBlocks * blockSize < minStride) - { - ++numXBlocks; - } - return numXBlocks * blockSize; + /* Count number of blocks required to store the given width. + * And then multiple it with bytes required to store a block. + */ + stride = (width + blockWidth - 1) / blockWidth * blockBytes; + + /* Round the given minimum stride to the next full blocksize. + * (minStride + blockBytes - 1) / blockBytes * blockBytes + */ + if ( stride < minStride ) + stride = (minStride + blockBytes - 1) / blockBytes * blockBytes; + + radeon_print(RADEON_TEXTURE, RADEON_TRACE, + "%s width %u, minStride %u, block(bytes %u, width %u):" + "stride %u\n", + __func__, width, minStride, + blockBytes, blockWidth, + stride); + + return stride; } -static unsigned get_compressed_image_size( - gl_format format, +unsigned get_texture_image_size( + mesa_format format, unsigned rowStride, - unsigned height) + unsigned height, + unsigned depth, + unsigned tiling) { - unsigned blockWidth, blockHeight; + if (_mesa_is_format_compressed(format)) { + unsigned blockWidth, blockHeight; - _mesa_get_format_block_size(format, &blockWidth, &blockHeight); + _mesa_get_format_block_size(format, &blockWidth, &blockHeight); + + return rowStride * ((height + blockHeight - 1) / blockHeight) * depth; + } else if (tiling) { + /* Need to align height to tile height */ + unsigned tileWidth, tileHeight; + + get_tile_size(format, &tileWidth, &tileHeight); + tileHeight--; + + height = (height + tileHeight) & ~tileHeight; + } - return rowStride * ((height + blockHeight - 1) / blockHeight); + return rowStride * height * depth; } -static int find_next_power_of_two(GLuint value) +unsigned get_texture_image_row_stride(radeonContextPtr rmesa, mesa_format format, unsigned width, unsigned tiling, GLuint target) { - int i, tmp; + if (_mesa_is_format_compressed(format)) { + return get_aligned_compressed_row_stride(format, width, rmesa->texture_compressed_row_align); + } else { + unsigned row_align; + + if (!util_is_power_of_two_or_zero(width) || target == GL_TEXTURE_RECTANGLE) { + row_align = rmesa->texture_rect_row_align - 1; + } else if (tiling) { + unsigned tileWidth, tileHeight; + get_tile_size(format, &tileWidth, &tileHeight); + row_align = tileWidth * _mesa_get_format_bytes(format) - 1; + } else { + row_align = rmesa->texture_row_align - 1; + } - i = 0; - tmp = value - 1; - while (tmp) { - tmp >>= 1; - i++; + return (_mesa_format_row_stride(format, width) + row_align) & ~row_align; } - return (1 << i); } /** @@ -92,57 +127,30 @@ static void compute_tex_image_offset(radeonContextPtr rmesa, radeon_mipmap_tree GLuint face, GLuint level, GLuint* curOffset) { radeon_mipmap_level *lvl = &mt->levels[level]; - uint32_t row_align; GLuint height; - height = find_next_power_of_two(lvl->height); - - /* Find image size in bytes */ - if (_mesa_is_format_compressed(mt->mesaFormat)) { - lvl->rowstride = get_aligned_compressed_row_stride(mt->mesaFormat, lvl->width, rmesa->texture_compressed_row_align); - lvl->size = get_compressed_image_size(mt->mesaFormat, lvl->rowstride, height); - } else if (mt->target == GL_TEXTURE_RECTANGLE_NV) { - row_align = rmesa->texture_rect_row_align - 1; - lvl->rowstride = (_mesa_format_row_stride(mt->mesaFormat, lvl->width) + row_align) & ~row_align; - lvl->size = lvl->rowstride * height; - } else if (mt->tilebits & RADEON_TXO_MICRO_TILE) { - /* tile pattern is 16 bytes x2. mipmaps stay 32 byte aligned, - * though the actual offset may be different (if texture is less than - * 32 bytes width) to the untiled case */ - lvl->rowstride = (_mesa_format_row_stride(mt->mesaFormat, lvl->width) * 2 + 31) & ~31; - lvl->size = lvl->rowstride * ((height + 1) / 2) * lvl->depth; - } else { - row_align = rmesa->texture_row_align - 1; - lvl->rowstride = (_mesa_format_row_stride(mt->mesaFormat, lvl->width) + row_align) & ~row_align; - lvl->size = lvl->rowstride * height * lvl->depth; - } + height = util_next_power_of_two(lvl->height); + + lvl->rowstride = get_texture_image_row_stride(rmesa, mt->mesaFormat, lvl->width, mt->tilebits, mt->target); + lvl->size = get_texture_image_size(mt->mesaFormat, lvl->rowstride, height, lvl->depth, mt->tilebits); + assert(lvl->size > 0); - /* All images are aligned to a 32-byte offset */ - *curOffset = (*curOffset + 0x1f) & ~0x1f; lvl->faces[face].offset = *curOffset; *curOffset += lvl->size; - if (RADEON_DEBUG & RADEON_TEXTURE) - fprintf(stderr, - "level %d, face %d: rs:%d %dx%d at %d\n", - level, face, lvl->rowstride, lvl->width, height, lvl->faces[face].offset); + radeon_print(RADEON_TEXTURE, RADEON_TRACE, + "%s(%p) level %d, face %d: rs:%d %dx%d at %d\n", + __func__, rmesa, + level, face, + lvl->rowstride, lvl->width, height, lvl->faces[face].offset); } -static GLuint minify(GLuint size, GLuint levels) -{ - size = size >> levels; - if (size < 1) - size = 1; - return size; -} - - -static void calculate_miptree_layout_r100(radeonContextPtr rmesa, radeon_mipmap_tree *mt) +static void calculate_miptree_layout(radeonContextPtr rmesa, radeon_mipmap_tree *mt) { GLuint curOffset, i, face, level; - assert(mt->numLevels <= rmesa->glCtx->Const.MaxTextureLevels); + assert(1 << (mt->numLevels - 1) <= rmesa->glCtx.Const.MaxTextureSize); curOffset = 0; for(face = 0; face < mt->faces; face++) { @@ -158,50 +166,29 @@ static void calculate_miptree_layout_r100(radeonContextPtr rmesa, radeon_mipmap_ /* Note the required size in memory */ mt->totalsize = (curOffset + RADEON_OFFSET_MASK) & ~RADEON_OFFSET_MASK; -} - -static void calculate_miptree_layout_r300(radeonContextPtr rmesa, radeon_mipmap_tree *mt) -{ - GLuint curOffset, i, level; - - assert(mt->numLevels <= rmesa->glCtx->Const.MaxTextureLevels); - curOffset = 0; - for(i = 0, level = mt->baseLevel; i < mt->numLevels; i++, level++) { - GLuint face; - - mt->levels[level].valid = 1; - mt->levels[level].width = minify(mt->width0, i); - mt->levels[level].height = minify(mt->height0, i); - mt->levels[level].depth = minify(mt->depth0, i); - - for(face = 0; face < mt->faces; face++) - compute_tex_image_offset(rmesa, mt, face, level, &curOffset); - /* r600 cube levels seems to be aligned to 8 faces but - * we have separate register for 1'st level offset so add - * 2 image alignment after 1'st mip level */ - if(rmesa->radeonScreen->chip_family >= CHIP_FAMILY_R600 && - mt->target == GL_TEXTURE_CUBE_MAP && level >= 1) - curOffset += 2 * mt->levels[level].size; - } - - /* Note the required size in memory */ - mt->totalsize = (curOffset + RADEON_OFFSET_MASK) & ~RADEON_OFFSET_MASK; + radeon_print(RADEON_TEXTURE, RADEON_TRACE, + "%s(%p, %p) total size %d\n", + __func__, rmesa, mt, mt->totalsize); } /** * Create a new mipmap tree, calculate its layout and allocate memory. */ -static radeon_mipmap_tree* radeon_miptree_create(radeonContextPtr rmesa, - GLenum target, gl_format mesaFormat, GLuint baseLevel, GLuint numLevels, - GLuint width0, GLuint height0, GLuint depth0, GLuint tilebits) +radeon_mipmap_tree* radeon_miptree_create(radeonContextPtr rmesa, + GLenum target, mesa_format mesaFormat, GLuint baseLevel, GLuint numLevels, + GLuint width0, GLuint height0, GLuint depth0, GLuint tilebits) { radeon_mipmap_tree *mt = CALLOC_STRUCT(_radeon_mipmap_tree); + radeon_print(RADEON_TEXTURE, RADEON_NORMAL, + "%s(%p) new tree is %p.\n", + __func__, rmesa, mt); + mt->mesaFormat = mesaFormat; mt->refcount = 1; mt->target = target; - mt->faces = (target == GL_TEXTURE_CUBE_MAP) ? 6 : 1; + mt->faces = _mesa_num_tex_faces(target); mt->baseLevel = baseLevel; mt->numLevels = numLevels; mt->width0 = width0; @@ -209,10 +196,7 @@ static radeon_mipmap_tree* radeon_miptree_create(radeonContextPtr rmesa, mt->depth0 = depth0; mt->tilebits = tilebits; - if (rmesa->radeonScreen->chip_family >= CHIP_FAMILY_R300) - calculate_miptree_layout_r300(rmesa, mt); - else - calculate_miptree_layout_r100(rmesa, mt); + calculate_miptree_layout(rmesa, mt); mt->bo = radeon_bo_open(rmesa->radeonScreen->bom, 0, mt->totalsize, 1024, @@ -255,7 +239,7 @@ void radeon_miptree_unreference(radeon_mipmap_tree **ptr) * @param[out] pminLod minimal LOD * @param[out] pmaxLod maximal LOD */ -static void calculate_min_max_lod(struct gl_texture_object *tObj, +static void calculate_min_max_lod(struct gl_sampler_object *samp, struct gl_texture_object *tObj, unsigned *pminLod, unsigned *pmaxLod) { int minLod, maxLod; @@ -266,17 +250,17 @@ static void calculate_min_max_lod(struct gl_texture_object *tObj, case GL_TEXTURE_2D: case GL_TEXTURE_3D: case GL_TEXTURE_CUBE_MAP: - if (tObj->MinFilter == GL_NEAREST || tObj->MinFilter == GL_LINEAR) { + if (samp->MinFilter == GL_NEAREST || samp->MinFilter == GL_LINEAR) { /* GL_NEAREST and GL_LINEAR only care about GL_TEXTURE_BASE_LEVEL. */ minLod = maxLod = tObj->BaseLevel; } else { - minLod = tObj->BaseLevel + (GLint)(tObj->MinLod); + minLod = tObj->BaseLevel + (GLint)(samp->MinLod); minLod = MAX2(minLod, tObj->BaseLevel); minLod = MIN2(minLod, tObj->MaxLevel); - maxLod = tObj->BaseLevel + (GLint)(tObj->MaxLod + 0.5); + maxLod = tObj->BaseLevel + (GLint)(samp->MaxLod + 0.5); maxLod = MIN2(maxLod, tObj->MaxLevel); - maxLod = MIN2(maxLod, tObj->Image[0][minLod]->MaxLog2 + minLod); + maxLod = MIN2(maxLod, tObj->Image[0][minLod]->MaxNumLevels - 1 + minLod); maxLod = MAX2(maxLod, minLod); /* need at least one level */ } break; @@ -288,6 +272,12 @@ static void calculate_min_max_lod(struct gl_texture_object *tObj, return; } + radeon_print(RADEON_TEXTURE, RADEON_TRACE, + "%s(%p) target %s, min %d, max %d.\n", + __func__, tObj, + _mesa_enum_to_string(tObj->Target), + minLod, maxLod); + /* save these values */ *pminLod = minLod; *pmaxLod = maxLod; @@ -298,13 +288,10 @@ static void calculate_min_max_lod(struct gl_texture_object *tObj, * given face and level. */ GLboolean radeon_miptree_matches_image(radeon_mipmap_tree *mt, - struct gl_texture_image *texImage, GLuint face, GLuint level) + struct gl_texture_image *texImage) { radeon_mipmap_level *lvl; - - if (face >= mt->faces) - return GL_FALSE; - + GLuint level = texImage->Level; if (texImage->TexFormat != mt->mesaFormat) return GL_FALSE; @@ -332,9 +319,9 @@ static GLboolean radeon_miptree_matches_texture(radeon_mipmap_tree *mt, struct g mtBaseLevel = &mt->levels[texObj->BaseLevel - mt->baseLevel]; firstImage = texObj->Image[0][texObj->BaseLevel]; - numLevels = MIN2(texObj->MaxLevel - texObj->BaseLevel + 1, firstImage->MaxLog2 + 1); + numLevels = MIN2(texObj->_MaxLevel - texObj->BaseLevel + 1, firstImage->MaxNumLevels); - if (RADEON_DEBUG & RADEON_TEXTURE) { + if (radeon_is_debug_enabled(RADEON_TEXTURE,RADEON_TRACE)) { fprintf(stderr, "Checking if miptree %p matches texObj %p\n", mt, texObj); fprintf(stderr, "target %d vs %d\n", mt->target, texObj->Target); fprintf(stderr, "format %d vs %d\n", mt->mesaFormat, firstImage->TexFormat); @@ -372,13 +359,16 @@ void radeon_try_alloc_miptree(radeonContextPtr rmesa, radeonTexObj *t) struct gl_texture_object *texObj = &t->base; struct gl_texture_image *texImg = texObj->Image[0][texObj->BaseLevel]; GLuint numLevels; - assert(!t->mt); - if (!texImg) + if (!texImg) { + radeon_warning("%s(%p) No image in given texture object(%p).\n", + __func__, rmesa, t); return; + } + - numLevels = MIN2(texObj->MaxLevel - texObj->BaseLevel + 1, texImg->MaxLog2 + 1); + numLevels = MIN2(texObj->MaxLevel - texObj->BaseLevel + 1, texImg->MaxNumLevels); t->mt = radeon_miptree_create(rmesa, t->base.Target, texImg->TexFormat, texObj->BaseLevel, @@ -408,9 +398,13 @@ static void migrate_image_to_miptree(radeon_mipmap_tree *mt, assert(image->mt != mt); assert(dstlvl->valid); - assert(dstlvl->width == image->base.Width); - assert(dstlvl->height == image->base.Height); - assert(dstlvl->depth == image->base.Depth); + assert(dstlvl->width == image->base.Base.Width); + assert(dstlvl->height == image->base.Base.Height); + assert(dstlvl->depth == image->base.Base.Depth); + + radeon_print(RADEON_TEXTURE, RADEON_VERBOSE, + "%s miptree %p, image %p, face %d, level %d.\n", + __func__, mt, image, face, level); radeon_bo_map(mt->bo, GL_TRUE); dest = mt->bo->ptr + dstlvl->faces[face].offset; @@ -420,16 +414,13 @@ static void migrate_image_to_miptree(radeon_mipmap_tree *mt, * In fact, that memcpy() could be done by the hardware in many * cases, provided that we have a proper memory manager. */ - assert(mt->mesaFormat == image->base.TexFormat); + assert(mt->mesaFormat == image->base.Base.TexFormat); - radeon_mipmap_level *srclvl = &image->mt->levels[image->mtlevel]; + radeon_mipmap_level *srclvl = &image->mt->levels[image->base.Base.Level]; - /* TODO: bring back these assertions once the FBOs are fixed */ -#if 0 - assert(image->mtlevel == level); + assert(image->base.Base.Level == level); assert(srclvl->size == dstlvl->size); assert(srclvl->rowstride == dstlvl->rowstride); -#endif radeon_bo_map(image->mt->bo, GL_FALSE); @@ -439,31 +430,11 @@ static void migrate_image_to_miptree(radeon_mipmap_tree *mt, radeon_bo_unmap(image->mt->bo); radeon_miptree_unreference(&image->mt); - } else if (image->base.Data) { - /* This condition should be removed, it's here to workaround - * a segfault when mapping textures during software fallbacks. - */ - const uint32_t srcrowstride = _mesa_format_row_stride(image->base.TexFormat, image->base.Width); - uint32_t rows = image->base.Height * image->base.Depth; - - if (_mesa_is_format_compressed(image->base.TexFormat)) { - uint32_t blockWidth, blockHeight; - _mesa_get_format_block_size(image->base.TexFormat, &blockWidth, &blockHeight); - rows = (rows + blockHeight - 1) / blockHeight; - } - - copy_rows(dest, dstlvl->rowstride, image->base.Data, srcrowstride, - rows, srcrowstride); - - _mesa_free_texmemory(image->base.Data); - image->base.Data = 0; } radeon_bo_unmap(mt->bo); radeon_miptree_reference(mt, &image->mt); - image->mtface = face; - image->mtlevel = level; } /** @@ -482,8 +453,10 @@ static radeon_mipmap_tree * get_biggest_matching_miptree(radeonTexObj *texObj, unsigned mtCount = 0; unsigned maxMtIndex = 0; radeon_mipmap_tree *tmp; + unsigned int level; + int i; - for (unsigned level = firstLevel; level <= lastLevel; ++level) { + for (level = firstLevel; level <= lastLevel; ++level) { radeon_texture_image *img = get_radeon_texture_image(texObj->base.Image[0][level]); unsigned found = 0; // TODO: why this hack?? @@ -493,26 +466,28 @@ static radeon_mipmap_tree * get_biggest_matching_miptree(radeonTexObj *texObj, if (!img->mt) continue; - for (int i = 0; i < mtCount; ++i) { + for (i = 0; i < mtCount; ++i) { if (mts[i] == img->mt) { found = 1; - mtSizes[i] += img->mt->levels[img->mtlevel].size; + mtSizes[i] += img->mt->levels[img->base.Base.Level].size; break; } } if (!found && radeon_miptree_matches_texture(img->mt, &texObj->base)) { - mtSizes[mtCount] = img->mt->levels[img->mtlevel].size; + mtSizes[mtCount] = img->mt->levels[img->base.Base.Level].size; mts[mtCount] = img->mt; mtCount++; } } if (mtCount == 0) { + free(mtSizes); + free(mts); return NULL; } - for (int i = 1; i < mtCount; ++i) { + for (i = 1; i < mtCount; ++i) { if (mtSizes[i] > mtSizes[maxMtIndex]) { maxMtIndex = i; } @@ -530,44 +505,40 @@ static radeon_mipmap_tree * get_biggest_matching_miptree(radeonTexObj *texObj, * If individual images are stored in different mipmap trees * use the mipmap tree that has the most of the correct data. */ -int radeon_validate_texture_miptree(GLcontext * ctx, struct gl_texture_object *texObj) +int radeon_validate_texture_miptree(struct gl_context * ctx, + struct gl_sampler_object *samp, + struct gl_texture_object *texObj) { radeonContextPtr rmesa = RADEON_CONTEXT(ctx); radeonTexObj *t = radeon_tex_obj(texObj); + radeon_mipmap_tree *dst_miptree; - if (t->validated || t->image_override) { + if (samp == &texObj->Sampler && (t->validated || t->image_override)) { return GL_TRUE; } - if (texObj->Image[0][texObj->BaseLevel]->Border > 0) - return GL_FALSE; - - _mesa_test_texobj_completeness(rmesa->glCtx, texObj); - if (!texObj->_Complete) { - return GL_FALSE; - } - - calculate_min_max_lod(&t->base, &t->minLod, &t->maxLod); + calculate_min_max_lod(samp, &t->base, &t->minLod, &t->maxLod); - if (RADEON_DEBUG & RADEON_TEXTURE) - fprintf(stderr, "%s: Validating texture %p now, minLod = %d, maxLod = %d\n", - __FUNCTION__, texObj ,t->minLod, t->maxLod); + radeon_print(RADEON_TEXTURE, RADEON_NORMAL, + "%s: Validating texture %p now, minLod = %d, maxLod = %d\n", + __func__, texObj ,t->minLod, t->maxLod); - radeon_mipmap_tree *dst_miptree; - dst_miptree = get_biggest_matching_miptree(t, t->minLod, t->maxLod); + dst_miptree = get_biggest_matching_miptree(t, t->base.BaseLevel, t->base._MaxLevel); + radeon_miptree_unreference(&t->mt); if (!dst_miptree) { - radeon_miptree_unreference(&t->mt); radeon_try_alloc_miptree(rmesa, t); - dst_miptree = t->mt; - if (RADEON_DEBUG & RADEON_TEXTURE) { - fprintf(stderr, "%s: No matching miptree found, allocated new one %p\n", __FUNCTION__, t->mt); - } - } else if (RADEON_DEBUG & RADEON_TEXTURE) { - fprintf(stderr, "%s: Using miptree %p\n", __FUNCTION__, t->mt); + radeon_print(RADEON_TEXTURE, RADEON_NORMAL, + "%s: No matching miptree found, allocated new one %p\n", + __func__, t->mt); + + } else { + radeon_miptree_reference(dst_miptree, &t->mt); + radeon_print(RADEON_TEXTURE, RADEON_NORMAL, + "%s: Using miptree %p\n", __func__, t->mt); } - const unsigned faces = texObj->Target == GL_TEXTURE_CUBE_MAP ? 6 : 1; + const unsigned faces = _mesa_num_tex_faces(texObj->Target); unsigned face, level; radeon_texture_image *img; /* Validate only the levels that will actually be used during rendering */ @@ -575,22 +546,21 @@ int radeon_validate_texture_miptree(GLcontext * ctx, struct gl_texture_object *t for (level = t->minLod; level <= t->maxLod; ++level) { img = get_radeon_texture_image(texObj->Image[face][level]); - if (RADEON_DEBUG & RADEON_TEXTURE) { - fprintf(stderr, "Checking image level %d, face %d, mt %p ... ", level, face, img->mt); - } + radeon_print(RADEON_TEXTURE, RADEON_TRACE, + "Checking image level %d, face %d, mt %p ... ", + level, face, img->mt); - if (img->mt != dst_miptree) { - if (RADEON_DEBUG & RADEON_TEXTURE) { - fprintf(stderr, "MIGRATING\n"); - } + if (img->mt != t->mt && !img->used_as_render_target) { + radeon_print(RADEON_TEXTURE, RADEON_TRACE, + "MIGRATING\n"); + struct radeon_bo *src_bo = (img->mt) ? img->mt->bo : img->bo; if (src_bo && radeon_bo_is_referenced_by_cs(src_bo, rmesa->cmdbuf.cs)) { radeon_firevertices(rmesa); } - migrate_image_to_miptree(dst_miptree, img, face, level); - } else if (RADEON_DEBUG & RADEON_TEXTURE) { - fprintf(stderr, "OK\n"); - } + migrate_image_to_miptree(t->mt, img, face, level); + } else + radeon_print(RADEON_TEXTURE, RADEON_TRACE, "OK\n"); } }