X-Git-Url: https://git.libre-soc.org/?a=blobdiff_plain;f=src%2Fmesa%2Fdrivers%2Fdri%2Fradeon%2Fradeon_screen.c;h=2ea77e56c7ead5bef0f1aab0c35b2ed6372906e2;hb=222d2f2ac2c7d93cbc0643082c78278ad2c8cfce;hp=6415ec1239c708f6768c34d8c94c73d9cebdbc68;hpb=3ce4375912c8ea488460e593e07c5bb15b92dca9;p=mesa.git diff --git a/src/mesa/drivers/dri/radeon/radeon_screen.c b/src/mesa/drivers/dri/radeon/radeon_screen.c index 6415ec1239c..2ea77e56c7e 100644 --- a/src/mesa/drivers/dri/radeon/radeon_screen.c +++ b/src/mesa/drivers/dri/radeon/radeon_screen.c @@ -52,7 +52,6 @@ WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. #include "radeon_tex.h" #elif defined(RADEON_R200) #include "r200_context.h" -#include "r200_ioctl.h" #include "r200_tex.h" #elif defined(RADEON_R300) #include "r300_context.h" @@ -214,6 +213,10 @@ static const GLuint __driNConfigOptions = 17; static int getSwapInfo( __DRIdrawable *dPriv, __DRIswapInfo * sInfo ); +#ifndef RADEON_INFO_TILE_CONFIG +#define RADEON_INFO_TILE_CONFIG 0x6 +#endif + static int radeonGetParam(__DRIscreen *sPriv, int param, void *value) { @@ -233,6 +236,9 @@ radeonGetParam(__DRIscreen *sPriv, int param, void *value) case RADEON_PARAM_NUM_Z_PIPES: info.request = RADEON_INFO_NUM_Z_PIPES; break; + case RADEON_INFO_TILE_CONFIG: + info.request = RADEON_INFO_TILE_CONFIG; + break; default: return -EINVAL; } @@ -338,12 +344,6 @@ static const __DRItexBufferExtension radeonTexBufferExtension = { #endif #if defined(RADEON_R200) -static const __DRIallocateExtension r200AllocateExtension = { - { __DRI_ALLOCATE, __DRI_ALLOCATE_VERSION }, - r200AllocateMemoryMESA, - r200FreeMemoryMESA, - r200GetMemoryOffsetMESA -}; static const __DRItexOffsetExtension r200texOffsetExtension = { { __DRI_TEX_OFFSET, __DRI_TEX_OFFSET_VERSION }, @@ -383,6 +383,21 @@ static const __DRItexBufferExtension r600TexBufferExtension = { }; #endif +static void +radeonDRI2Flush(__DRIdrawable *drawable) +{ + radeonContextPtr rmesa; + + rmesa = (radeonContextPtr) drawable->driContextPriv->driverPrivate; + radeonFlush(rmesa->glCtx); +} + +static const struct __DRI2flushExtensionRec radeonFlushExtension = { + { __DRI2_FLUSH, __DRI2_FLUSH_VERSION }, + radeonDRI2Flush, + dri2InvalidateDrawable, +}; + static int radeon_set_screen_flags(radeonScreenPtr screen, int device_id) { screen->device_id = device_id; @@ -516,6 +531,7 @@ static int radeon_set_screen_flags(radeonScreenPtr screen, int device_id) case PCI_CHIP_RV380_3150: case PCI_CHIP_RV380_3152: case PCI_CHIP_RV380_3154: + case PCI_CHIP_RV380_3155: case PCI_CHIP_RV380_3E50: case PCI_CHIP_RV380_3E54: screen->chip_family = CHIP_FAMILY_RV380; @@ -846,6 +862,7 @@ static int radeon_set_screen_flags(radeonScreenPtr screen, int device_id) case PCI_CHIP_RV770_9456: case PCI_CHIP_RV770_945A: case PCI_CHIP_RV770_945B: + case PCI_CHIP_RV770_945E: case PCI_CHIP_RV790_9460: case PCI_CHIP_RV790_9462: case PCI_CHIP_RV770_946A: @@ -860,6 +877,7 @@ static int radeon_set_screen_flags(radeonScreenPtr screen, int device_id) case PCI_CHIP_RV730_9487: case PCI_CHIP_RV730_9488: case PCI_CHIP_RV730_9489: + case PCI_CHIP_RV730_948A: case PCI_CHIP_RV730_948F: case PCI_CHIP_RV730_9490: case PCI_CHIP_RV730_9491: @@ -881,6 +899,7 @@ static int radeon_set_screen_flags(radeonScreenPtr screen, int device_id) case PCI_CHIP_RV710_9553: case PCI_CHIP_RV710_9555: case PCI_CHIP_RV710_9557: + case PCI_CHIP_RV710_955F: screen->chip_family = CHIP_FAMILY_RV710; screen->chip_flags = RADEON_CHIPSET_TCL; break; @@ -897,6 +916,61 @@ static int radeon_set_screen_flags(radeonScreenPtr screen, int device_id) screen->chip_flags = RADEON_CHIPSET_TCL; break; + case PCI_CHIP_CEDAR_68E0: + case PCI_CHIP_CEDAR_68E1: + case PCI_CHIP_CEDAR_68E4: + case PCI_CHIP_CEDAR_68E5: + case PCI_CHIP_CEDAR_68E8: + case PCI_CHIP_CEDAR_68E9: + case PCI_CHIP_CEDAR_68F1: + case PCI_CHIP_CEDAR_68F8: + case PCI_CHIP_CEDAR_68F9: + case PCI_CHIP_CEDAR_68FE: + screen->chip_family = CHIP_FAMILY_CEDAR; + screen->chip_flags = RADEON_CHIPSET_TCL; + break; + + case PCI_CHIP_REDWOOD_68C0: + case PCI_CHIP_REDWOOD_68C1: + case PCI_CHIP_REDWOOD_68C8: + case PCI_CHIP_REDWOOD_68C9: + case PCI_CHIP_REDWOOD_68D8: + case PCI_CHIP_REDWOOD_68D9: + case PCI_CHIP_REDWOOD_68DA: + case PCI_CHIP_REDWOOD_68DE: + screen->chip_family = CHIP_FAMILY_REDWOOD; + screen->chip_flags = RADEON_CHIPSET_TCL; + break; + + case PCI_CHIP_JUNIPER_68A0: + case PCI_CHIP_JUNIPER_68A1: + case PCI_CHIP_JUNIPER_68A8: + case PCI_CHIP_JUNIPER_68A9: + case PCI_CHIP_JUNIPER_68B0: + case PCI_CHIP_JUNIPER_68B8: + case PCI_CHIP_JUNIPER_68B9: + case PCI_CHIP_JUNIPER_68BE: + screen->chip_family = CHIP_FAMILY_JUNIPER; + screen->chip_flags = RADEON_CHIPSET_TCL; + break; + + case PCI_CHIP_CYPRESS_6880: + case PCI_CHIP_CYPRESS_6888: + case PCI_CHIP_CYPRESS_6889: + case PCI_CHIP_CYPRESS_688A: + case PCI_CHIP_CYPRESS_6898: + case PCI_CHIP_CYPRESS_6899: + case PCI_CHIP_CYPRESS_689E: + screen->chip_family = CHIP_FAMILY_CYPRESS; + screen->chip_flags = RADEON_CHIPSET_TCL; + break; + + case PCI_CHIP_HEMLOCK_689C: + case PCI_CHIP_HEMLOCK_689D: + screen->chip_family = CHIP_FAMILY_HEMLOCK; + screen->chip_flags = RADEON_CHIPSET_TCL; + break; + default: fprintf(stderr, "unknown chip id 0x%x, can't guess.\n", device_id); @@ -1097,7 +1171,7 @@ radeonCreateScreen( __DRIscreen *sPriv ) } } else - { + { screen->fbLocation = (temp & 0xffff) << 16; } } @@ -1133,6 +1207,7 @@ radeonCreateScreen( __DRIscreen *sPriv ) /* pipe overrides */ switch (dri_priv->deviceID) { case PCI_CHIP_R300_AD: /* 9500 with 1 quadpipe verified by: Reid Linnemann */ + case PCI_CHIP_R350_AH: /* 9800 SE only have 1 quadpipe */ case PCI_CHIP_RV410_5E4C: /* RV410 SE only have 1 quadpipe */ case PCI_CHIP_RV410_5E4F: /* RV410 SE only have 1 quadpipe */ screen->num_gb_pipes = 1; @@ -1204,7 +1279,6 @@ radeonCreateScreen( __DRIscreen *sPriv ) i = 0; screen->extensions[i++] = &driCopySubBufferExtension.base; - screen->extensions[i++] = &driFrameTrackingExtension.base; screen->extensions[i++] = &driReadDrawableExtension; if ( screen->irq != 0 ) { @@ -1217,9 +1291,6 @@ radeonCreateScreen( __DRIscreen *sPriv ) #endif #if defined(RADEON_R200) - if (IS_R200_CLASS(screen)) - screen->extensions[i++] = &r200AllocateExtension.base; - screen->extensions[i++] = &r200texOffsetExtension.base; #endif @@ -1231,6 +1302,8 @@ radeonCreateScreen( __DRIscreen *sPriv ) screen->extensions[i++] = &r600texOffsetExtension.base; #endif + screen->extensions[i++] = &dri2ConfigQueryExtension.base; + screen->extensions[i++] = NULL; sPriv->extensions = screen->extensions; @@ -1309,6 +1382,56 @@ radeonCreateScreen2(__DRIscreen *sPriv) else screen->chip_flags |= RADEON_CLASS_R600; + /* r6xx+ tiling */ + if (IS_R600_CLASS(screen) && (sPriv->drm_version.minor >= 6)) { + ret = radeonGetParam(sPriv, RADEON_INFO_TILE_CONFIG, &temp); + if (ret) + fprintf(stderr, "failed to get tiling info\n"); + else { + screen->tile_config = temp; + screen->r7xx_bank_op = 0; + switch((screen->tile_config & 0xe) >> 1) { + case 0: + screen->num_channels = 1; + break; + case 1: + screen->num_channels = 2; + break; + case 2: + screen->num_channels = 4; + break; + case 3: + screen->num_channels = 8; + break; + default: + fprintf(stderr, "bad channels\n"); + break; + } + switch((screen->tile_config & 0x30) >> 4) { + case 0: + screen->num_banks = 4; + break; + case 1: + screen->num_banks = 8; + break; + default: + fprintf(stderr, "bad banks\n"); + break; + } + switch((screen->tile_config & 0xc0) >> 6) { + case 0: + screen->group_bytes = 256; + break; + case 1: + screen->group_bytes = 512; + break; + default: + fprintf(stderr, "bad group_bytes\n"); + break; + } + } + } + if (IS_R300_CLASS(screen)) { ret = radeonGetParam(sPriv, RADEON_PARAM_NUM_GB_PIPES, &temp); if (ret) { @@ -1340,6 +1463,7 @@ radeonCreateScreen2(__DRIscreen *sPriv) /* pipe overrides */ switch (device_id) { case PCI_CHIP_R300_AD: /* 9500 with 1 quadpipe verified by: Reid Linnemann */ + case PCI_CHIP_R350_AH: /* 9800 SE only have 1 quadpipe */ case PCI_CHIP_RV410_5E4C: /* RV410 SE only have 1 quadpipe */ case PCI_CHIP_RV410_5E4F: /* RV410 SE only have 1 quadpipe */ screen->num_gb_pipes = 1; @@ -1358,8 +1482,8 @@ radeonCreateScreen2(__DRIscreen *sPriv) i = 0; screen->extensions[i++] = &driCopySubBufferExtension.base; - screen->extensions[i++] = &driFrameTrackingExtension.base; screen->extensions[i++] = &driReadDrawableExtension; + screen->extensions[i++] = &dri2ConfigQueryExtension.base; if ( screen->irq != 0 ) { screen->extensions[i++] = &driSwapControlExtension.base; @@ -1371,9 +1495,6 @@ radeonCreateScreen2(__DRIscreen *sPriv) #endif #if defined(RADEON_R200) - if (IS_R200_CLASS(screen)) - screen->extensions[i++] = &r200AllocateExtension.base; - screen->extensions[i++] = &r200TexBufferExtension.base; #endif @@ -1385,6 +1506,8 @@ radeonCreateScreen2(__DRIscreen *sPriv) screen->extensions[i++] = &r600TexBufferExtension.base; #endif + screen->extensions[i++] = &radeonFlushExtension.base; + screen->extensions[i++] = NULL; sPriv->extensions = screen->extensions;