X-Git-Url: https://git.libre-soc.org/?a=blobdiff_plain;f=src%2Fmesa%2Fdrivers%2Fdri%2Fradeon%2Fradeon_state_init.c;h=6a8cf606dcb42b33c7e37ebcb27b18d8a517ddd5;hb=a6b7068ff5fbf4694a45a6e07adac5047e574514;hp=698efb145c0b5897347f66ce78c884eada6c6a8f;hpb=cd6a31cd4a9ea6deef4778c2eaef2d47240c3a6e;p=mesa.git diff --git a/src/mesa/drivers/dri/radeon/radeon_state_init.c b/src/mesa/drivers/dri/radeon/radeon_state_init.c index 698efb145c0..6a8cf606dcb 100644 --- a/src/mesa/drivers/dri/radeon/radeon_state_init.c +++ b/src/mesa/drivers/dri/radeon/radeon_state_init.c @@ -24,9 +24,10 @@ * * Authors: * Gareth Hughes - * Keith Whitwell + * Keith Whitwell */ +#include "main/errors.h" #include "main/glheader.h" #include "main/imports.h" #include "main/api_arrayelt.h" @@ -44,7 +45,7 @@ #include "../r200/r200_reg.h" -#include "xmlpool.h" +#include "util/xmlpool.h" /* New (1.3) state mechanism. 3 commands (packet, scalar, vector) in * 1.3 cmdbuffers allow all previous state to be updated as well as @@ -160,16 +161,7 @@ static struct { */ static int cmdpkt( r100ContextPtr rmesa, int id ) { - drm_radeon_cmd_header_t h; - - if (rmesa->radeon.radeonScreen->kernel_mm) { - return CP_PACKET0(packet[id].start, packet[id].len - 1); - } else { - h.i = 0; - h.packet.cmd_type = RADEON_CMD_PACKET; - h.packet.packet_id = id; - } - return h.i; + return CP_PACKET0(packet[id].start, packet[id].len - 1); } static int cmdvec( int offset, int stride, int count ) @@ -211,42 +203,21 @@ static int check_##NM( struct gl_context *ctx, struct radeon_state_atom *atom ) CHECK( always, GL_TRUE, 0 ) CHECK( always_add2, GL_TRUE, 2 ) CHECK( always_add4, GL_TRUE, 4 ) -CHECK( never, GL_FALSE, 0 ) -CHECK( tex0_mm, ctx->Texture.Unit[0]._ReallyEnabled, 3 ) -CHECK( tex1_mm, ctx->Texture.Unit[1]._ReallyEnabled, 3 ) +CHECK( tex0_mm, GL_TRUE, 3 ) +CHECK( tex1_mm, GL_TRUE, 3 ) /* need this for the cubic_map on disabled unit 2 bug, maybe r100 only? */ -CHECK( tex2_mm, ctx->Texture._EnabledUnits, 3 ) -CHECK( tex0, ctx->Texture.Unit[0]._ReallyEnabled, 2 ) -CHECK( tex1, ctx->Texture.Unit[1]._ReallyEnabled, 2 ) -CHECK( tex2, ctx->Texture._EnabledUnits, 2 ) -CHECK( cube0, (ctx->Texture.Unit[0]._ReallyEnabled & TEXTURE_CUBE_BIT), 3 + 3*5 - CUBE_STATE_SIZE ) -CHECK( cube1, (ctx->Texture.Unit[1]._ReallyEnabled & TEXTURE_CUBE_BIT), 3 + 3*5 - CUBE_STATE_SIZE ) -CHECK( cube2, (ctx->Texture.Unit[2]._ReallyEnabled & TEXTURE_CUBE_BIT), 3 + 3*5 - CUBE_STATE_SIZE ) -CHECK( cube0_mm, (ctx->Texture.Unit[0]._ReallyEnabled & TEXTURE_CUBE_BIT), 2 + 4*5 - CUBE_STATE_SIZE ) -CHECK( cube1_mm, (ctx->Texture.Unit[1]._ReallyEnabled & TEXTURE_CUBE_BIT), 2 + 4*5 - CUBE_STATE_SIZE ) -CHECK( cube2_mm, (ctx->Texture.Unit[2]._ReallyEnabled & TEXTURE_CUBE_BIT), 2 + 4*5 - CUBE_STATE_SIZE ) -CHECK( fog, ctx->Fog.Enabled, 0 ) +CHECK( tex2_mm, GL_TRUE, 3 ) +CHECK( cube0_mm, (ctx->Texture.Unit[0]._Current && ctx->Texture.Unit[0]._Current->Target == GL_TEXTURE_CUBE_MAP), 2 + 4*5 - CUBE_STATE_SIZE ) +CHECK( cube1_mm, (ctx->Texture.Unit[1]._Current && ctx->Texture.Unit[1]._Current->Target == GL_TEXTURE_CUBE_MAP), 2 + 4*5 - CUBE_STATE_SIZE ) +CHECK( cube2_mm, (ctx->Texture.Unit[2]._Current && ctx->Texture.Unit[2]._Current->Target == GL_TEXTURE_CUBE_MAP), 2 + 4*5 - CUBE_STATE_SIZE ) CHECK( fog_add4, ctx->Fog.Enabled, 4 ) -TCL_CHECK( tcl, GL_TRUE, 0 ) TCL_CHECK( tcl_add4, GL_TRUE, 4 ) -TCL_CHECK( tcl_tex0, ctx->Texture.Unit[0]._ReallyEnabled, 0 ) -TCL_CHECK( tcl_tex1, ctx->Texture.Unit[1]._ReallyEnabled, 0 ) -TCL_CHECK( tcl_tex2, ctx->Texture.Unit[2]._ReallyEnabled, 0 ) -TCL_CHECK( tcl_tex0_add4, ctx->Texture.Unit[0]._ReallyEnabled, 4 ) -TCL_CHECK( tcl_tex1_add4, ctx->Texture.Unit[1]._ReallyEnabled, 4 ) -TCL_CHECK( tcl_tex2_add4, ctx->Texture.Unit[2]._ReallyEnabled, 4 ) +TCL_CHECK( tcl_tex0_add4, ctx->Texture.Unit[0]._Current, 4 ) +TCL_CHECK( tcl_tex1_add4, ctx->Texture.Unit[1]._Current, 4 ) +TCL_CHECK( tcl_tex2_add4, ctx->Texture.Unit[2]._Current, 4 ) TCL_CHECK( tcl_lighting, ctx->Light.Enabled, 0 ) TCL_CHECK( tcl_lighting_add4, ctx->Light.Enabled, 4 ) -TCL_CHECK( tcl_eyespace_or_lighting, ctx->_NeedEyeCoords || ctx->Light.Enabled, 0 ) TCL_CHECK( tcl_eyespace_or_lighting_add4, ctx->_NeedEyeCoords || ctx->Light.Enabled, 4 ) -TCL_CHECK( tcl_lit0, ctx->Light.Enabled && ctx->Light.Light[0].Enabled, 0 ) -TCL_CHECK( tcl_lit1, ctx->Light.Enabled && ctx->Light.Light[1].Enabled, 0 ) -TCL_CHECK( tcl_lit2, ctx->Light.Enabled && ctx->Light.Light[2].Enabled, 0 ) -TCL_CHECK( tcl_lit3, ctx->Light.Enabled && ctx->Light.Light[3].Enabled, 0 ) -TCL_CHECK( tcl_lit4, ctx->Light.Enabled && ctx->Light.Light[4].Enabled, 0 ) -TCL_CHECK( tcl_lit5, ctx->Light.Enabled && ctx->Light.Light[5].Enabled, 0 ) -TCL_CHECK( tcl_lit6, ctx->Light.Enabled && ctx->Light.Light[6].Enabled, 0 ) -TCL_CHECK( tcl_lit7, ctx->Light.Enabled && ctx->Light.Light[7].Enabled, 0 ) TCL_CHECK( tcl_lit0_add6, ctx->Light.Enabled && ctx->Light.Light[0].Enabled, 6 ) TCL_CHECK( tcl_lit1_add6, ctx->Light.Enabled && ctx->Light.Light[1].Enabled, 6 ) TCL_CHECK( tcl_lit2_add6, ctx->Light.Enabled && ctx->Light.Light[2].Enabled, 6 ) @@ -255,24 +226,17 @@ TCL_CHECK( tcl_lit4_add6, ctx->Light.Enabled && ctx->Light.Light[4].Enabled, 6 ) TCL_CHECK( tcl_lit5_add6, ctx->Light.Enabled && ctx->Light.Light[5].Enabled, 6 ) TCL_CHECK( tcl_lit6_add6, ctx->Light.Enabled && ctx->Light.Light[6].Enabled, 6 ) TCL_CHECK( tcl_lit7_add6, ctx->Light.Enabled && ctx->Light.Light[7].Enabled, 6 ) -TCL_CHECK( tcl_ucp0, (ctx->Transform.ClipPlanesEnabled & 0x1), 0 ) -TCL_CHECK( tcl_ucp1, (ctx->Transform.ClipPlanesEnabled & 0x2), 0 ) -TCL_CHECK( tcl_ucp2, (ctx->Transform.ClipPlanesEnabled & 0x4), 0 ) -TCL_CHECK( tcl_ucp3, (ctx->Transform.ClipPlanesEnabled & 0x8), 0 ) -TCL_CHECK( tcl_ucp4, (ctx->Transform.ClipPlanesEnabled & 0x10), 0 ) -TCL_CHECK( tcl_ucp5, (ctx->Transform.ClipPlanesEnabled & 0x20), 0 ) TCL_CHECK( tcl_ucp0_add4, (ctx->Transform.ClipPlanesEnabled & 0x1), 4 ) TCL_CHECK( tcl_ucp1_add4, (ctx->Transform.ClipPlanesEnabled & 0x2), 4 ) TCL_CHECK( tcl_ucp2_add4, (ctx->Transform.ClipPlanesEnabled & 0x4), 4 ) TCL_CHECK( tcl_ucp3_add4, (ctx->Transform.ClipPlanesEnabled & 0x8), 4 ) TCL_CHECK( tcl_ucp4_add4, (ctx->Transform.ClipPlanesEnabled & 0x10), 4 ) TCL_CHECK( tcl_ucp5_add4, (ctx->Transform.ClipPlanesEnabled & 0x20), 4 ) -TCL_CHECK( tcl_eyespace_or_fog, ctx->_NeedEyeCoords || ctx->Fog.Enabled, 0 ) TCL_CHECK( tcl_eyespace_or_fog_add4, ctx->_NeedEyeCoords || ctx->Fog.Enabled, 4 ) -CHECK( txr0, (ctx->Texture.Unit[0]._ReallyEnabled & TEXTURE_RECT_BIT), 0 ) -CHECK( txr1, (ctx->Texture.Unit[1]._ReallyEnabled & TEXTURE_RECT_BIT), 0 ) -CHECK( txr2, (ctx->Texture.Unit[2]._ReallyEnabled & TEXTURE_RECT_BIT), 0 ) +CHECK( txr0, (ctx->Texture.Unit[0]._Current && ctx->Texture.Unit[0]._Current->Target == GL_TEXTURE_RECTANGLE), 0 ) +CHECK( txr1, (ctx->Texture.Unit[1]._Current && ctx->Texture.Unit[1]._Current->Target == GL_TEXTURE_RECTANGLE), 0 ) +CHECK( txr2, (ctx->Texture.Unit[2]._Current && ctx->Texture.Unit[2]._Current->Target == GL_TEXTURE_RECTANGLE), 0 ) #define OUT_VEC(hdr, data) do { \ drm_radeon_cmd_header_t h; \ @@ -300,7 +264,7 @@ static void scl_emit(struct gl_context *ctx, struct radeon_state_atom *atom) BATCH_LOCALS(&r100->radeon); uint32_t dwords = atom->check(ctx, atom); - BEGIN_BATCH_NO_AUTOSTATE(dwords); + BEGIN_BATCH(dwords); OUT_SCL(atom->cmd[0], atom->cmd+1); END_BATCH(); } @@ -312,7 +276,7 @@ static void vec_emit(struct gl_context *ctx, struct radeon_state_atom *atom) BATCH_LOCALS(&r100->radeon); uint32_t dwords = atom->check(ctx, atom); - BEGIN_BATCH_NO_AUTOSTATE(dwords); + BEGIN_BATCH(dwords); OUT_VEC(atom->cmd[0], atom->cmd+1); END_BATCH(); } @@ -324,77 +288,12 @@ static void lit_emit(struct gl_context *ctx, struct radeon_state_atom *atom) BATCH_LOCALS(&r100->radeon); uint32_t dwords = atom->check(ctx, atom); - BEGIN_BATCH_NO_AUTOSTATE(dwords); + BEGIN_BATCH(dwords); OUT_VEC(atom->cmd[LIT_CMD_0], atom->cmd+1); OUT_SCL(atom->cmd[LIT_CMD_1], atom->cmd+LIT_CMD_1+1); END_BATCH(); } -static void ctx_emit(struct gl_context *ctx, struct radeon_state_atom *atom) -{ - r100ContextPtr r100 = R100_CONTEXT(ctx); - BATCH_LOCALS(&r100->radeon); - struct radeon_renderbuffer *rrb; - uint32_t cbpitch; - uint32_t zbpitch, depth_fmt; - uint32_t dwords = atom->check(ctx, atom); - - /* output the first 7 bytes of context */ - BEGIN_BATCH_NO_AUTOSTATE(dwords); - OUT_BATCH_TABLE(atom->cmd, 5); - - rrb = radeon_get_depthbuffer(&r100->radeon); - if (!rrb) { - OUT_BATCH(0); - OUT_BATCH(0); - } else { - zbpitch = (rrb->pitch / rrb->cpp); - if (r100->using_hyperz) - zbpitch |= RADEON_DEPTH_HYPERZ; - - OUT_BATCH_RELOC(0, rrb->bo, 0, 0, RADEON_GEM_DOMAIN_VRAM, 0); - OUT_BATCH(zbpitch); - if (rrb->cpp == 4) - depth_fmt = RADEON_DEPTH_FORMAT_24BIT_INT_Z; - else - depth_fmt = RADEON_DEPTH_FORMAT_16BIT_INT_Z; - atom->cmd[CTX_RB3D_ZSTENCILCNTL] &= ~RADEON_DEPTH_FORMAT_MASK; - atom->cmd[CTX_RB3D_ZSTENCILCNTL] |= depth_fmt; - } - - OUT_BATCH(atom->cmd[CTX_RB3D_ZSTENCILCNTL]); - OUT_BATCH(atom->cmd[CTX_CMD_1]); - OUT_BATCH(atom->cmd[CTX_PP_CNTL]); - - rrb = radeon_get_colorbuffer(&r100->radeon); - if (!rrb || !rrb->bo) { - OUT_BATCH(atom->cmd[CTX_RB3D_CNTL]); - OUT_BATCH(atom->cmd[CTX_RB3D_COLOROFFSET]); - } else { - atom->cmd[CTX_RB3D_CNTL] &= ~(0xf << 10); - if (rrb->cpp == 4) - atom->cmd[CTX_RB3D_CNTL] |= RADEON_COLOR_FORMAT_ARGB8888; - else - atom->cmd[CTX_RB3D_CNTL] |= RADEON_COLOR_FORMAT_RGB565; - - OUT_BATCH(atom->cmd[CTX_RB3D_CNTL]); - OUT_BATCH_RELOC(0, rrb->bo, 0, 0, RADEON_GEM_DOMAIN_VRAM, 0); - } - - OUT_BATCH(atom->cmd[CTX_CMD_2]); - - if (!rrb || !rrb->bo) { - OUT_BATCH(atom->cmd[CTX_RB3D_COLORPITCH]); - } else { - cbpitch = (rrb->pitch / rrb->cpp); - if (rrb->bo->flags & RADEON_BO_FLAGS_MACRO_TILE) - cbpitch |= RADEON_COLOR_TILE_ENABLE; - OUT_BATCH(cbpitch); - } - - END_BATCH(); -} - static int check_always_ctx( struct gl_context *ctx, struct radeon_state_atom *atom) { r100ContextPtr r100 = R100_CONTEXT(ctx); @@ -436,14 +335,17 @@ static void ctx_emit_cs(struct gl_context *ctx, struct radeon_state_atom *atom) atom->cmd[CTX_RB3D_CNTL] &= ~(0xf << 10); if (rrb->cpp == 4) atom->cmd[CTX_RB3D_CNTL] |= RADEON_COLOR_FORMAT_ARGB8888; - else switch (rrb->base.Format) { - case MESA_FORMAT_RGB565: + else switch (rrb->base.Base.Format) { + case MESA_FORMAT_B5G6R5_UNORM: + case MESA_FORMAT_R5G6B5_UNORM: atom->cmd[CTX_RB3D_CNTL] |= RADEON_COLOR_FORMAT_RGB565; break; - case MESA_FORMAT_ARGB4444: + case MESA_FORMAT_B4G4R4A4_UNORM: + case MESA_FORMAT_A4R4G4B4_UNORM: atom->cmd[CTX_RB3D_CNTL] |= RADEON_COLOR_FORMAT_ARGB4444; break; - case MESA_FORMAT_ARGB1555: + case MESA_FORMAT_B5G5R5A1_UNORM: + case MESA_FORMAT_A1R5G5B5_UNORM: atom->cmd[CTX_RB3D_CNTL] |= RADEON_COLOR_FORMAT_ARGB1555; break; default: @@ -453,6 +355,8 @@ static void ctx_emit_cs(struct gl_context *ctx, struct radeon_state_atom *atom) cbpitch = (rrb->pitch / rrb->cpp); if (rrb->bo->flags & RADEON_BO_FLAGS_MACRO_TILE) cbpitch |= R200_COLOR_TILE_ENABLE; + if (rrb->bo->flags & RADEON_BO_FLAGS_MICRO_TILE) + cbpitch |= RADEON_COLOR_MICROTILE_ENABLE; drb = radeon_get_depthbuffer(&r100->radeon); if (drb) { @@ -466,7 +370,7 @@ static void ctx_emit_cs(struct gl_context *ctx, struct radeon_state_atom *atom) } - BEGIN_BATCH_NO_AUTOSTATE(dwords); + BEGIN_BATCH(dwords); /* In the CS case we need to split this up */ OUT_BATCH(CP_PACKET0(packet[0].start, 3)); @@ -488,7 +392,7 @@ static void ctx_emit_cs(struct gl_context *ctx, struct radeon_state_atom *atom) if (rrb) { OUT_BATCH(CP_PACKET0(RADEON_RB3D_COLOROFFSET, 0)); - OUT_BATCH_RELOC(0, rrb->bo, 0, 0, RADEON_GEM_DOMAIN_VRAM, 0); + OUT_BATCH_RELOC(rrb->draw_offset, rrb->bo, rrb->draw_offset, 0, RADEON_GEM_DOMAIN_VRAM, 0); OUT_BATCH(CP_PACKET0(RADEON_RB3D_COLORPITCH, 0)); OUT_BATCH_RELOC(cbpitch, rrb->bo, cbpitch, 0, RADEON_GEM_DOMAIN_VRAM, 0); @@ -499,47 +403,19 @@ static void ctx_emit_cs(struct gl_context *ctx, struct radeon_state_atom *atom) // } END_BATCH(); - BEGIN_BATCH_NO_AUTOSTATE(4); + BEGIN_BATCH(4); OUT_BATCH(CP_PACKET0(RADEON_RE_TOP_LEFT, 0)); OUT_BATCH(0); OUT_BATCH(CP_PACKET0(RADEON_RE_WIDTH_HEIGHT, 0)); if (rrb) { - OUT_BATCH(((rrb->base.Width - 1) << RADEON_RE_WIDTH_SHIFT) | - ((rrb->base.Height - 1) << RADEON_RE_HEIGHT_SHIFT)); + OUT_BATCH(((rrb->base.Base.Width - 1) << RADEON_RE_WIDTH_SHIFT) | + ((rrb->base.Base.Height - 1) << RADEON_RE_HEIGHT_SHIFT)); } else { OUT_BATCH(0); } END_BATCH(); } -static void cube_emit(struct gl_context *ctx, struct radeon_state_atom *atom) -{ - r100ContextPtr r100 = R100_CONTEXT(ctx); - BATCH_LOCALS(&r100->radeon); - uint32_t dwords = atom->check(ctx, atom); - int i = atom->idx, j; - radeonTexObj *t = r100->state.texture.unit[i].texobj; - radeon_mipmap_level *lvl; - - if (!(ctx->Texture.Unit[i]._ReallyEnabled & TEXTURE_CUBE_BIT)) - return; - - if (!t) - return; - - if (!t->mt) - return; - - BEGIN_BATCH_NO_AUTOSTATE(dwords); - OUT_BATCH_TABLE(atom->cmd, 3); - lvl = &t->mt->levels[0]; - for (j = 0; j < 5; j++) { - OUT_BATCH_RELOC(lvl->faces[j].offset, t->mt->bo, lvl->faces[j].offset, - RADEON_GEM_DOMAIN_VRAM, 0, 0); - } - END_BATCH(); -} - static void cube_emit_cs(struct gl_context *ctx, struct radeon_state_atom *atom) { r100ContextPtr r100 = R100_CONTEXT(ctx); @@ -550,7 +426,8 @@ static void cube_emit_cs(struct gl_context *ctx, struct radeon_state_atom *atom) radeon_mipmap_level *lvl; uint32_t base_reg; - if (!(ctx->Texture.Unit[i]._ReallyEnabled & TEXTURE_CUBE_BIT)) + if (!ctx->Texture.Unit[i]._Current || + ctx->Texture.Unit[i]._Current->Target != GL_TEXTURE_CUBE_MAP) return; if (!t) @@ -564,8 +441,8 @@ static void cube_emit_cs(struct gl_context *ctx, struct radeon_state_atom *atom) case 2: base_reg = RADEON_PP_CUBIC_OFFSET_T2_0; break; default: case 0: base_reg = RADEON_PP_CUBIC_OFFSET_T0_0; break; - }; - BEGIN_BATCH_NO_AUTOSTATE(dwords); + } + BEGIN_BATCH(dwords); OUT_BATCH_TABLE(atom->cmd, 2); lvl = &t->mt->levels[0]; for (j = 0; j < 5; j++) { @@ -576,41 +453,6 @@ static void cube_emit_cs(struct gl_context *ctx, struct radeon_state_atom *atom) END_BATCH(); } -static void tex_emit(struct gl_context *ctx, struct radeon_state_atom *atom) -{ - r100ContextPtr r100 = R100_CONTEXT(ctx); - BATCH_LOCALS(&r100->radeon); - uint32_t dwords = atom->cmd_size; - int i = atom->idx; - radeonTexObj *t = r100->state.texture.unit[i].texobj; - radeon_mipmap_level *lvl; - - if (t && t->mt && !t->image_override) - dwords += 2; - BEGIN_BATCH_NO_AUTOSTATE(dwords); - - OUT_BATCH_TABLE(atom->cmd, 3); - if (t && t->mt && !t->image_override) { - if ((ctx->Texture.Unit[i]._ReallyEnabled & TEXTURE_CUBE_BIT)) { - lvl = &t->mt->levels[0]; - OUT_BATCH_RELOC(lvl->faces[5].offset, t->mt->bo, lvl->faces[5].offset, - RADEON_GEM_DOMAIN_GTT|RADEON_GEM_DOMAIN_VRAM, 0, 0); - } else { - OUT_BATCH_RELOC(t->tile_bits, t->mt->bo, 0, - RADEON_GEM_DOMAIN_GTT|RADEON_GEM_DOMAIN_VRAM, 0, 0); - } - } else if (!t) { - /* workaround for old CS mechanism */ - OUT_BATCH(r100->radeon.radeonScreen->texOffset[RADEON_LOCAL_TEX_HEAP]); - // OUT_BATCH(r100->radeon.radeonScreen); - } else { - OUT_BATCH(t->override_offset); - } - - OUT_BATCH_TABLE((atom->cmd+4), 5); - END_BATCH(); -} - static void tex_emit_cs(struct gl_context *ctx, struct radeon_state_atom *atom) { r100ContextPtr r100 = R100_CONTEXT(ctx); @@ -632,7 +474,7 @@ static void tex_emit_cs(struct gl_context *ctx, struct radeon_state_atom *atom) dwords += 2; else dwords -= 2; - BEGIN_BATCH_NO_AUTOSTATE(dwords); + BEGIN_BATCH(dwords); OUT_BATCH(CP_PACKET0(RADEON_PP_TXFILTER_0 + (24 * i), 1)); OUT_BATCH_TABLE((atom->cmd + 1), 2); @@ -640,7 +482,8 @@ static void tex_emit_cs(struct gl_context *ctx, struct radeon_state_atom *atom) if (hastexture) { OUT_BATCH(CP_PACKET0(RADEON_PP_TXOFFSET_0 + (24 * i), 0)); if (t->mt && !t->image_override) { - if ((ctx->Texture.Unit[i]._ReallyEnabled & TEXTURE_CUBE_BIT)) { + if (ctx->Texture.Unit[i]._Current && + ctx->Texture.Unit[i]._Current->Target == GL_TEXTURE_CUBE_MAP) { lvl = &t->mt->levels[t->minLod]; OUT_BATCH_RELOC(lvl->faces[5].offset, t->mt->bo, lvl->faces[5].offset, RADEON_GEM_DOMAIN_GTT|RADEON_GEM_DOMAIN_VRAM, 0, 0); @@ -666,24 +509,9 @@ static void tex_emit_cs(struct gl_context *ctx, struct radeon_state_atom *atom) */ void radeonInitState( r100ContextPtr rmesa ) { - struct gl_context *ctx = rmesa->radeon.glCtx; + struct gl_context *ctx = &rmesa->radeon.glCtx; GLuint i; - rmesa->radeon.state.color.clear = 0x00000000; - - switch ( ctx->Visual.depthBits ) { - case 16: - rmesa->radeon.state.depth.clear = 0x0000ffff; - rmesa->radeon.state.stencil.clear = 0x00000000; - break; - case 24: - rmesa->radeon.state.depth.clear = 0x00ffffff; - rmesa->radeon.state.stencil.clear = 0xffff0000; - break; - default: - break; - } - rmesa->radeon.Fallback = 0; @@ -692,8 +520,8 @@ void radeonInitState( r100ContextPtr rmesa ) #define ALLOC_STATE_IDX( ATOM, CHK, SZ, NM, FLAG, IDX ) \ do { \ rmesa->hw.ATOM.cmd_size = SZ; \ - rmesa->hw.ATOM.cmd = (GLuint *)CALLOC(SZ * sizeof(int)); \ - rmesa->hw.ATOM.lastcmd = (GLuint *)CALLOC(SZ * sizeof(int)); \ + rmesa->hw.ATOM.cmd = (GLuint *) calloc(SZ, sizeof(int)); \ + rmesa->hw.ATOM.lastcmd = (GLuint *) calloc(SZ, sizeof(int)); \ rmesa->hw.ATOM.name = NM; \ rmesa->hw.ATOM.is_tcl = FLAG; \ rmesa->hw.ATOM.check = check_##CHK; \ @@ -708,11 +536,8 @@ void radeonInitState( r100ContextPtr rmesa ) /* Allocate state buffers: */ ALLOC_STATE( ctx, always_add4, CTX_STATE_SIZE, "CTX/context", 0 ); - if (rmesa->radeon.radeonScreen->kernel_mm) { - rmesa->hw.ctx.emit = ctx_emit_cs; - rmesa->hw.ctx.check = check_always_ctx; - } else - rmesa->hw.ctx.emit = ctx_emit; + rmesa->hw.ctx.emit = ctx_emit_cs; + rmesa->hw.ctx.check = check_always_ctx; ALLOC_STATE( lin, always, LIN_STATE_SIZE, "LIN/line", 0 ); ALLOC_STATE( msk, always, MSK_STATE_SIZE, "MSK/mask", 0 ); ALLOC_STATE( vpt, always, VPT_STATE_SIZE, "VPT/viewport", 0 ); @@ -721,96 +546,44 @@ void radeonInitState( r100ContextPtr rmesa ) ALLOC_STATE( zbs, always, ZBS_STATE_SIZE, "ZBS/zbias", 0 ); ALLOC_STATE( tcl, always, TCL_STATE_SIZE, "TCL/tcl", 1 ); ALLOC_STATE( mtl, tcl_lighting, MTL_STATE_SIZE, "MTL/material", 1 ); - if (rmesa->radeon.radeonScreen->kernel_mm) { - ALLOC_STATE( grd, always_add2, GRD_STATE_SIZE, "GRD/guard-band", 1 ); - ALLOC_STATE( fog, fog_add4, FOG_STATE_SIZE, "FOG/fog", 1 ); - ALLOC_STATE( glt, tcl_lighting_add4, GLT_STATE_SIZE, "GLT/light-global", 1 ); - ALLOC_STATE( eye, tcl_lighting_add4, EYE_STATE_SIZE, "EYE/eye-vector", 1 ); - ALLOC_STATE_IDX( tex[0], tex0_mm, TEX_STATE_SIZE, "TEX/tex-0", 0, 0); - ALLOC_STATE_IDX( tex[1], tex1_mm, TEX_STATE_SIZE, "TEX/tex-1", 0, 1); - ALLOC_STATE_IDX( tex[2], tex2_mm, TEX_STATE_SIZE, "TEX/tex-2", 0, 2); - ALLOC_STATE( mat[0], tcl_add4, MAT_STATE_SIZE, "MAT/modelproject", 1 ); - ALLOC_STATE( mat[1], tcl_eyespace_or_fog_add4, MAT_STATE_SIZE, "MAT/modelview", 1 ); - ALLOC_STATE( mat[2], tcl_eyespace_or_lighting_add4, MAT_STATE_SIZE, "MAT/it-modelview", 1 ); - ALLOC_STATE( mat[3], tcl_tex0_add4, MAT_STATE_SIZE, "MAT/texmat0", 1 ); - ALLOC_STATE( mat[4], tcl_tex1_add4, MAT_STATE_SIZE, "MAT/texmat1", 1 ); - ALLOC_STATE( mat[5], tcl_tex2_add4, MAT_STATE_SIZE, "MAT/texmat2", 1 ); - ALLOC_STATE( lit[0], tcl_lit0_add6, LIT_STATE_SIZE, "LIT/light-0", 1 ); - ALLOC_STATE( lit[1], tcl_lit1_add6, LIT_STATE_SIZE, "LIT/light-1", 1 ); - ALLOC_STATE( lit[2], tcl_lit2_add6, LIT_STATE_SIZE, "LIT/light-2", 1 ); - ALLOC_STATE( lit[3], tcl_lit3_add6, LIT_STATE_SIZE, "LIT/light-3", 1 ); - ALLOC_STATE( lit[4], tcl_lit4_add6, LIT_STATE_SIZE, "LIT/light-4", 1 ); - ALLOC_STATE( lit[5], tcl_lit5_add6, LIT_STATE_SIZE, "LIT/light-5", 1 ); - ALLOC_STATE( lit[6], tcl_lit6_add6, LIT_STATE_SIZE, "LIT/light-6", 1 ); - ALLOC_STATE( lit[7], tcl_lit7_add6, LIT_STATE_SIZE, "LIT/light-7", 1 ); - ALLOC_STATE( ucp[0], tcl_ucp0_add4, UCP_STATE_SIZE, "UCP/userclip-0", 1 ); - ALLOC_STATE( ucp[1], tcl_ucp1_add4, UCP_STATE_SIZE, "UCP/userclip-1", 1 ); - ALLOC_STATE( ucp[2], tcl_ucp2_add4, UCP_STATE_SIZE, "UCP/userclip-2", 1 ); - ALLOC_STATE( ucp[3], tcl_ucp3_add4, UCP_STATE_SIZE, "UCP/userclip-3", 1 ); - ALLOC_STATE( ucp[4], tcl_ucp4_add4, UCP_STATE_SIZE, "UCP/userclip-4", 1 ); - ALLOC_STATE( ucp[5], tcl_ucp5_add4, UCP_STATE_SIZE, "UCP/userclip-5", 1 ); - } else { - ALLOC_STATE( grd, always, GRD_STATE_SIZE, "GRD/guard-band", 1 ); - ALLOC_STATE( fog, fog, FOG_STATE_SIZE, "FOG/fog", 1 ); - ALLOC_STATE( glt, tcl_lighting, GLT_STATE_SIZE, "GLT/light-global", 1 ); - ALLOC_STATE( eye, tcl_lighting, EYE_STATE_SIZE, "EYE/eye-vector", 1 ); - ALLOC_STATE_IDX( tex[0], tex0, TEX_STATE_SIZE, "TEX/tex-0", 0, 0); - ALLOC_STATE_IDX( tex[1], tex1, TEX_STATE_SIZE, "TEX/tex-1", 0, 1); - ALLOC_STATE_IDX( tex[2], tex2, TEX_STATE_SIZE, "TEX/tex-2", 0, 2); - ALLOC_STATE( mat[0], tcl, MAT_STATE_SIZE, "MAT/modelproject", 1 ); - ALLOC_STATE( mat[1], tcl_eyespace_or_fog, MAT_STATE_SIZE, "MAT/modelview", 1 ); - ALLOC_STATE( mat[2], tcl_eyespace_or_lighting, MAT_STATE_SIZE, "MAT/it-modelview", 1 ); - ALLOC_STATE( mat[3], tcl_tex0, MAT_STATE_SIZE, "MAT/texmat0", 1 ); - ALLOC_STATE( mat[4], tcl_tex1, MAT_STATE_SIZE, "MAT/texmat1", 1 ); - ALLOC_STATE( mat[5], tcl_tex2, MAT_STATE_SIZE, "MAT/texmat2", 1 ); - ALLOC_STATE( lit[0], tcl_lit0, LIT_STATE_SIZE, "LIT/light-0", 1 ); - ALLOC_STATE( lit[1], tcl_lit1, LIT_STATE_SIZE, "LIT/light-1", 1 ); - ALLOC_STATE( lit[2], tcl_lit2, LIT_STATE_SIZE, "LIT/light-2", 1 ); - ALLOC_STATE( lit[3], tcl_lit3, LIT_STATE_SIZE, "LIT/light-3", 1 ); - ALLOC_STATE( lit[4], tcl_lit4, LIT_STATE_SIZE, "LIT/light-4", 1 ); - ALLOC_STATE( lit[5], tcl_lit5, LIT_STATE_SIZE, "LIT/light-5", 1 ); - ALLOC_STATE( lit[6], tcl_lit6, LIT_STATE_SIZE, "LIT/light-6", 1 ); - ALLOC_STATE( lit[7], tcl_lit7, LIT_STATE_SIZE, "LIT/light-7", 1 ); - ALLOC_STATE( ucp[0], tcl_ucp0, UCP_STATE_SIZE, "UCP/userclip-0", 1 ); - ALLOC_STATE( ucp[1], tcl_ucp1, UCP_STATE_SIZE, "UCP/userclip-1", 1 ); - ALLOC_STATE( ucp[2], tcl_ucp2, UCP_STATE_SIZE, "UCP/userclip-2", 1 ); - ALLOC_STATE( ucp[3], tcl_ucp3, UCP_STATE_SIZE, "UCP/userclip-3", 1 ); - ALLOC_STATE( ucp[4], tcl_ucp4, UCP_STATE_SIZE, "UCP/userclip-4", 1 ); - ALLOC_STATE( ucp[5], tcl_ucp5, UCP_STATE_SIZE, "UCP/userclip-5", 1 ); - } + ALLOC_STATE( grd, always_add2, GRD_STATE_SIZE, "GRD/guard-band", 1 ); + ALLOC_STATE( fog, fog_add4, FOG_STATE_SIZE, "FOG/fog", 1 ); + ALLOC_STATE( glt, tcl_lighting_add4, GLT_STATE_SIZE, "GLT/light-global", 1 ); + ALLOC_STATE( eye, tcl_lighting_add4, EYE_STATE_SIZE, "EYE/eye-vector", 1 ); + ALLOC_STATE_IDX( tex[0], tex0_mm, TEX_STATE_SIZE, "TEX/tex-0", 0, 0); + ALLOC_STATE_IDX( tex[1], tex1_mm, TEX_STATE_SIZE, "TEX/tex-1", 0, 1); + ALLOC_STATE_IDX( tex[2], tex2_mm, TEX_STATE_SIZE, "TEX/tex-2", 0, 2); + ALLOC_STATE( mat[0], tcl_add4, MAT_STATE_SIZE, "MAT/modelproject", 1 ); + ALLOC_STATE( mat[1], tcl_eyespace_or_fog_add4, MAT_STATE_SIZE, "MAT/modelview", 1 ); + ALLOC_STATE( mat[2], tcl_eyespace_or_lighting_add4, MAT_STATE_SIZE, "MAT/it-modelview", 1 ); + ALLOC_STATE( mat[3], tcl_tex0_add4, MAT_STATE_SIZE, "MAT/texmat0", 1 ); + ALLOC_STATE( mat[4], tcl_tex1_add4, MAT_STATE_SIZE, "MAT/texmat1", 1 ); + ALLOC_STATE( mat[5], tcl_tex2_add4, MAT_STATE_SIZE, "MAT/texmat2", 1 ); + ALLOC_STATE( lit[0], tcl_lit0_add6, LIT_STATE_SIZE, "LIT/light-0", 1 ); + ALLOC_STATE( lit[1], tcl_lit1_add6, LIT_STATE_SIZE, "LIT/light-1", 1 ); + ALLOC_STATE( lit[2], tcl_lit2_add6, LIT_STATE_SIZE, "LIT/light-2", 1 ); + ALLOC_STATE( lit[3], tcl_lit3_add6, LIT_STATE_SIZE, "LIT/light-3", 1 ); + ALLOC_STATE( lit[4], tcl_lit4_add6, LIT_STATE_SIZE, "LIT/light-4", 1 ); + ALLOC_STATE( lit[5], tcl_lit5_add6, LIT_STATE_SIZE, "LIT/light-5", 1 ); + ALLOC_STATE( lit[6], tcl_lit6_add6, LIT_STATE_SIZE, "LIT/light-6", 1 ); + ALLOC_STATE( lit[7], tcl_lit7_add6, LIT_STATE_SIZE, "LIT/light-7", 1 ); + ALLOC_STATE( ucp[0], tcl_ucp0_add4, UCP_STATE_SIZE, "UCP/userclip-0", 1 ); + ALLOC_STATE( ucp[1], tcl_ucp1_add4, UCP_STATE_SIZE, "UCP/userclip-1", 1 ); + ALLOC_STATE( ucp[2], tcl_ucp2_add4, UCP_STATE_SIZE, "UCP/userclip-2", 1 ); + ALLOC_STATE( ucp[3], tcl_ucp3_add4, UCP_STATE_SIZE, "UCP/userclip-3", 1 ); + ALLOC_STATE( ucp[4], tcl_ucp4_add4, UCP_STATE_SIZE, "UCP/userclip-4", 1 ); + ALLOC_STATE( ucp[5], tcl_ucp5_add4, UCP_STATE_SIZE, "UCP/userclip-5", 1 ); + ALLOC_STATE( stp, always, STP_STATE_SIZE, "STP/stp", 0 ); - if (rmesa->radeon.radeonScreen->kernel_mm) { - ALLOC_STATE( stp, always, STP_STATE_SIZE, "STP/stp", 0 ); - } - for (i = 0; i < 3; i++) { - if (rmesa->radeon.radeonScreen->kernel_mm) - rmesa->hw.tex[i].emit = tex_emit_cs; - else - rmesa->hw.tex[i].emit = tex_emit; - } - if (rmesa->radeon.radeonScreen->drmSupportsCubeMapsR100) - { - if (rmesa->radeon.radeonScreen->kernel_mm) { - ALLOC_STATE_IDX( cube[0], cube0_mm, CUBE_STATE_SIZE, "CUBE/cube-0", 0, 0 ); - ALLOC_STATE_IDX( cube[1], cube1_mm, CUBE_STATE_SIZE, "CUBE/cube-1", 0, 1 ); - ALLOC_STATE_IDX( cube[2], cube2_mm, CUBE_STATE_SIZE, "CUBE/cube-2", 0, 2 ); - for (i = 0; i < 3; i++) - rmesa->hw.cube[i].emit = cube_emit_cs; - } else { - ALLOC_STATE_IDX( cube[0], cube0, CUBE_STATE_SIZE, "CUBE/cube-0", 0, 0 ); - ALLOC_STATE_IDX( cube[1], cube1, CUBE_STATE_SIZE, "CUBE/cube-1", 0, 1 ); - ALLOC_STATE_IDX( cube[2], cube2, CUBE_STATE_SIZE, "CUBE/cube-2", 0, 2 ); - for (i = 0; i < 3; i++) - rmesa->hw.cube[i].emit = cube_emit; - } - } - else - { - ALLOC_STATE_IDX( cube[0], never, CUBE_STATE_SIZE, "CUBE/cube-0", 0, 0 ); - ALLOC_STATE_IDX( cube[1], never, CUBE_STATE_SIZE, "CUBE/cube-1", 0, 1 ); - ALLOC_STATE_IDX( cube[2], never, CUBE_STATE_SIZE, "CUBE/cube-2", 0, 2 ); + rmesa->hw.tex[i].emit = tex_emit_cs; } + ALLOC_STATE_IDX( cube[0], cube0_mm, CUBE_STATE_SIZE, "CUBE/cube-0", 0, 0 ); + ALLOC_STATE_IDX( cube[1], cube1_mm, CUBE_STATE_SIZE, "CUBE/cube-1", 0, 1 ); + ALLOC_STATE_IDX( cube[2], cube2_mm, CUBE_STATE_SIZE, "CUBE/cube-2", 0, 2 ); + for (i = 0; i < 3; i++) + rmesa->hw.cube[i].emit = cube_emit_cs; + ALLOC_STATE_IDX( txr[0], txr0, TXR_STATE_SIZE, "TXR/txr-0", 0, 0 ); ALLOC_STATE_IDX( txr[1], txr1, TXR_STATE_SIZE, "TXR/txr-1", 0, 1 ); ALLOC_STATE_IDX( txr[2], txr2, TXR_STATE_SIZE, "TXR/txr-2", 0, 2 ); @@ -874,27 +647,22 @@ void radeonInitState( r100ContextPtr rmesa ) cmdvec( RADEON_VS_UCP_ADDR + i, 1, 4 ); } - if (rmesa->radeon.radeonScreen->kernel_mm) { - rmesa->hw.stp.cmd[STP_CMD_0] = CP_PACKET0(RADEON_RE_STIPPLE_ADDR, 0); - rmesa->hw.stp.cmd[STP_DATA_0] = 0; - rmesa->hw.stp.cmd[STP_CMD_1] = CP_PACKET0_ONE(RADEON_RE_STIPPLE_DATA, 31); + rmesa->hw.stp.cmd[STP_CMD_0] = CP_PACKET0(RADEON_RE_STIPPLE_ADDR, 0); + rmesa->hw.stp.cmd[STP_DATA_0] = 0; + rmesa->hw.stp.cmd[STP_CMD_1] = CP_PACKET0_ONE(RADEON_RE_STIPPLE_DATA, 31); - rmesa->hw.grd.emit = scl_emit; - rmesa->hw.fog.emit = vec_emit; - rmesa->hw.glt.emit = vec_emit; - rmesa->hw.eye.emit = vec_emit; - - for (i = 0; i < 6; i++) - rmesa->hw.mat[i].emit = vec_emit; + rmesa->hw.grd.emit = scl_emit; + rmesa->hw.fog.emit = vec_emit; + rmesa->hw.glt.emit = vec_emit; + rmesa->hw.eye.emit = vec_emit; + for (i = 0; i < 6; i++) + rmesa->hw.mat[i].emit = vec_emit; - for (i = 0; i < 8; i++) - rmesa->hw.lit[i].emit = lit_emit; + for (i = 0; i < 8; i++) + rmesa->hw.lit[i].emit = lit_emit; - for (i = 0; i < 6; i++) - rmesa->hw.ucp[i].emit = vec_emit; - } - - rmesa->last_ReallyEnabled = -1; + for (i = 0; i < 6; i++) + rmesa->hw.ucp[i].emit = vec_emit; /* Initial Harware state: */ @@ -1150,11 +918,9 @@ void radeonInitState( r100ContextPtr rmesa ) rmesa->hw.eye.cmd[EYE_Z] = IEEE_ONE; rmesa->hw.eye.cmd[EYE_RESCALE_FACTOR] = IEEE_ONE; - if (rmesa->radeon.radeonScreen->kernel_mm) { - radeon_init_query_stateobj(&rmesa->radeon, R100_QUERYOBJ_CMDSIZE); - rmesa->radeon.query.queryobj.cmd[R100_QUERYOBJ_CMD_0] = CP_PACKET0(RADEON_RB3D_ZPASS_DATA, 0); - rmesa->radeon.query.queryobj.cmd[R100_QUERYOBJ_DATA_0] = 0; - } + radeon_init_query_stateobj(&rmesa->radeon, R100_QUERYOBJ_CMDSIZE); + rmesa->radeon.query.queryobj.cmd[R100_QUERYOBJ_CMD_0] = CP_PACKET0(RADEON_RB3D_ZPASS_DATA, 0); + rmesa->radeon.query.queryobj.cmd[R100_QUERYOBJ_DATA_0] = 0; rmesa->radeon.hw.all_dirty = GL_TRUE;