X-Git-Url: https://git.libre-soc.org/?a=blobdiff_plain;f=src%2Fmesa%2Fdrivers%2Fdri%2Fradeon%2Fradeon_tcl.c;h=4f0a127314a4caf9c4c8704fb6ba8da1ddb2ae8e;hb=8e3696137f2cb7b4f5a3824f26186ecbb06f9282;hp=b334ea05e5b1ce2beb267b04cc34154ef256ab83;hpb=1d4dbd8d9b00cdba8c4aef4a3994d8763fea0dff;p=mesa.git diff --git a/src/mesa/drivers/dri/radeon/radeon_tcl.c b/src/mesa/drivers/dri/radeon/radeon_tcl.c index b334ea05e5b..4f0a127314a 100644 --- a/src/mesa/drivers/dri/radeon/radeon_tcl.c +++ b/src/mesa/drivers/dri/radeon/radeon_tcl.c @@ -1,7 +1,7 @@ /************************************************************************** Copyright 2000, 2001 ATI Technologies Inc., Ontario, Canada, and - Tungsten Graphics Inc., Austin, Texas. + VMware, Inc. All Rights Reserved. @@ -29,14 +29,16 @@ WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. /* * Authors: - * Keith Whitwell + * Keith Whitwell */ #include "main/glheader.h" -#include "main/imports.h" -#include "main/light.h" #include "main/mtypes.h" +#include "main/light.h" #include "main/enums.h" +#include "main/state.h" + +#include "util/macros.h" #include "vbo/vbo.h" #include "tnl/tnl.h" @@ -46,7 +48,6 @@ WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. #include "radeon_context.h" #include "radeon_state.h" #include "radeon_ioctl.h" -#include "radeon_tex.h" #include "radeon_tcl.h" #include "radeon_swtcl.h" #include "radeon_maos.h" @@ -65,7 +66,6 @@ WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. #define HAVE_LINE_STRIPS 1 #define HAVE_TRIANGLES 1 #define HAVE_TRI_STRIPS 1 -#define HAVE_TRI_STRIP_1 0 #define HAVE_TRI_FANS 1 #define HAVE_QUADS 0 #define HAVE_QUAD_STRIPS 0 @@ -104,7 +104,7 @@ static GLboolean discrete_prim[0x10] = { 0, 0, }; - + #define LOCAL_VARS r100ContextPtr rmesa = R100_CONTEXT(ctx) #define ELT_TYPE GLushort @@ -145,10 +145,10 @@ static GLboolean discrete_prim[0x10] = { #define ALLOC_ELTS(nr) radeonAllocElts( rmesa, nr ) -static GLushort *radeonAllocElts( r100ContextPtr rmesa, GLuint nr ) +static GLushort *radeonAllocElts( r100ContextPtr rmesa, GLuint nr ) { if (rmesa->radeon.dma.flush) - rmesa->radeon.dma.flush( rmesa->radeon.glCtx ); + rmesa->radeon.dma.flush( &rmesa->radeon.glCtx ); radeonEmitAOS( rmesa, rmesa->radeon.tcl.aos_count, 0 ); @@ -165,19 +165,19 @@ static GLushort *radeonAllocElts( r100ContextPtr rmesa, GLuint nr ) * discrete and there are no intervening state changes. (Somewhat * duplicates changes to DrawArrays code) */ -static void radeonEmitPrim( GLcontext *ctx, - GLenum prim, - GLuint hwprim, - GLuint start, - GLuint count) +static void radeonEmitPrim( struct gl_context *ctx, + GLenum prim, + GLuint hwprim, + GLuint start, + GLuint count) { r100ContextPtr rmesa = R100_CONTEXT( ctx ); radeonTclPrimitive( ctx, prim, hwprim ); - + radeonEmitAOS( rmesa, rmesa->radeon.tcl.aos_count, start ); - + /* Why couldn't this packet have taken an offset param? */ radeonEmitVbufPrim( rmesa, @@ -208,8 +208,8 @@ static void radeonEmitPrim( GLcontext *ctx, #ifdef MESA_BIG_ENDIAN /* We could do without (most of) this ugliness if dest was always 32 bit word aligned... */ #define EMIT_ELT(dest, offset, x) do { \ - int off = offset + ( ( (GLuint)dest & 0x2 ) >> 1 ); \ - GLushort *des = (GLushort *)( (GLuint)dest & ~0x2 ); \ + int off = offset + ( ( (uintptr_t)dest & 0x2 ) >> 1 ); \ + GLushort *des = (GLushort *)( (uintptr_t)dest & ~0x2 ); \ (des)[ off + 1 - 2 * ( off & 1 ) ] = (GLushort)(x); \ (void)rmesa; } while (0) #else @@ -229,7 +229,7 @@ static void radeonEmitPrim( GLcontext *ctx, /* External entrypoints */ /**********************************************************************/ -void radeonEmitPrimitive( GLcontext *ctx, +void radeonEmitPrimitive( struct gl_context *ctx, GLuint first, GLuint last, GLuint flags ) @@ -237,7 +237,7 @@ void radeonEmitPrimitive( GLcontext *ctx, tcl_render_tab_verts[flags&PRIM_MODE_MASK]( ctx, first, last, flags ); } -void radeonEmitEltPrimitive( GLcontext *ctx, +void radeonEmitEltPrimitive( struct gl_context *ctx, GLuint first, GLuint last, GLuint flags ) @@ -245,7 +245,7 @@ void radeonEmitEltPrimitive( GLcontext *ctx, tcl_render_tab_elts[flags&PRIM_MODE_MASK]( ctx, first, last, flags ); } -void radeonTclPrimitive( GLcontext *ctx, +void radeonTclPrimitive( struct gl_context *ctx, GLenum prim, int hw_prim ) { @@ -253,6 +253,10 @@ void radeonTclPrimitive( GLcontext *ctx, GLuint se_cntl; GLuint newprim = hw_prim | RADEON_CP_VC_CNTL_TCL_ENABLE; + radeon_prepare_render(&rmesa->radeon); + if (rmesa->radeon.NewGLState) + radeonValidateState( ctx ); + if (newprim != rmesa->tcl.hw_primitive || !discrete_prim[hw_prim&0xf]) { RADEON_NEWPRIM( rmesa ); @@ -262,7 +266,7 @@ void radeonTclPrimitive( GLcontext *ctx, se_cntl = rmesa->hw.set.cmd[SET_SE_CNTL]; se_cntl &= ~RADEON_FLAT_SHADE_VTX_LAST; - if (prim == GL_POLYGON && (ctx->_TriangleCaps & DD_FLATSHADE)) + if (prim == GL_POLYGON && ctx->Light.ShadeModel == GL_FLAT) se_cntl |= RADEON_FLAT_SHADE_VTX_0; else se_cntl |= RADEON_FLAT_SHADE_VTX_LAST; @@ -273,94 +277,11 @@ void radeonTclPrimitive( GLcontext *ctx, } } -/**********************************************************************/ -/* Fog blend factor computation for hw tcl */ -/* same calculation used as in t_vb_fog.c */ -/**********************************************************************/ - -#define FOG_EXP_TABLE_SIZE 256 -#define FOG_MAX (10.0) -#define EXP_FOG_MAX .0006595 -#define FOG_INCR (FOG_MAX/FOG_EXP_TABLE_SIZE) -static GLfloat exp_table[FOG_EXP_TABLE_SIZE]; - -#if 1 -#define NEG_EXP( result, narg ) \ -do { \ - GLfloat f = (GLfloat) (narg * (1.0/FOG_INCR)); \ - GLint k = (GLint) f; \ - if (k > FOG_EXP_TABLE_SIZE-2) \ - result = (GLfloat) EXP_FOG_MAX; \ - else \ - result = exp_table[k] + (f-k)*(exp_table[k+1]-exp_table[k]); \ -} while (0) -#else -#define NEG_EXP( result, narg ) \ -do { \ - result = exp(-narg); \ -} while (0) -#endif - - -/** - * Initialize the exp_table[] lookup table for approximating exp(). - */ -void -radeonInitStaticFogData( void ) -{ - GLfloat f = 0.0F; - GLint i = 0; - for ( ; i < FOG_EXP_TABLE_SIZE ; i++, f += FOG_INCR) { - exp_table[i] = (GLfloat) exp(-f); - } -} - - -/** - * Compute per-vertex fog blend factors from fog coordinates by - * evaluating the GL_LINEAR, GL_EXP or GL_EXP2 fog function. - * Fog coordinates are distances from the eye (typically between the - * near and far clip plane distances). - * Note the fog (eye Z) coords may be negative so we use ABS(z) below. - * Fog blend factors are in the range [0,1]. - */ -float -radeonComputeFogBlendFactor( GLcontext *ctx, GLfloat fogcoord ) -{ - GLfloat end = ctx->Fog.End; - GLfloat d, temp; - const GLfloat z = FABSF(fogcoord); - - switch (ctx->Fog.Mode) { - case GL_LINEAR: - if (ctx->Fog.Start == ctx->Fog.End) - d = 1.0F; - else - d = 1.0F / (ctx->Fog.End - ctx->Fog.Start); - temp = (end - z) * d; - return CLAMP(temp, 0.0F, 1.0F); - break; - case GL_EXP: - d = ctx->Fog.Density; - NEG_EXP( temp, d * z ); - return temp; - break; - case GL_EXP2: - d = ctx->Fog.Density*ctx->Fog.Density; - NEG_EXP( temp, d * z * z ); - return temp; - break; - default: - _mesa_problem(ctx, "Bad fog mode in make_fog_coord"); - return 0; - } -} - /** * Predict total emit size for next rendering operation so there is no flush in middle of rendering * Prediction has to aim towards the best possible value that is worse than worst case scenario */ -static GLuint radeonEnsureEmitSize( GLcontext * ctx , GLuint inputs ) +static GLuint radeonEnsureEmitSize( struct gl_context * ctx , GLuint inputs ) { r100ContextPtr rmesa = R100_CONTEXT(ctx); TNLcontext *tnl = TNL_CONTEXT(ctx); @@ -377,7 +298,7 @@ static GLuint radeonEnsureEmitSize( GLcontext * ctx , GLuint inputs ) VERT_BIT_FOG }; /* predict number of aos to emit */ - for (i=0; i < sizeof(flags_to_check)/sizeof(flags_to_check[0]); ++i) + for (i=0; i < ARRAY_SIZE(flags_to_check); ++i) { if (inputs & flags_to_check[i]) ++nr_aos; @@ -394,12 +315,10 @@ static GLuint radeonEnsureEmitSize( GLcontext * ctx , GLuint inputs ) state_size = radeonCountStateEmitSize( &rmesa->radeon ); /* tcl may be changed in radeonEmitArrays so account for it if not dirty */ if (!rmesa->hw.tcl.dirty) - state_size += rmesa->hw.tcl.check( rmesa->radeon.glCtx, &rmesa->hw.tcl ); + state_size += rmesa->hw.tcl.check( &rmesa->radeon.glCtx, &rmesa->hw.tcl ); /* predict size for elements */ for (i = 0; i < VB->PrimitiveCount; ++i) { - if (!VB->Primitive[i].count) - continue; /* If primitive.count is less than MAX_CONVERSION_SIZE rendering code may decide convert to elts. In that case we have to make pessimistic prediction. @@ -407,17 +326,20 @@ static GLuint radeonEnsureEmitSize( GLcontext * ctx , GLuint inputs ) const GLuint elts = ELTS_BUFSZ(nr_aos); const GLuint index = INDEX_BUFSZ; const GLuint vbuf = VBUF_BUFSZ; + if (!VB->Primitive[i].count) + continue; if ( (!VB->Elts && VB->Primitive[i].count >= MAX_CONVERSION_SIZE) || vbuf > index + elts) space_required += vbuf; else space_required += index + elts; + space_required += VB->Primitive[i].count * 3; space_required += AOS_BUFSZ(nr_aos); } space_required += SCISSOR_BUFSZ; } /* flush the buffer in case we need more than is left. */ - if (rcommonEnsureCmdBufSpace(&rmesa->radeon, space_required, __FUNCTION__)) + if (rcommonEnsureCmdBufSpace(&rmesa->radeon, space_required, __func__)) return space_required + radeonCountStateEmitSize( &rmesa->radeon ); else return space_required + state_size; @@ -430,7 +352,7 @@ static GLuint radeonEnsureEmitSize( GLcontext * ctx , GLuint inputs ) /* TCL render. */ -static GLboolean radeon_run_tcl_render( GLcontext *ctx, +static GLboolean radeon_run_tcl_render( struct gl_context *ctx, struct tnl_pipeline_stage *stage ) { r100ContextPtr rmesa = R100_CONTEXT(ctx); @@ -438,8 +360,9 @@ static GLboolean radeon_run_tcl_render( GLcontext *ctx, struct vertex_buffer *VB = &tnl->vb; GLuint inputs = VERT_BIT_POS | VERT_BIT_COLOR0; GLuint i; + GLuint emit_end; - /* TODO: separate this from the swtnl pipeline + /* TODO: separate this from the swtnl pipeline */ if (rmesa->radeon.TclFallback) return GL_TRUE; /* fallback to software t&l */ @@ -454,7 +377,7 @@ static GLboolean radeon_run_tcl_render( GLcontext *ctx, inputs |= VERT_BIT_NORMAL; } - if (ctx->_TriangleCaps & DD_SEPARATE_SPECULAR) { + if (_mesa_need_secondary_color(ctx)) { inputs |= VERT_BIT_COLOR1; } @@ -463,7 +386,7 @@ static GLboolean radeon_run_tcl_render( GLcontext *ctx, } for (i = 0 ; i < ctx->Const.MaxTextureUnits; i++) { - if (ctx->Texture.Unit[i]._ReallyEnabled) { + if (ctx->Texture.Unit[i]._Current) { /* TODO: probably should not emit texture coords when texgen is enabled */ if (rmesa->TexGenNeedNormals[i]) { inputs |= VERT_BIT_NORMAL; @@ -473,7 +396,7 @@ static GLboolean radeon_run_tcl_render( GLcontext *ctx, } radeonReleaseArrays( ctx, ~0 ); - GLuint emit_end = radeonEnsureEmitSize( ctx, inputs ) + emit_end = radeonEnsureEmitSize( ctx, inputs ) + rmesa->radeon.cmdbuf.cs->cdw; radeonEmitArrays( ctx, inputs ); @@ -503,7 +426,7 @@ static GLboolean radeon_run_tcl_render( GLcontext *ctx, -/* Initial state for tcl stage. +/* Initial state for tcl stage. */ const struct tnl_pipeline_stage _radeon_tcl_stage = { @@ -527,7 +450,7 @@ const struct tnl_pipeline_stage _radeon_tcl_stage = */ -static void transition_to_swtnl( GLcontext *ctx ) +static void transition_to_swtnl( struct gl_context *ctx ) { r100ContextPtr rmesa = R100_CONTEXT(ctx); TNLcontext *tnl = TNL_CONTEXT(ctx); @@ -539,16 +462,16 @@ static void transition_to_swtnl( GLcontext *ctx ) radeonChooseVertexState( ctx ); radeonChooseRenderState( ctx ); - _mesa_validate_all_lighting_tables( ctx ); + _tnl_validate_shine_tables( ctx ); - tnl->Driver.NotifyMaterialChange = - _mesa_validate_all_lighting_tables; + tnl->Driver.NotifyMaterialChange = + _tnl_validate_shine_tables; radeonReleaseArrays( ctx, ~0 ); se_cntl = rmesa->hw.set.cmd[SET_SE_CNTL]; se_cntl |= RADEON_FLAT_SHADE_VTX_LAST; - + if (se_cntl != rmesa->hw.set.cmd[SET_SE_CNTL]) { RADEON_STATECHANGE( rmesa, set ); rmesa->hw.set.cmd[SET_SE_CNTL] = se_cntl; @@ -556,7 +479,7 @@ static void transition_to_swtnl( GLcontext *ctx ) } -static void transition_to_hwtnl( GLcontext *ctx ) +static void transition_to_hwtnl( struct gl_context *ctx ) { r100ContextPtr rmesa = R100_CONTEXT(ctx); TNLcontext *tnl = TNL_CONTEXT(ctx); @@ -577,15 +500,15 @@ static void transition_to_hwtnl( GLcontext *ctx ) tnl->Driver.NotifyMaterialChange = radeonUpdateMaterial; - if ( rmesa->radeon.dma.flush ) - rmesa->radeon.dma.flush( rmesa->radeon.glCtx ); + if ( rmesa->radeon.dma.flush ) + rmesa->radeon.dma.flush( &rmesa->radeon.glCtx ); rmesa->radeon.dma.flush = NULL; rmesa->swtcl.vertex_format = 0; - - // if (rmesa->swtcl.indexed_verts.buf) - // radeonReleaseDmaRegion( rmesa, &rmesa->swtcl.indexed_verts, - // __FUNCTION__ ); + + // if (rmesa->swtcl.indexed_verts.buf) + // radeonReleaseDmaRegion( rmesa, &rmesa->swtcl.indexed_verts, + // __func__ ); if (RADEON_DEBUG & RADEON_FALLBACKS) fprintf(stderr, "Radeon end tcl fallback\n"); @@ -616,7 +539,7 @@ static char *getFallbackString(GLuint bit) -void radeonTclFallback( GLcontext *ctx, GLuint bit, GLboolean mode ) +void radeonTclFallback( struct gl_context *ctx, GLuint bit, GLboolean mode ) { r100ContextPtr rmesa = R100_CONTEXT(ctx); GLuint oldfallback = rmesa->radeon.TclFallback;