X-Git-Url: https://git.libre-soc.org/?a=blobdiff_plain;f=src%2Fmesa%2Fshader%2Fprog_instruction.h;h=48e7b04c98cc506d7dd7ee17be9162a71ddb168c;hb=c0b59420eec5ffdf22a5919d38851c3620b97c09;hp=16701e4ec95b51555a41bceb500078131be95070;hpb=035c0cf71a5fe3beee55654e1f7148adfe626cc0;p=mesa.git diff --git a/src/mesa/shader/prog_instruction.h b/src/mesa/shader/prog_instruction.h index 16701e4ec95..48e7b04c98c 100644 --- a/src/mesa/shader/prog_instruction.h +++ b/src/mesa/shader/prog_instruction.h @@ -1,8 +1,8 @@ /* * Mesa 3-D graphics library - * Version: 6.5.3 + * Version: 7.3 * - * Copyright (C) 1999-2007 Brian Paul All Rights Reserved. + * Copyright (C) 1999-2008 Brian Paul All Rights Reserved. * * Permission is hereby granted, free of charge, to any person obtaining a * copy of this software and associated documentation files (the "Software"), @@ -145,6 +145,7 @@ typedef enum prog_opcode { OPCODE_NOP = 0, /* X */ OPCODE_ABS, /* X X 1.1 X */ OPCODE_ADD, /* X X X X X */ + OPCODE_AND, /* */ OPCODE_ARA, /* 2 */ OPCODE_ARL, /* X X */ OPCODE_ARL_NV, /* 2 */ @@ -159,6 +160,8 @@ typedef enum prog_opcode { OPCODE_COS, /* X 2 X X */ OPCODE_DDX, /* X X */ OPCODE_DDY, /* X X */ + OPCODE_DP2, /* 2 */ + OPCODE_DP2A, /* 2 */ OPCODE_DP3, /* X X X X X */ OPCODE_DP4, /* X X X X X */ OPCODE_DPH, /* X X 1.1 */ @@ -188,6 +191,10 @@ typedef enum prog_opcode { OPCODE_NOISE2, /* X */ OPCODE_NOISE3, /* X */ OPCODE_NOISE4, /* X */ + OPCODE_NOT, /* */ + OPCODE_NRM3, /* */ + OPCODE_NRM4, /* */ + OPCODE_OR, /* */ OPCODE_PK2H, /* X */ OPCODE_PK2US, /* X */ OPCODE_PK4B, /* X */ @@ -226,13 +233,18 @@ typedef enum prog_opcode { OPCODE_UP4B, /* X */ OPCODE_UP4UB, /* X */ OPCODE_X2D, /* X */ + OPCODE_XOR, /* */ OPCODE_XPD, /* X X X */ MAX_OPCODE } gl_inst_opcode; -/* temporary, just in case, remove soon */ -#define OPCODE_INT OPCODE_TRUNC +/** + * Number of bits for the src/dst register Index field. + * This limits the size of temp/uniform register files. + */ +#define INST_INDEX_BITS 10 + /** * Instruction source register. @@ -240,7 +252,9 @@ typedef enum prog_opcode { struct prog_src_register { GLuint File:4; /**< One of the PROGRAM_* register file values. */ - GLint Index:9; /**< May be negative for relative addressing. */ + GLint Index:(INST_INDEX_BITS+1); /**< Extra bit here for sign bit. + * May be negative for relative addressing. + */ GLuint Swizzle:12; GLuint RelAddr:1; @@ -283,13 +297,10 @@ struct prog_src_register */ struct prog_dst_register { - /** - * One of the PROGRAM_* register file values. - */ - GLuint File:4; - - GLuint Index:8; + GLuint File:4; /**< One of the PROGRAM_* register file values */ + GLuint Index:INST_INDEX_BITS; /**< Unsigned, never negative */ GLuint WriteMask:4; + GLuint RelAddr:1; /** * \name Conditional destination update control. @@ -320,8 +331,7 @@ struct prog_dst_register */ GLuint CondSrc:1; /*@}*/ - - GLuint pad:31; + GLuint pad:28; }; @@ -416,11 +426,13 @@ struct prog_instruction */ GLint BranchTarget; +#if 01 /* XXX just use this for i965 driver for now! */ /** * For TEX instructions in shaders, the sampler to use for the * texture lookup. */ GLint Sampler; +#endif const char *Comment; };