X-Git-Url: https://git.libre-soc.org/?a=blobdiff_plain;f=src%2Fmesa%2Fx86%2Fcommon_x86.c;h=5efdb4f24a6a82064444d66b04d6c71c88296df2;hb=a531a5cf940a55d4438521fe394ae5395977bf3f;hp=c6b307e640c36657b4844fc685b94e6d636c756d;hpb=ab9e273c75e2d752e5027f7790480120c672ce01;p=mesa.git diff --git a/src/mesa/x86/common_x86.c b/src/mesa/x86/common_x86.c index c6b307e640c..5efdb4f24a6 100644 --- a/src/mesa/x86/common_x86.c +++ b/src/mesa/x86/common_x86.c @@ -1,10 +1,8 @@ -/* $Id: common_x86.c,v 1.9 2000/12/07 02:36:38 gareth Exp $ */ - /* * Mesa 3-D graphics library - * Version: 3.5 + * Version: 6.5.1 * - * Copyright (C) 1999-2000 Brian Paul All Rights Reserved. + * Copyright (C) 1999-2006 Brian Paul All Rights Reserved. * * Permission is hereby granted, free of charge, to any person obtaining a * copy of this software and associated documentation files (the "Software"), @@ -24,276 +22,272 @@ * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. */ - -/* +/** + * \file common_x86.c + * * Check CPU capabilities & initialize optimized funtions for this particular * processor. * - * Written by Holger Waechtler - * Changed by Andre Werthmann for using the - * new Katmai functions. + * Changed by Andre Werthmann for using the new SSE functions. + * + * \author Holger Waechtler + * \author Andre Werthmann */ -#include -#include -#if defined(USE_KATMAI_ASM) && defined(__linux__) && defined(_POSIX_SOURCE) -#include +/* XXX these includes should probably go into imports.h or glheader.h */ +#if defined(USE_SSE_ASM) && defined(__linux__) +#include +#endif +#if defined(USE_SSE_ASM) && defined(__FreeBSD__) +#include +#include +#endif +#if defined(USE_SSE_ASM) && defined(__OpenBSD__) +#include +#include +#include #endif -#include "context.h" +#include "main/imports.h" #include "common_x86_asm.h" -int gl_x86_cpu_features = 0; +/** Bitmask of X86_FEATURE_x bits */ +int _mesa_x86_cpu_features = 0x0; + + /* No reason for this to be public. */ -extern int gl_identify_x86_cpu_features( void ); - +extern GLuint _ASMAPI _mesa_x86_has_cpuid(void); +extern void _ASMAPI _mesa_x86_cpuid(GLuint op, GLuint *reg_eax, GLuint *reg_ebx, GLuint *reg_ecx, GLuint *reg_edx); +extern GLuint _ASMAPI _mesa_x86_cpuid_eax(GLuint op); +extern GLuint _ASMAPI _mesa_x86_cpuid_ebx(GLuint op); +extern GLuint _ASMAPI _mesa_x86_cpuid_ecx(GLuint op); +extern GLuint _ASMAPI _mesa_x86_cpuid_edx(GLuint op); -static void message( const char *msg ) -{ - GLboolean debug; -#ifdef DEBUG - debug = GL_TRUE; -#else - if ( getenv( "MESA_DEBUG" ) ) { - debug = GL_TRUE; - } else { - debug = GL_FALSE; - } -#endif - if ( debug ) { - fprintf( stderr, "%s", msg ); - } -} -#if defined(USE_KATMAI_ASM) +#if defined(USE_SSE_ASM) /* * We must verify that the Streaming SIMD Extensions are truly supported * on this processor before we go ahead and hook out the optimized code. - * Unfortunately, the CPUID bit isn't enough, as the OS must set the - * OSFXSR bit in CR4 if it supports the extended FPU save and restore - * required to use SSE. Unfortunately, we can't just go ahead and read - * this register, as only the kernel can do that. Similarly, we must - * verify that the OSXMMEXCPT bit in CR4 has been set by the OS, - * signifying that it supports unmasked SIMD FPU exceptions. If we take - * an unmasked exception and the OS doesn't correctly support them, the - * best we'll get is a SIGILL and the worst we'll get is an infinite - * loop in the signal delivery from the kernel as we can't interact with - * the SIMD FPU state to clear the exception bits. Either way, this is - * not good. + * + * However, I have been told by Alan Cox that all 2.4 (and later) Linux + * kernels provide full SSE support on all processors that expose SSE via + * the CPUID mechanism. */ -extern void gl_test_os_katmai_support( void ); -extern void gl_test_os_katmai_exception_support( void ); +/* These are assembly functions: */ +extern void _mesa_test_os_sse_support( void ); +extern void _mesa_test_os_sse_exception_support( void ); -#if defined(__linux__) && defined(_POSIX_SOURCE) -static void sigill_handler( int signal, struct sigcontext sc ) -{ - message( "SIGILL, " ); - - /* Both the "xorps %%xmm0,%%xmm0" and "divps %xmm0,%%xmm1" - * instructions are 3 bytes long. We must increment the instruction - * pointer manually to avoid repeated execution of the offending - * instruction. - * - * If the SIGILL is caused by a divide-by-zero when unmasked - * exceptions aren't supported, the SIMD FPU status and control - * word will be restored at the end of the test, so we don't need - * to worry about doing it here. Besides, we may not be able to... - */ - sc.eip += 3; - gl_x86_cpu_features &= ~(X86_FEATURE_XMM); -} - -static void sigfpe_handler( int signal, struct sigcontext sc ) +#if defined(WIN32) +#ifndef STATUS_FLOAT_MULTIPLE_TRAPS +# define STATUS_FLOAT_MULTIPLE_TRAPS (0xC00002B5L) +#endif +static LONG WINAPI ExceptionFilter(LPEXCEPTION_POINTERS exp) { - message( "SIGFPE, " ); - - if ( sc.fpstate->magic != 0xffff ) { - /* Our signal context has the extended FPU state, so reset the - * divide-by-zero exception mask and clear the divide-by-zero - * exception bit. - */ - sc.fpstate->mxcsr |= 0x00000200; - sc.fpstate->mxcsr &= 0xfffffffb; + PEXCEPTION_RECORD rec = exp->ExceptionRecord; + PCONTEXT ctx = exp->ContextRecord; + + if ( rec->ExceptionCode == EXCEPTION_ILLEGAL_INSTRUCTION ) { + _mesa_debug(NULL, "EXCEPTION_ILLEGAL_INSTRUCTION\n" ); + _mesa_x86_cpu_features &= ~(X86_FEATURE_XMM); + } else if ( rec->ExceptionCode == STATUS_FLOAT_MULTIPLE_TRAPS ) { + _mesa_debug(NULL, "STATUS_FLOAT_MULTIPLE_TRAPS\n"); + /* Windows seems to clear the exception flag itself, we just have to increment Eip */ } else { - /* If we ever get here, we're completely hosed. - */ - message( "\n\n" ); - gl_problem( NULL, "SSE enabling test failed badly!" ); + _mesa_debug(NULL, "UNEXPECTED EXCEPTION (0x%08x), terminating!\n" ); + return EXCEPTION_EXECUTE_HANDLER; } -} -#endif /* __linux__ && _POSIX_SOURCE */ -/* If we're running on a processor that can do SSE, let's see if we - * are allowed to or not. This will catch 2.4.0 or later kernels that - * haven't been configured for a Pentium III but are running on one, - * and RedHat patched 2.2 kernels that have broken exception handling - * support for user space apps that do SSE. - * - * GH: Isn't this just awful? - */ -static void check_os_katmai_support( void ) -{ -#if defined(__linux__) -#if defined(_POSIX_SOURCE) - struct sigaction saved_sigill; - struct sigaction saved_sigfpe; + if ( (ctx->ContextFlags & CONTEXT_CONTROL) != CONTEXT_CONTROL ) { + _mesa_debug(NULL, "Context does not contain control registers, terminating!\n"); + return EXCEPTION_EXECUTE_HANDLER; + } + ctx->Eip += 3; - /* Save the original signal handlers. - */ - sigaction( SIGILL, NULL, &saved_sigill ); - sigaction( SIGFPE, NULL, &saved_sigfpe ); + return EXCEPTION_CONTINUE_EXECUTION; +} +#endif /* WIN32 */ - signal( SIGILL, (void (*)(int))sigill_handler ); - signal( SIGFPE, (void (*)(int))sigfpe_handler ); - /* Emulate test for OSFXSR in CR4. The OS will set this bit if it - * supports the extended FPU save and restore required for SSE. If - * we execute an SSE instruction on a PIII and get a SIGILL, the OS - * doesn't support Streaming SIMD Exceptions, even if the processor - * does. - */ +/** + * Check if SSE is supported. + * If not, turn off the X86_FEATURE_XMM flag in _mesa_x86_cpu_features. + */ +void _mesa_check_os_sse_support( void ) +{ +#if defined(__FreeBSD__) + { + int ret, enabled; + unsigned int len; + len = sizeof(enabled); + ret = sysctlbyname("hw.instruction_sse", &enabled, &len, NULL, 0); + if (ret || !enabled) + _mesa_x86_cpu_features &= ~(X86_FEATURE_XMM); + } +#elif defined (__NetBSD__) + { + int ret, enabled; + size_t len = sizeof(enabled); + ret = sysctlbyname("machdep.sse", &enabled, &len, (void *)NULL, 0); + if (ret || !enabled) + _mesa_x86_cpu_features &= ~(X86_FEATURE_XMM); + } +#elif defined(__OpenBSD__) + { + int mib[2]; + int ret, enabled; + size_t len = sizeof(enabled); + + mib[0] = CTL_MACHDEP; + mib[1] = CPU_SSE; + + ret = sysctl(mib, 2, &enabled, &len, NULL, 0); + if (ret || !enabled) + _mesa_x86_cpu_features &= ~(X86_FEATURE_XMM); + } +#elif defined(WIN32) + LPTOP_LEVEL_EXCEPTION_FILTER oldFilter; + + /* Install our ExceptionFilter */ + oldFilter = SetUnhandledExceptionFilter( ExceptionFilter ); + if ( cpu_has_xmm ) { - message( "Testing OS support for SSE... " ); + _mesa_debug(NULL, "Testing OS support for SSE...\n"); - gl_test_os_katmai_support(); + _mesa_test_os_sse_support(); if ( cpu_has_xmm ) { - message( "yes.\n" ); + _mesa_debug(NULL, "Yes.\n"); } else { - message( "no!\n" ); + _mesa_debug(NULL, "No!\n"); } } - /* Emulate test for OSXMMEXCPT in CR4. The OS will set this bit if - * it supports unmasked SIMD FPU exceptions. If we unmask the - * exceptions, do a SIMD divide-by-zero and get a SIGILL, the OS - * doesn't support unmasked SIMD FPU exceptions. If we get a SIGFPE - * as expected, we're okay but we need to clean up after it. - * - * Are we being too stringent in our requirement that the OS support - * unmasked exceptions? Certain RedHat 2.2 kernels enable SSE by - * setting CR4.OSFXSR but don't support unmasked exceptions. Win98 - * doesn't even support them. We at least know the user-space SSE - * support is good in kernels that do support unmasked exceptions, - * and therefore to be safe I'm going to leave this test in here. - */ if ( cpu_has_xmm ) { - message( "Testing OS support for SSE unmasked exceptions... " ); + _mesa_debug(NULL, "Testing OS support for SSE unmasked exceptions...\n"); - gl_test_os_katmai_exception_support(); + _mesa_test_os_sse_exception_support(); if ( cpu_has_xmm ) { - message( "yes.\n" ); + _mesa_debug(NULL, "Yes.\n"); } else { - message( "no!\n" ); + _mesa_debug(NULL, "No!\n"); } } - /* Restore the original signal handlers. - */ - sigaction( SIGILL, &saved_sigill, NULL ); - sigaction( SIGFPE, &saved_sigfpe, NULL ); + /* Restore previous exception filter */ + SetUnhandledExceptionFilter( oldFilter ); - /* If we've gotten to here and the XMM CPUID bit is still set, we're - * safe to go ahead and hook out the SSE code throughout Mesa. - */ if ( cpu_has_xmm ) { - message( "Tests of OS support for SSE passed.\n" ); + _mesa_debug(NULL, "Tests of OS support for SSE passed.\n"); } else { - message( "Tests of OS support for SSE failed!\n" ); + _mesa_debug(NULL, "Tests of OS support for SSE failed!\n"); } #else - /* We can't use POSIX signal handling to test the availability of - * SSE, so we disable it by default. + /* Do nothing on other platforms for now. */ - message( "Cannot test OS support for SSE, disabling to be safe.\n" ); - gl_x86_cpu_features &= ~(X86_FEATURE_XMM); -#endif /* _POSIX_SOURCE */ -#else - /* Do nothing on non-Linux platforms for now. - */ - message( "Not testing OS support for SSE, leaving enabled.\n" ); -#endif /* __linux__ */ + _mesa_debug(NULL, "Not testing OS support for SSE, leaving enabled.\n"); +#endif /* __FreeBSD__ */ } -#endif /* USE_KATMAI_ASM */ +#endif /* USE_SSE_ASM */ -void gl_init_all_x86_transform_asm( void ) +/** + * Initialize the _mesa_x86_cpu_features bitfield. + * This is a no-op if called more than once. + */ +void +_mesa_get_x86_features(void) { + static int called = 0; + + if (called) + return; + + called = 1; + #ifdef USE_X86_ASM - gl_x86_cpu_features = gl_identify_x86_cpu_features(); + _mesa_x86_cpu_features = 0x0; - if ( getenv( "MESA_NO_ASM" ) ) { - gl_x86_cpu_features = 0; + if (_mesa_getenv( "MESA_NO_ASM")) { + return; } - if ( gl_x86_cpu_features ) { - gl_init_x86_transform_asm(); + if (!_mesa_x86_has_cpuid()) { + _mesa_debug(NULL, "CPUID not detected\n"); } + else { + GLuint cpu_features; + GLuint cpu_ext_features; + GLuint cpu_ext_info; + char cpu_vendor[13]; + GLuint result; + + /* get vendor name */ + _mesa_x86_cpuid(0, &result, (GLuint *)(cpu_vendor + 0), (GLuint *)(cpu_vendor + 8), (GLuint *)(cpu_vendor + 4)); + cpu_vendor[12] = '\0'; + + _mesa_debug(NULL, "CPU vendor: %s\n", cpu_vendor); + + /* get cpu features */ + cpu_features = _mesa_x86_cpuid_edx(1); + + if (cpu_features & X86_CPU_FPU) + _mesa_x86_cpu_features |= X86_FEATURE_FPU; + if (cpu_features & X86_CPU_CMOV) + _mesa_x86_cpu_features |= X86_FEATURE_CMOV; #ifdef USE_MMX_ASM - if ( cpu_has_mmx ) { - if ( getenv( "MESA_NO_MMX" ) == 0 ) { - message( "MMX cpu detected.\n" ); - } else { - gl_x86_cpu_features &= ~(X86_FEATURE_MMX); - } - } + if (cpu_features & X86_CPU_MMX) + _mesa_x86_cpu_features |= X86_FEATURE_MMX; #endif -#ifdef USE_3DNOW_ASM - if ( cpu_has_3dnow ) { - if ( getenv( "MESA_NO_3DNOW" ) == 0 ) { - message( "3DNow! cpu detected.\n" ); - gl_init_3dnow_transform_asm(); - } else { - gl_x86_cpu_features &= ~(X86_FEATURE_3DNOW); - } - } +#ifdef USE_SSE_ASM + if (cpu_features & X86_CPU_XMM) + _mesa_x86_cpu_features |= X86_FEATURE_XMM; + if (cpu_features & X86_CPU_XMM2) + _mesa_x86_cpu_features |= X86_FEATURE_XMM2; #endif -#ifdef USE_KATMAI_ASM - if ( cpu_has_xmm && getenv( "MESA_FORCE_KATMAI" ) == 0 ) { - check_os_katmai_support(); - } - if ( cpu_has_xmm ) { - if ( getenv( "MESA_NO_KATMAI" ) == 0 ) { - message( "Katmai cpu detected.\n" ); - gl_init_katmai_transform_asm(); - } else { - gl_x86_cpu_features &= ~(X86_FEATURE_XMM); - } - } -#endif -#endif -} + /* query extended cpu features */ + if ((cpu_ext_info = _mesa_x86_cpuid_eax(0x80000000)) > 0x80000000) { + if (cpu_ext_info >= 0x80000001) { -/* Note: the above function must be called before this one, so that - * gl_x86_cpu_features gets correctly initialized. - */ -void gl_init_all_x86_vertex_asm( void ) -{ -#ifdef USE_X86_ASM - if ( gl_x86_cpu_features ) { - gl_init_x86_vertex_asm(); - } + cpu_ext_features = _mesa_x86_cpuid_edx(0x80000001); + + if (cpu_features & X86_CPU_MMX) { #ifdef USE_3DNOW_ASM - if ( cpu_has_3dnow && getenv( "MESA_NO_3DNOW" ) == 0 ) { - gl_init_3dnow_vertex_asm(); - } + if (cpu_ext_features & X86_CPUEXT_3DNOW) + _mesa_x86_cpu_features |= X86_FEATURE_3DNOW; + if (cpu_ext_features & X86_CPUEXT_3DNOW_EXT) + _mesa_x86_cpu_features |= X86_FEATURE_3DNOWEXT; #endif -#ifdef USE_KATMAI_ASM - if ( cpu_has_xmm && getenv( "MESA_NO_KATMAI" ) == 0 ) { - gl_init_katmai_vertex_asm(); - } -#endif +#ifdef USE_MMX_ASM + if (cpu_ext_features & X86_CPUEXT_MMX_EXT) + _mesa_x86_cpu_features |= X86_FEATURE_MMXEXT; #endif + } + } + + /* query cpu name */ + if (cpu_ext_info >= 0x80000002) { + GLuint ofs; + char cpu_name[49]; + for (ofs = 0; ofs < 3; ofs++) + _mesa_x86_cpuid(0x80000002+ofs, (GLuint *)(cpu_name + (16*ofs)+0), (GLuint *)(cpu_name + (16*ofs)+4), (GLuint *)(cpu_name + (16*ofs)+8), (GLuint *)(cpu_name + (16*ofs)+12)); + cpu_name[48] = '\0'; /* the name should be NULL terminated, but just to be sure */ + + _mesa_debug(NULL, "CPU name: %s\n", cpu_name); + } + } + + } +#endif /* USE_X86_ASM */ }