X-Git-Url: https://git.libre-soc.org/?a=blobdiff_plain;f=src%2Fnmutil%2Flatch.py;fp=src%2Fnmutil%2Flatch.py;h=5f3a0c01edc73fa0bc2559da4378e94df9a62885;hb=2acd98076eb5a69c72cfbf6d00975b92e00be83c;hp=6bf6fd9979e0a8555b44983a883d90b07a3b09a6;hpb=3ed40da9845876864206f98de01f38de37a254cb;p=nmutil.git

diff --git a/src/nmutil/latch.py b/src/nmutil/latch.py
index 6bf6fd9..5f3a0c0 100644
--- a/src/nmutil/latch.py
+++ b/src/nmutil/latch.py
@@ -23,7 +23,7 @@ endmodule
 
 def latchregister(m, incoming, outgoing, settrue, name=None):
     reg = Signal.like(incoming, name=name) # make reg same as input. reset OK.
-    with m.If(settrue):
+    with m.If(settrue): # pass in some kind of expression/condition here
         m.d.sync += reg.eq(incoming)      # latch input into register
         m.d.comb += outgoing.eq(incoming) # return input (combinatorial)
     with m.Else():