X-Git-Url: https://git.libre-soc.org/?a=blobdiff_plain;f=src%2Fnmutil%2Flatch.py;fp=src%2Fnmutil%2Flatch.py;h=908c15cecf7ea77c955047934fa59704481adb9a;hb=d6cfdcf2350803ba55b350a0a0470bc91422ec40;hp=813ad64bd7318691560ca8c3740c81b2516307b5;hpb=8ec7414aac7ae73a6aefe7abfcd147c2c41c0ad0;p=nmutil.git

diff --git a/src/nmutil/latch.py b/src/nmutil/latch.py
index 813ad64..908c15c 100644
--- a/src/nmutil/latch.py
+++ b/src/nmutil/latch.py
@@ -1,3 +1,10 @@
+"""
+    This work is funded through NLnet under Grant 2019-02-012
+
+    License: LGPLv3+
+
+
+"""
 from nmigen.compat.sim import run_simulation
 from nmigen.cli import verilog, rtlil
 from nmigen import Record, Signal, Module, Const, Elaboratable, Mux