X-Git-Url: https://git.libre-soc.org/?a=blobdiff_plain;f=src%2Fopenpower%2Fdecoder%2Fdecode2execute1.py;h=efdf441cebd4dfc59cd9b4e1b68e457b5571e519;hb=7343a03846310ced878ab8b212016303eb7e0e66;hp=6333dcdf87641405b68fc438761cf222e7755d34;hpb=28221555c092a1411ce417878f17d4b2598a5c16;p=openpower-isa.git

diff --git a/src/openpower/decoder/decode2execute1.py b/src/openpower/decoder/decode2execute1.py
index 6333dcdf..efdf441c 100644
--- a/src/openpower/decoder/decode2execute1.py
+++ b/src/openpower/decoder/decode2execute1.py
@@ -5,10 +5,14 @@ based on Anton Blanchard microwatt decode2.vhdl
 """
 from nmigen import Signal, Record
 from nmutil.iocontrol import RecordObject
-from soc.decoder.power_enums import (MicrOp, CryIn, Function,
+from openpower.decoder.power_enums import (MicrOp, CryIn, Function,
                                      SPRfull, SPRreduced, LDSTMode)
-from soc.consts import TT
-from soc.experiment.mem_types import LDSTException
+from openpower.consts import TT
+from openpower.exceptions import LDSTException
+from openpower.decoder.power_svp64_rm import sv_input_record_layout
+from openpower.decoder.power_enums import asmlen
+
+from openpower.util import log
 
 
 class Data(Record):
@@ -37,11 +41,13 @@ class IssuerDecode2ToOperand(RecordObject):
 
     def __init__(self, name=None):
 
-        RecordObject.__init__(self, name=name)
+        RecordObject.__init__(self, layout=sv_input_record_layout,
+                                    name=name)
 
         # current "state" (TODO: this in its own Record)
         self.msr = Signal(64, reset_less=True)
         self.cia = Signal(64, reset_less=True)
+        self.svstate = Signal(64, reset_less=True)
 
         # instruction, type and decoded information
         self.insn = Signal(32, reset_less=True) # original instruction
@@ -98,7 +104,7 @@ class Decode2ToExecute1Type(RecordObject):
         RecordObject.__init__(self, name=name)
 
         if asmcode:
-            self.asmcode = Signal(8, reset_less=True) # only for simulator
+            self.asmcode = Signal(asmlen, reset_less=True) # only for simulator
         self.write_reg = Data(7, name="rego")
         self.write_ea = Data(7, name="ea") # for LD/ST in update mode
         self.read_reg1 = Data(7, name="reg1")
@@ -111,10 +117,13 @@ class Decode2ToExecute1Type(RecordObject):
         self.xer_in = Signal(3, reset_less=True)   # xer might be read
         self.xer_out = Signal(reset_less=True)  # xer might be written
 
+        # for the FAST regs (SRR1, SRR2, SVSRR0, CTR, LR etc.)
         self.read_fast1 = Data(3, name="fast1")
         self.read_fast2 = Data(3, name="fast2")
+        self.read_fast3 = Data(3, name="fast3")   # really only for SVSRR0
         self.write_fast1 = Data(3, name="fasto1")
         self.write_fast2 = Data(3, name="fasto2")
+        self.write_fast3 = Data(3, name="fasto3") # likewise
 
         self.read_cr1 = Data(7, name="cr_in1")
         self.read_cr2 = Data(7, name="cr_in2")
@@ -122,7 +131,7 @@ class Decode2ToExecute1Type(RecordObject):
         self.write_cr = Data(7, name="cr_out")
 
         # decode operand data
-        print ("decode2execute init", name, opkls, do)
+        log ("decode2execute init", name, opkls, do)
         #assert name is not None, str(opkls)
         if do is not None:
             self.do = do