X-Git-Url: https://git.libre-soc.org/?a=blobdiff_plain;f=src%2Fopenpower%2Fdecoder%2Fdecode2execute1.py;h=efdf441cebd4dfc59cd9b4e1b68e457b5571e519;hb=7343a03846310ced878ab8b212016303eb7e0e66;hp=cd012f6fa58f6ba9012f54df84adea618fe6a437;hpb=bb824753cdc455444e0b7accc47552eb41d3513d;p=openpower-isa.git

diff --git a/src/openpower/decoder/decode2execute1.py b/src/openpower/decoder/decode2execute1.py
index cd012f6f..efdf441c 100644
--- a/src/openpower/decoder/decode2execute1.py
+++ b/src/openpower/decoder/decode2execute1.py
@@ -10,9 +10,11 @@ from openpower.decoder.power_enums import (MicrOp, CryIn, Function,
 from openpower.consts import TT
 from openpower.exceptions import LDSTException
 from openpower.decoder.power_svp64_rm import sv_input_record_layout
+from openpower.decoder.power_enums import asmlen
 
 from openpower.util import log
 
+
 class Data(Record):
 
     def __init__(self, width, name):
@@ -45,7 +47,7 @@ class IssuerDecode2ToOperand(RecordObject):
         # current "state" (TODO: this in its own Record)
         self.msr = Signal(64, reset_less=True)
         self.cia = Signal(64, reset_less=True)
-        self.svstate = Signal(32, reset_less=True)
+        self.svstate = Signal(64, reset_less=True)
 
         # instruction, type and decoded information
         self.insn = Signal(32, reset_less=True) # original instruction
@@ -102,7 +104,7 @@ class Decode2ToExecute1Type(RecordObject):
         RecordObject.__init__(self, name=name)
 
         if asmcode:
-            self.asmcode = Signal(8, reset_less=True) # only for simulator
+            self.asmcode = Signal(asmlen, reset_less=True) # only for simulator
         self.write_reg = Data(7, name="rego")
         self.write_ea = Data(7, name="ea") # for LD/ST in update mode
         self.read_reg1 = Data(7, name="reg1")