X-Git-Url: https://git.libre-soc.org/?a=blobdiff_plain;f=src%2Fopenpower%2Fdecoder%2Fisa%2Ftest_caller_bcd.py;h=f9efcf43fd98aa908b7a7f5632a5592e50b36fc1;hb=e0518a4fa19ea3bba436154de8b7d66313caec28;hp=50141cbee9993b7969063baff0449f7fb266d748;hpb=3f9a6b3eb3856eae4af40ca9c29d89effc349e47;p=openpower-isa.git

diff --git a/src/openpower/decoder/isa/test_caller_bcd.py b/src/openpower/decoder/isa/test_caller_bcd.py
index 50141cbe..f9efcf43 100644
--- a/src/openpower/decoder/isa/test_caller_bcd.py
+++ b/src/openpower/decoder/isa/test_caller_bcd.py
@@ -1,19 +1,14 @@
-import itertools
 import random
 import re
-from nmigen import Module, Signal
-from nmigen.back.pysim import Simulator, Settle
 from nmutil.formaltest import FHDLTestCase
 import unittest
 
-from openpower.decoder.isa.caller import ISACaller
 from openpower.decoder.power_decoder import create_pdecode
 from openpower.decoder.power_decoder2 import (PowerDecode2)
 from openpower.simulator.program import Program
-from openpower.decoder.isa.caller import ISACaller, inject
 from openpower.decoder.selectable_int import SelectableInt
-from openpower.decoder.orderedset import OrderedSet
-from openpower.decoder.isa.all import ISA
+
+from openpower.decoder.isa.test_runner import run_tst
 
 
 # PowerISA Version 3.0C Book 1 App. B, Table 129
@@ -199,72 +194,7 @@ BCD_TO_DPD_PATTERN = (r"^(\d{2})_\s" +
 BCD_TO_DPD_REGEX = re.compile(BCD_TO_DPD_PATTERN, re.M)
 
 
-def run_tst(generator, initial_regs, initial_sprs=None, svstate=0, mmu=False,
-                                     initial_cr=0, mem=None,
-                                     initial_fprs=None,
-                                     pdecode2=None):
-    if initial_sprs is None:
-        initial_sprs = {}
-    m = Module()
-    comb = m.d.comb
-    instruction = Signal(32)
-
-    if pdecode2 is None:
-        pdecode = create_pdecode(include_fp=initial_fprs is not None)
-        pdecode2 = PowerDecode2(pdecode)
-
-    gen = list(generator.generate_instructions())
-    insncode = generator.assembly.splitlines()
-    instructions = list(zip(gen, insncode))
-
-    m.submodules.pdecode2 = pdecode2
-    simulator = ISA(pdecode2, initial_regs, initial_sprs, initial_cr,
-                    initial_insns=gen, respect_pc=True,
-                    initial_svstate=svstate,
-                    initial_mem=mem,
-                    fpregfile=initial_fprs,
-                    disassembly=insncode,
-                    bigendian=0,
-                    mmu=mmu)
-    comb += pdecode2.dec.raw_opcode_in.eq(instruction)
-    sim = Simulator(m)
-
-    def process():
-
-        print ("GPRs")
-        simulator.gpr.dump()
-        print ("FPRs")
-        simulator.fpr.dump()
-
-        yield pdecode2.dec.bigendian.eq(0)  # little / big?
-        pc = simulator.pc.CIA.value
-        index = pc//4
-        while index < len(instructions):
-            print("instr pc", pc)
-            try:
-                yield from simulator.setup_one()
-            except KeyError:  # indicates instruction not in imem: stop
-                break
-            yield Settle()
-
-            ins, code = instructions[index]
-            print("    0x{:X}".format(ins & 0xffffffff))
-            opname = code.split(' ')[0]
-            print(code, opname)
-
-            # ask the decoder to decode this binary data (endian'd)
-            yield from simulator.execute_one()
-            pc = simulator.pc.CIA.value
-            index = pc//4
-
-    sim.add_process(process)
-    with sim.write_vcd("simulator.vcd", "simulator.gtkw",
-                       traces=[]):
-        sim.run()
-    return simulator
-
-
-def testgen(mapping):
+def tstgen(mapping):
     zeros = [0] * 32
     length = len(mapping)
     iregs_whole = list(mapping.keys())
@@ -283,7 +213,7 @@ class BCDTestCase(FHDLTestCase):
 
     def run_tst(self, instr, mapping):
         lst = [f"{instr} {reg}, {reg}" for reg in range(32)]
-        for (iregs, oregs) in testgen(mapping):
+        for (iregs, oregs) in tstgen(mapping):
             with self.subTest():
                 with Program(lst, bigendian=False) as program:
                     sim = self.run_tst_program(program, iregs)
@@ -297,8 +227,8 @@ class BCDTestCase(FHDLTestCase):
             for digit in range(0x10):
                 dpd = int((match[0] + f"{digit:X}"), 16)
                 bcd = ((int(match[1 + digit][0]) << 8) |
-                        (int(match[1 + digit][1]) << 4) |
-                        (int(match[1 + digit][2]) << 0))
+                       (int(match[1 + digit][1]) << 4) |
+                       (int(match[1 + digit][2]) << 0))
                 mapping[dpd] = bcd
         self.run_tst("cdtbcd", mapping)
 
@@ -307,8 +237,8 @@ class BCDTestCase(FHDLTestCase):
         for match in BCD_TO_DPD_REGEX.findall(BCD_TO_DPD_TABLE):
             for digit in range(10):
                 bcd = ((int(match[0][0]) << 8) |
-                        (int(match[0][1]) << 4) |
-                        (int(digit) << 0))
+                       (int(match[0][1]) << 4) |
+                       (int(digit) << 0))
                 dpd = int(match[1 + digit], 16)
                 mapping[bcd] = dpd
         self.run_tst("cbcdtd", mapping)
@@ -336,8 +266,8 @@ class BCDTestCase(FHDLTestCase):
             return int("".join(map(str, reversed(addg6s))), 2)
 
         bcd = [f"{digit:04b}" for digit in range(10)]
-        rng10 = lambda: random.randrange(0, 10)
-        bcdrng = lambda: int("".join((bcd[rng10()] for _ in range(16))), 2)
+        def rng10(): return random.randrange(0, 10)
+        def bcdrng(): return int("".join((bcd[rng10()] for _ in range(16))), 2)
 
         lst = [f"addg6s {gpr}, {gpr + 0}, {gpr + 1}" for gpr in range(31)]
         oregs = [0] * 32
@@ -350,7 +280,7 @@ class BCDTestCase(FHDLTestCase):
                     sim = self.run_tst_program(program, iregs)
                     for gpr in range(31):
                         self.assertEqual(sim.gpr(gpr),
-                            SelectableInt(oregs[gpr], 64))
+                                         SelectableInt(oregs[gpr], 64))
 
     def run_tst_program(self, prog, initial_regs=[0] * 32):
         simulator = run_tst(prog, initial_regs, pdecode2=self.pdecode2)