X-Git-Url: https://git.libre-soc.org/?a=blobdiff_plain;f=src%2Fopenpower%2Fdecoder%2Fisa%2Ftest_caller_fp.py;h=b5f2bcec7a9e616e8d89fa73a7f7c4056b58fef8;hb=e0518a4fa19ea3bba436154de8b7d66313caec28;hp=a5e16b6baa13f54162ccb78d8038674265743a2f;hpb=8d81845d6808c843310472b623ec4b853f0b48e5;p=openpower-isa.git diff --git a/src/openpower/decoder/isa/test_caller_fp.py b/src/openpower/decoder/isa/test_caller_fp.py index a5e16b6b..b5f2bcec 100644 --- a/src/openpower/decoder/isa/test_caller_fp.py +++ b/src/openpower/decoder/isa/test_caller_fp.py @@ -38,6 +38,22 @@ class DecoderTestCase(FHDLTestCase): print("FPR 1", sim.fpr(1)) self.assertEqual(sim.fpr(1), SelectableInt(0x4040266660000000, 64)) + def test_fpload_imm(self): + """>>> lst = ["lfs 1, 8(1)", + ] + """ + lst = ["lfs 1, 8(1)", + ] + initial_mem = {0x0000: (0x42013333, 8), + 0x0008: (0x42026666, 8), + 0x0020: (0x1828384822324252, 8), + } + + with Program(lst, bigendian=False) as program: + sim = self.run_tst_program(program, initial_mem=initial_mem) + print("FPR 1", sim.fpr(1)) + self.assertEqual(sim.fpr(1), SelectableInt(0x40404cccc0000000, 64)) + def test_fpload2(self): """>>> lst = ["lfsx 1, 0, 0", ] @@ -56,7 +72,7 @@ class DecoderTestCase(FHDLTestCase): def test_fp_single_ldst(self): """>>> lst = ["lfsx 1, 1, 0", # load fp 1 from mem location 0 "stfsu 1, 16(1)", # store fp 1 into mem 0x10, update RA - "lfsu 2, 0(1)", # re-load from UPDATED r1 + "lfs 2, 0(1)", # re-load from UPDATED r1 ] """ lst = ["lfsx 1, 1, 0", @@ -77,6 +93,105 @@ class DecoderTestCase(FHDLTestCase): self.assertEqual(sim.fpr(1), SelectableInt(0x4040266660000000, 64)) self.assertEqual(sim.fpr(2), SelectableInt(0x4040266660000000, 64)) + def test_fp_single_ldst_update_idx(self): + """>>> lst = ["lfsx 1, 0, 0", # load fp 1 from mem location 0 + "stfsux 1, 2, 1", # store fp 1 into mem 0x10, update RA + "lfs 2, 0(2)", # re-load from UPDATED r2 + ] + """ + lst = ["lfsx 1, 0, 0", + "stfsux 1, 2, 1", + "lfs 2, 0(2)", + ] + initial_mem = {0x0000: (0x42013333, 8), + 0x0008: (0x42026666, 8), + 0x0020: (0x1828384822324252, 8), + } + # create an offset of 0x10 (2+3) + initial_regs = [0]*32 + initial_regs[1] = 0x4 + initial_regs[2] = 0xc + + with Program(lst, bigendian=False) as program: + sim = self.run_tst_program(program, initial_regs=initial_regs, + initial_mem=initial_mem) + print("FPR 1", sim.fpr(1)) + print("FPR 2", sim.fpr(2)) + print("GPR 1", sim.gpr(1)) # should be 0x4 + print("GPR 2", sim.gpr(2)) # should be 0x10 due to update + print("mem dump") + print(sim.mem.dump()) + self.assertEqual(sim.gpr(1), SelectableInt(0x4, 64)) + self.assertEqual(sim.gpr(2), SelectableInt(0x10, 64)) + self.assertEqual(sim.fpr(1), SelectableInt(0x4040266660000000, 64)) + self.assertEqual(sim.fpr(2), SelectableInt(0x4040266660000000, 64)) + + def test_fp_single_ldst_idx(self): + """>>> lst = ["lfsx 1, 0, 0", # load fp 1 from mem location 0 + "stfsx 1, 2, 1", # store fp 1 into mem 0x10, no update + "lfs 2, 4(2)", # re-load from NOT updated r2 + ] + """ + lst = ["lfsx 1, 0, 0", + "stfsx 1, 2, 1", + "lfs 2, 4(2)", + ] + initial_mem = {0x0000: (0x42013333, 8), + 0x0008: (0x42026666, 8), + 0x0020: (0x1828384822324252, 8), + } + # create an offset of 0x10 (2+3) + initial_regs = [0]*32 + initial_regs[1] = 0x4 + initial_regs[2] = 0xc + + with Program(lst, bigendian=False) as program: + sim = self.run_tst_program(program, initial_regs=initial_regs, + initial_mem=initial_mem) + print("FPR 1", sim.fpr(1)) + print("FPR 2", sim.fpr(2)) + print("GPR 1", sim.gpr(1)) # should be 0x4 + print("GPR 2", sim.gpr(2)) # should be 0xc (no update) + print("mem dump") + print(sim.mem.dump()) + self.assertEqual(sim.gpr(1), SelectableInt(0x4, 64)) + self.assertEqual(sim.gpr(2), SelectableInt(0xc, 64)) + self.assertEqual(sim.fpr(1), SelectableInt(0x4040266660000000, 64)) + self.assertEqual(sim.fpr(2), SelectableInt(0x4040266660000000, 64)) + + def test_fp_single_ldst_2(self): + """>>> lst = ["lfsx 1, 0, 0", # load fp 1 from mem location 0 + "stfs 1, 4(2)", # store fp 1 into mem 0x10, no update + "lfs 2, 4(2)", # re-load from NOT updated r2 + ] + """ + lst = ["lfsx 1, 0, 0", + "stfs 1, 4(2)", + "lfs 2, 4(2)", + ] + initial_mem = {0x0000: (0x42013333, 8), + 0x0008: (0x42026666, 8), + 0x0020: (0x1828384822324252, 8), + } + # create an offset of 0x10 (2+3) + initial_regs = [0]*32 + initial_regs[1] = 0x4 + initial_regs[2] = 0xc + + with Program(lst, bigendian=False) as program: + sim = self.run_tst_program(program, initial_regs=initial_regs, + initial_mem=initial_mem) + print("FPR 1", sim.fpr(1)) + print("FPR 2", sim.fpr(2)) + print("GPR 1", sim.gpr(1)) # should be 0x4 + print("GPR 2", sim.gpr(2)) # should be 0xc (no update) + print("mem dump") + print(sim.mem.dump()) + self.assertEqual(sim.gpr(1), SelectableInt(0x4, 64)) + self.assertEqual(sim.gpr(2), SelectableInt(0xc, 64)) + self.assertEqual(sim.fpr(1), SelectableInt(0x4040266660000000, 64)) + self.assertEqual(sim.fpr(2), SelectableInt(0x4040266660000000, 64)) + def test_fp_mv(self): """>>> lst = ["fmr 1, 2", ] @@ -176,6 +291,23 @@ class DecoderTestCase(FHDLTestCase): self.assertEqual(sim.fpr(2), SelectableInt(0x4040266660000000, 64)) self.assertEqual(sim.fpr(3), SelectableInt(0, 64)) + def test_fp_subs(self): + """>>> lst = ["fsubs 3, 1, 2", + ] + """ + lst = ["fsubs 3, 1, 2", # 0 - -32.3 = 32.3 + ] + + fprs = [0] * 32 + fprs[1] = 0x0 + fprs[2] = 0xC040266660000000 + + with Program(lst, bigendian=False) as program: + sim = self.run_tst_program(program, initial_fprs=fprs) + self.assertEqual(sim.fpr(1), SelectableInt(0x0, 64)) + self.assertEqual(sim.fpr(2), SelectableInt(0xC040266660000000, 64)) + self.assertEqual(sim.fpr(3), SelectableInt(0x4040266660000000, 64)) + def test_fp_add(self): """>>> lst = ["fadd 3, 1, 2", ] @@ -211,20 +343,51 @@ class DecoderTestCase(FHDLTestCase): self.assertEqual(sim.fpr(2), SelectableInt(0xC02399999999999A, 64)) self.assertEqual(sim.fpr(3), SelectableInt(0xc051266640000000, 64)) - def test_fp_muls2(self): + def test_fp_muls3(self): + """>>> lst = ["fmuls 3, 1, 2", + ] + """ + lst = ["fmuls 3, 1, 2", # + ] + + fprs = [0] * 32 + fprs[1] = 0xbfb0ab5100000000 + fprs[2] = 0xbdca000000000000 + + with Program(lst, bigendian=False) as program: + sim = self.run_tst_program(program, initial_fprs=fprs) + self.assertEqual(sim.fpr(3), SelectableInt(0x3d8b1663a0000000, 64)) + + def test_fp_muls4(self): + """>>> lst = ["fmuls 3, 1, 2", + ] + """ + lst = ["fmuls 3, 1, 2", # + ] + + fprs = [0] * 32 + fprs[1] = 0xbe724e2000000000 # negative number + fprs[2] = 0x0 # times zero + + with Program(lst, bigendian=False) as program: + sim = self.run_tst_program(program, initial_fprs=fprs) + # result should be -ve zero not +ve zero + self.assertEqual(sim.fpr(3), SelectableInt(0x8000000000000000, 64)) + + def test_fp_muls5(self): """>>> lst = ["fmuls 3, 1, 2", ] """ - lst = ["fmuls 3, 1, 2", # + lst = ["fmuls 3, 1, 2", # ] fprs = [0] * 32 - fprs[1] = 0xbfc4e9d700000000 - fprs[2] = 0xbdc5000000000000 + fprs[1] = 0xbfb0ab5100000000 + fprs[2] = 0xbdca000000000000 with Program(lst, bigendian=False) as program: sim = self.run_tst_program(program, initial_fprs=fprs) - self.assertEqual(sim.fpr(3), SelectableInt(0x3d9b72ea40000000, 64)) + self.assertEqual(sim.fpr(3), SelectableInt(0x3d8b1663a0000000, 64)) def test_fp_mul(self): """>>> lst = ["fmul 3, 1, 2", @@ -243,6 +406,38 @@ class DecoderTestCase(FHDLTestCase): self.assertEqual(sim.fpr(2), SelectableInt(0xC02399999999999A, 64)) self.assertEqual(sim.fpr(3), SelectableInt(0xC051266666666667, 64)) + def test_fp_madd1(self): + """>>> lst = ["fmadds 3, 1, 2, 4", + ] + """ + lst = ["fmadds 3, 1, 2, 4", # 7.0 * -9.8 + 2 = -66.6 + ] + + fprs = [0] * 32 + fprs[1] = 0x401C000000000000 # 7.0 + fprs[2] = 0xC02399999999999A # -9.8 + fprs[4] = 0x4000000000000000 # 2.0 + + with Program(lst, bigendian=False) as program: + sim = self.run_tst_program(program, initial_fprs=fprs) + self.assertEqual(sim.fpr(3), SelectableInt(0xC050A66660000000, 64)) + + def test_fp_msub1(self): + """>>> lst = ["fmsubs 3, 1, 2, 4", + ] + """ + lst = ["fmsubs 3, 1, 2, 4", # 7.0 * -9.8 + 2 = -70.6 + ] + + fprs = [0] * 32 + fprs[1] = 0x401C000000000000 # 7.0 + fprs[2] = 0xC02399999999999A # -9.8 + fprs[4] = 0x4000000000000000 # 2.0 + + with Program(lst, bigendian=False) as program: + sim = self.run_tst_program(program, initial_fprs=fprs) + self.assertEqual(sim.fpr(3), SelectableInt(0xc051a66660000000, 64)) + def test_fp_fcfids(self): """>>> lst = ["fcfids 1, 2", lst = ["fcfids 3, 4",