X-Git-Url: https://git.libre-soc.org/?a=blobdiff_plain;f=src%2Fopenpower%2Fdecoder%2Fpower_decoder.py;h=250cb9b2878796acb5abc3730595e2dbed8d9d3b;hb=f89e15664c9fdeb4ce257c9b72fcd151dc60dbd1;hp=229073242d731587d4476cca9bca695a54554f5c;hpb=55349e1f570d310c3194ff0f1723793871a76461;p=openpower-isa.git diff --git a/src/openpower/decoder/power_decoder.py b/src/openpower/decoder/power_decoder.py index 22907324..250cb9b2 100644 --- a/src/openpower/decoder/power_decoder.py +++ b/src/openpower/decoder/power_decoder.py @@ -87,16 +87,17 @@ Top Level: """ import gc -from collections import namedtuple -from nmigen import Module, Elaboratable, Signal, Cat, Mux -from nmigen.cli import rtlil +from collections import namedtuple, OrderedDict +from nmigen import Module, Elaboratable, Signal, Cat, Mux, Const +from nmigen.cli import rtlil, verilog from openpower.decoder.power_enums import (Function, Form, MicrOp, In1Sel, In2Sel, In3Sel, OutSel, SVEXTRA, SVEtype, SVPtype, # Simple-V RC, LdstLen, LDSTMode, CryIn, single_bit_flags, CRInSel, CROutSel, get_signal_name, - default_values, insns, asmidx) + default_values, insns, asmidx, + asmlen) from openpower.decoder.power_fields import DecodeFields from openpower.decoder.power_fieldsn import SigDecode, SignalBitRange from openpower.decoder.power_svp64 import SVP64RM @@ -120,7 +121,7 @@ Subdecoder = namedtuple( # fix autoformatter power_op_types = {'function_unit': Function, 'internal_op': MicrOp, 'form': Form, - 'asmcode': 8, + 'asmcode': asmlen, 'SV_Etype': SVEtype, 'SV_Ptype': SVPtype, 'in1_sel': In1Sel, @@ -183,7 +184,7 @@ class PowerOp: self.name = name self.subset = subset if fields is not None: - for k, v in fields: + for k, v in fields.items(): setattr(self, k, v) return debug_report = set() @@ -214,8 +215,9 @@ class PowerOp: """ fields = {} for fname in other._fields: - sig = getattr(other, fname) - fields[fname] = sig.__class__.like(sig) + sig = getattr(other, fname, None) + if sig is not None: + fields[fname] = sig.__class__.like(sig) return PowerOp(subset=other.subset, fields=fields) def _eq(self, row=None): @@ -318,9 +320,16 @@ class PowerDecoder(Elaboratable): the constructor is called. all quite messy. """ - def __init__(self, width, dec, name=None, col_subset=None, row_subset=None): + def __init__(self, width, dec, name=None, col_subset=None, + row_subset=None, conditions=None): + if conditions is None: + # XXX conditions = {} + conditions = {'SVP64BREV': Const(0, 1), + 'SVP64FFT': Const(0, 1), + } self.actually_does_something = False self.pname = name + self.conditions = conditions self.col_subset = col_subset self.row_subsetfn = row_subset if not isinstance(dec, list): @@ -332,8 +341,43 @@ class PowerDecoder(Elaboratable): for d in dec: if d.suffix is not None and d.suffix >= width: d.suffix = None + self.width = width + # create some case statement condition patterns for matching + # a single condition. "1----" for the first condition, + # "-1----" for the 2nd etc. + # also create a matching ordered list of conditions, for the switch, + # which will Cat() them together + self.ccases = {} + self.ckeys = list(conditions.keys()) + self.ckeys.sort() + + def find_conditions(self, opcodes): + # look for conditions, create dictionary entries for them + # sorted by opcode + rows = OrderedDict() # start as a dictionary, get as list (after) + for row in opcodes: + condition = row['CONDITIONS'] + opcode = row['opcode'] + if condition: + # check it's expected + assert (condition in self.conditions or + (condition[0] == '~' and + condition[1:] in self.conditions)), \ + "condition %s not in %s" % (condition, str(conditions)) + if opcode not in rows: + rows[opcode] = {} + rows[opcode][condition] = row + else: + # check it's unique + assert opcode not in rows, \ + "opcode %s already in rows for %s" % \ + (opcode, self.pname) + rows[opcode] = row + # after checking for conditions, get just the values (ordered) + return list(rows.values()) + def suffix_mask(self, d): return ((1 << d.suffix) - 1) @@ -370,6 +414,7 @@ class PowerDecoder(Elaboratable): eq.append(opcode_switch.eq(look_for)) if d.suffix: opcodes = self.divide_opcodes(d) + # TODO opcodes = self.find_conditions(opcodes) opc_in = Signal(d.suffix, reset_less=True) eq.append(opc_in.eq(opcode_switch[:d.suffix])) # begin the dynamic Switch statement here @@ -385,7 +430,8 @@ class PowerDecoder(Elaboratable): subdecoder = PowerDecoder(width=32, dec=sd, name=mname, col_subset=self.col_subset, - row_subset=self.row_subsetfn) + row_subset=self.row_subsetfn, + conditions=self.conditions) if not subdecoder.tree_analyse(): del subdecoder continue @@ -406,17 +452,34 @@ class PowerDecoder(Elaboratable): if seqs: case_does_something = True eq += seqs - for row in d.opcodes: - opcode = row['opcode'] + opcodes = self.find_conditions(d.opcodes) + for row in opcodes: + # urrr this is an awful hack. if "conditions" are active + # get the FIRST item (will be the same opcode), and it + # had BETTER have the same unit and also pass other + # row subset conditions. + if 'opcode' not in row: # must be a "CONDITIONS" dict... + is_conditions = True + _row = row[list(row.keys())[0]] + else: + is_conditions = False + _row = row + opcode = _row['opcode'] if d.opint and '-' not in opcode: opcode = int(opcode, 0) - if not row['unit']: + if not _row['unit']: continue if self.row_subsetfn: - if not self.row_subsetfn(opcode, row): + if not self.row_subsetfn(opcode, _row): continue # add in the dynamic Case statement here - switch_case[opcode] = self.op._eq(row) + if is_conditions: + switch_case[opcode] = {} + for k, crow in row.items(): + # log("ordered", k, crow) + switch_case[opcode][k] = self.op._eq(crow) + else: + switch_case[opcode] = self.op._eq(row) self.actually_does_something = True case_does_something = True @@ -446,7 +509,8 @@ class PowerDecoder(Elaboratable): subdecoder = PowerDecoder(self.width, dec, name=mname, col_subset=self.col_subset, - row_subset=self.row_subsetfn) + row_subset=self.row_subsetfn, + conditions=self.conditions) log ("subdecoder", mname, subdecoder) if not subdecoder.tree_analyse(): # doesn't do anything log ("analysed, DELETING", mname) @@ -474,9 +538,30 @@ class PowerDecoder(Elaboratable): with m.Switch(switch): for key, eqs in cases.items(): with m.Case(key): - comb += eqs + # "conditions" are a further switch statement + if isinstance(eqs, dict): + self.condition_switch(m, eqs) + else: + comb += eqs return m + def condition_switch(self, m, cases): + """against the global list of "conditions", having matched against + bits of the opcode, we FINALLY now have to match against some + additional "conditions". this is because there can be **MULTIPLE** + entries for a given opcode match. here we discern them. + """ + comb = m.d.comb + cswitch = [] + ccases = [] + for casekey, eqs in cases.items(): + if casekey.startswith('~'): + with m.If(~self.conditions[casekey[1:]]): + comb += eqs + else: + with m.If(self.conditions[casekey]): + comb += eqs + def ports(self): return [self.opcode_in] + self.op.ports() @@ -489,8 +574,10 @@ class TopPowerDecoder(PowerDecoder): (reverses byte order). See V3.0B p44 1.11.2 """ - def __init__(self, width, dec, name=None, col_subset=None, row_subset=None): - PowerDecoder.__init__(self, width, dec, name, col_subset, row_subset) + def __init__(self, width, dec, name=None, col_subset=None, + row_subset=None, conditions=None): + PowerDecoder.__init__(self, width, dec, name, + col_subset, row_subset, conditions) self.fields = df = DecodeFields(SignalBitRange, [self.opcode_in]) self.fields.create_specs() self.raw_opcode_in = Signal.like(self.opcode_in, reset_less=True) @@ -553,7 +640,10 @@ class TopPowerDecoder(PowerDecoder): return m def ports(self): - return [self.raw_opcode_in, self.bigendian] + PowerDecoder.ports(self) + res = [self.raw_opcode_in, self.bigendian] + PowerDecoder.ports(self) + for condition in self.conditions.values(): + res.append(condition) + return res ############################################################# @@ -608,7 +698,7 @@ def create_pdecode_svp64_ldst(name=None, col_subset=None, row_subset=None, # PRIMARY FUNCTION SPECIFYING THE FULL POWER DECODER def create_pdecode(name=None, col_subset=None, row_subset=None, - include_fp=False): + include_fp=False, conditions=None): """create_pdecode - creates a cascading hierarchical POWER ISA decoder subsetting of the PowerOp decoding is possible by setting col_subset @@ -669,7 +759,30 @@ def create_pdecode(name=None, col_subset=None, row_subset=None, bitsel=(0, 32), suffix=None, subdecoders=[])) return TopPowerDecoder(32, dec, name=name, col_subset=col_subset, - row_subset=row_subset) + row_subset=row_subset, + conditions=conditions) + +# test function from +#https://github.com/apertus-open-source-cinema/naps/blob/9ebbc0/naps/soc/cli.py#L17 +def fragment_repr(original): + from textwrap import indent + attrs_str = "\n" + for attr in ['ports', 'drivers', 'statements', 'attrs', + 'generated', 'flatten']: + attrs_str += f"{attr}={repr(getattr(original, attr))},\n" + + domains_str = "\n" + for name, domain in original.domains.items(): + # TODO: this is not really sound because domains could be non local + domains_str += f"{name}: {domain.name}\n" + attrs_str += f"domains={{{indent(domains_str, ' ')}}},\n" + + children_str = "\n" + for child, name in original.subfragments: + children_str += f"[{name}, {fragment_repr(child)}]\n" + attrs_str += f"children=[{indent(children_str, ' ')}],\n" + + return f"Fragment({indent(attrs_str, ' ')})" if __name__ == '__main__': @@ -679,24 +792,43 @@ if __name__ == '__main__': def rowsubsetfn(opcode, row): log("row_subset", opcode, row) - return row['unit'] == 'FPU' + return row['unit'] in ['LDST', 'FPU'] + conditions = {'SVP64BREV': Signal(name="svp64brev", reset_less=True), + 'SVP64FFT': Signal(name="svp64fft", reset_less=True), + } pdecode = create_pdecode(name="rowsub", col_subset={'opcode', 'function_unit', - 'form'}, + 'asmcode', + 'in2_sel', 'in3_sel'}, row_subset=rowsubsetfn, - include_fp=True) + include_fp=True, + conditions=conditions) vl = rtlil.convert(pdecode, ports=pdecode.ports()) with open("row_subset_decoder.il", "w") as f: f.write(vl) + vl = verilog.convert(pdecode, ports=pdecode.ports()) + with open("row_subset_decoder.v", "w") as f: + f.write(vl) + # col subset - pdecode = create_pdecode(name="fusubset", col_subset={'function_unit'}) + pdecode = create_pdecode(name="fusubset", col_subset={'function_unit'}, + conditions=conditions) vl = rtlil.convert(pdecode, ports=pdecode.ports()) with open("col_subset_decoder.il", "w") as f: f.write(vl) + from nmigen.hdl.ir import Fragment + elaborated = Fragment.get(pdecode, platform=None) + elaborated_repr = fragment_repr(elaborated) + print (elaborated_repr) + + exit(0) + + exit(0) + # full decoder pdecode = create_pdecode(include_fp=True) vl = rtlil.convert(pdecode, ports=pdecode.ports()) @@ -708,3 +840,5 @@ if __name__ == '__main__': vl = rtlil.convert(pdecode, ports=pdecode.ports()) with open("decoder_svp64.il", "w") as f: f.write(vl) + +