X-Git-Url: https://git.libre-soc.org/?a=blobdiff_plain;f=src%2Fopenpower%2Fdecoder%2Fpower_enums.py;h=2eef375801e3aee0badac50711507da07c787506;hb=a67c21910a83dbd7abdcdd106c0bae2d78baf212;hp=73bdcdafe0a6e5d3b2df504959d473d3af1bc267;hpb=ae34450b8a7cf417c4238eb070d3ac06227f4fa8;p=openpower-isa.git

diff --git a/src/openpower/decoder/power_enums.py b/src/openpower/decoder/power_enums.py
index 73bdcdaf..2eef3758 100644
--- a/src/openpower/decoder/power_enums.py
+++ b/src/openpower/decoder/power_enums.py
@@ -210,6 +210,15 @@ class SVEtype(Enum):
         return self.name
 
 
+@unique
+class SVmask_src(Enum):
+    NO = 0
+    EN = 1
+
+    def __repr__(self):
+        return self.name
+
+
 @unique
 class SVExtra(Enum):
     NONE = 0
@@ -270,11 +279,11 @@ class SVExtraReg(Enum):
     @classmethod
     def _missing_(cls, value):
         selectors = (
-            In1Sel, In2Sel, In3Sel, CRInSel,
+            In1Sel, In2Sel, In3Sel, CRInSel, CRIn2Sel,
             OutSel, CROutSel,
         )
         if isinstance(value, selectors):
-            return cls.__members__.get(value.name, cls.NONE)
+            return cls.__members__[value.name]
         return super()._missing_(value)
 
 
@@ -404,6 +413,74 @@ class RegType(Enum):
     BI = CR_BIT
     BT = CR_BIT
 
+    @classmethod
+    def _missing_(cls, value):
+        if isinstance(value, SVExtraReg):
+            return cls.__members__[value.name]
+        return super()._missing_(value)
+
+
+FPTRANS_INSNS = (
+    "fatan2", "fatan2s",
+    "fatan2pi", "fatan2pis",
+    "fpow", "fpows",
+    "fpown", "fpowns",
+    "fpowr", "fpowrs",
+    "frootn", "frootns",
+    "fhypot", "fhypots",
+    "frsqrt", "frsqrts",
+    "fcbrt", "fcbrts",
+    "frecip", "frecips",
+    "fexp2m1", "fexp2m1s",
+    "flog2p1", "flog2p1s",
+    "fexp2", "fexp2s",
+    "flog2", "flog2s",
+    "fexpm1", "fexpm1s",
+    "flogp1", "flogp1s",
+    "fexp", "fexps",
+    "flog", "flogs",
+    "fexp10m1", "fexp10m1s",
+    "flog10p1", "flog10p1s",
+    "fexp10", "fexp10s",
+    "flog10", "flog10s",
+    "fsin", "fsins",
+    "fcos", "fcoss",
+    "ftan", "ftans",
+    "fasin", "fasins",
+    "facos", "facoss",
+    "fatan", "fatans",
+    "fsinpi", "fsinpis",
+    "fcospi", "fcospis",
+    "ftanpi", "ftanpis",
+    "fasinpi", "fasinpis",
+    "facospi", "facospis",
+    "fatanpi", "fatanpis",
+    "fsinh", "fsinhs",
+    "fcosh", "fcoshs",
+    "ftanh", "ftanhs",
+    "fasinh", "fasinhs",
+    "facosh", "facoshs",
+    "fatanh", "fatanhs",
+    "fminnum08", "fminnum08s",
+    "fmaxnum08", "fmaxnum08s",
+    "fmin19", "fmin19s",
+    "fmax19", "fmax19s",
+    "fminnum19", "fminnum19s",
+    "fmaxnum19", "fmaxnum19s",
+    "fminc", "fmincs",
+    "fmaxc", "fmaxcs",
+    "fminmagnum08", "fminmagnum08s",
+    "fmaxmagnum08", "fmaxmagnum08s",
+    "fminmag19", "fminmag19s",
+    "fmaxmag19", "fmaxmag19s",
+    "fminmagnum19", "fminmagnum19s",
+    "fmaxmagnum19", "fmaxmagnum19s",
+    "fminmagc", "fminmagcs",
+    "fmaxmagc", "fmaxmagcs",
+    "fmod", "fmods",
+    "fremainder", "fremainders",
+)
+
 
 # supported instructions: make sure to keep up-to-date with CSV files
 # just like everything else
@@ -430,8 +507,11 @@ _insns = [
     "darn",
     "dcbf", "dcbst", "dcbt", "dcbtst", "dcbz",
     "divd", "divde", "divdeo", "divdeu",
-    "divdeuo", "divdo", "divdu", "divduo", "divw", "divwe", "divweo",
+    "divdeuo", "divdo", "divdu", "divduo",
+    "divmod2du",
+    "divw", "divwe", "divweo",
     "divweu", "divweuo", "divwo", "divwu", "divwuo",
+    "dsld", "dsrd",
     "eieio", "eqv",
     "extsb", "extsh", "extsw", "extswsli",
     "fadd", "fadds", "fsub", "fsubs",                   # FP add / sub
@@ -442,7 +522,6 @@ _insns = [
     "ffmsubs", "ffmadds", "ffnmsubs", "ffnmadds",       # FFT FP 3-arg
     "fmul", "fmuls", "fdiv", "fdivs",                   # FP mul / div
     "fmr", "fabs", "fnabs", "fneg", "fcpsgn",           # FP move/abs/neg
-    "fsins", "fcoss",                                   # FP SIN/COS
     "fmvis",                                            # FP load immediate
     "fishmv",                                           # Float Replace Lower-Half Single, Immediate
     'grev', 'grev.', 'grevi', 'grevi.',
@@ -462,6 +541,7 @@ _insns = [
     "lwz", "lwzcix", "lwzu", "lwzux", "lwzx",           # more load word
     # "lwabr",           # load word SVP64 bit-reversed
     # "lwzbr", "lwzubr", # more load word SVP64 bit-reversed
+    "maddedu",
     "maddhd", "maddhdu", "maddld",                      # INT multiply-and-add
     "mcrf", "mcrxr", "mcrxrx", "mfcr/mfocrf",           # CR mvs
     "mfmsr", "mfspr",
@@ -473,6 +553,7 @@ _insns = [
     "nand", "neg", "nego",
     "nop",
     "nor", "or", "orc", "ori", "oris",
+    "pcdec",
     "popcntb", "popcntd", "popcntw",
     "prtyd", "prtyw",
     "rfid",
@@ -503,6 +584,7 @@ _insns = [
     "tw", "twi",
     "wait",
     "xor", "xori", "xoris",
+    *FPTRANS_INSNS,
 ]
 
 # two-way lookup of instruction-to-index and vice-versa
@@ -615,6 +697,11 @@ class MicrOp(Enum):
     OP_SVINDEX = 95
     OP_FMVIS = 96
     OP_FISHMV = 97
+    OP_PCDEC = 98
+    OP_MADDEDU = 99
+    OP_DIVMOD2DU = 100
+    OP_DSHL = 101
+    OP_DSHR = 102
 
 
 @unique
@@ -672,6 +759,7 @@ class OutSel(Enum):
     RT_OR_ZERO = 4
     FRT = 5
     FRS = 6
+    RS = 7
 
 
 @unique
@@ -720,6 +808,13 @@ class CRInSel(Enum):
     BC = 5
     WHOLE_REG = 6
     CR1 = 7
+    BA = 8
+
+
+@unique
+class CRIn2Sel(Enum):
+    NONE = 0
+    BB = 1
 
 
 @unique