X-Git-Url: https://git.libre-soc.org/?a=blobdiff_plain;f=src%2Fopenpower%2Fdecoder%2Fpower_enums.py;h=86a9c28803400a881579412290cbb922309fb29a;hb=ae770cc6c2d648a020c8a0ed0447211933c25d3e;hp=c6dd9efa08f3ab44560a59b601aac0df2e026867;hpb=bf92502a9a005711f3fcdfc72168f1fa9a29ed74;p=openpower-isa.git

diff --git a/src/openpower/decoder/power_enums.py b/src/openpower/decoder/power_enums.py
index c6dd9efa..86a9c288 100644
--- a/src/openpower/decoder/power_enums.py
+++ b/src/openpower/decoder/power_enums.py
@@ -120,6 +120,7 @@ class Form(Enum):
     SVDS = 31  # Simple-V for LD/ST bit-reverse, variant of DS-Form
     SVM = 32  # Simple-V SHAPE mode - TEMPORARY TEMPORARY TEMPORARY
     SVRM = 33  # Simple-V REMAP mode - TEMPORARY TEMPORARY TEMPORARY
+    TLI = 34  # ternlogi
 
 # Simple-V svp64 fields https://libre-soc.org/openpower/sv/svp64/
 
@@ -329,6 +330,7 @@ _insns = [
     "subf", "subfc", "subfco", "subfe", "subfeo", "subfic",
     "subfme", "subfmeo", "subfo", "subfze", "subfzeo",
     "sync",
+    "ternlogi",
     "td", "tdi",
     "tlbie", "tlbiel",
     "tw", "twi",
@@ -433,6 +435,7 @@ class MicrOp(Enum):
     OP_ADDG6S = 83
     OP_CDTBCD = 84
     OP_CBCDTD = 85
+    OP_TERNLOG = 86
 
 
 @unique
@@ -475,6 +478,7 @@ class In3Sel(Enum):
     FRS = 3
     FRC = 4
     RC = 5  # for SVP64 bit-reverse LD/ST
+    RT = 6  # for ternlog[i]
 
 
 @unique