X-Git-Url: https://git.libre-soc.org/?a=blobdiff_plain;f=src%2Fopenpower%2Fdecoder%2Fpower_enums.py;h=eee86b949e7d18675b798caf6289f2152761223e;hb=c3b9973df8edcb1f6c1583c2da693336af7d1921;hp=2f124e2d6c27ed1c492a1413c1cdd79436405182;hpb=902007e3cd5c1151169c9d71906b897d3699f87a;p=openpower-isa.git

diff --git a/src/openpower/decoder/power_enums.py b/src/openpower/decoder/power_enums.py
index 2f124e2d..eee86b94 100644
--- a/src/openpower/decoder/power_enums.py
+++ b/src/openpower/decoder/power_enums.py
@@ -186,6 +186,35 @@ class SVP64RMMode(Enum):
     FFIRST = 2
     SATURATE = 3
     PREDRES = 4
+    BRANCH = 5
+
+
+@unique
+class SVP64BCPredMode(Enum):
+    NONE = 0
+    MASKZERO = 1
+    MASKONE = 2
+
+@unique
+class SVP64BCVLSETMode(Enum):
+    NONE = 0
+    VL_INCL = 1
+    VL_EXCL = 2
+
+
+# note that these are chosen to be exactly the same as
+# SVP64 RM bit 4.  ALL=1 => bit4=1
+@unique
+class SVP64BCGate(Enum):
+    ANY = 0
+    ALL = 1
+
+
+@unique
+class SVP64BCStep(Enum):
+    NONE = 0
+    STEP = 1
+    STEP_RC = 2
 
 
 @unique
@@ -216,7 +245,7 @@ class SVP64LDSTmode(Enum):
     INDEXED = 1
     ELSTRIDE = 2
     UNITSTRIDE = 3
-    BITREVERSE = 4
+    SHIFT = 4
 
 
 # supported instructions: make sure to keep up-to-date with CSV files
@@ -230,6 +259,7 @@ _insns = [
     "attn",
     "b", "bc", "bcctr", "bclr", "bctar",
     "bpermd",
+    "cbcdtd",
     "cdtbcd",
     "cmp", "cmpb", "cmpeqb", "cmpi", "cmpl", "cmpli", "cmprb",
     "cntlzd", "cntlzw", "cnttzd", "cnttzw",
@@ -401,6 +431,7 @@ class MicrOp(Enum):
     OP_SVSTEP = 82
     OP_ADDG6S = 83
     OP_CDTBCD = 84
+    OP_CBCDTD = 85
 
 
 @unique