X-Git-Url: https://git.libre-soc.org/?a=blobdiff_plain;f=src%2Fopenpower%2Fdecoder%2Fpower_svp64.py;h=ea7f465c9d4f299151e2785b80ab4665f2d87fe9;hb=7343a03846310ced878ab8b212016303eb7e0e66;hp=0fa44901d9b119d04fe7c0a3f956619d68fdffe7;hpb=99cf5b6d03171b50ecee780e143683141a1734a1;p=openpower-isa.git

diff --git a/src/openpower/decoder/power_svp64.py b/src/openpower/decoder/power_svp64.py
index 0fa44901..ea7f465c 100644
--- a/src/openpower/decoder/power_svp64.py
+++ b/src/openpower/decoder/power_svp64.py
@@ -3,6 +3,7 @@
 # Funded by NLnet http://nlnet.nl
 
 from openpower.decoder.power_enums import get_csv, find_wiki_dir
+from openpower.util import log
 import os
 
 # identifies register by type
@@ -37,12 +38,12 @@ def decode_extra(rm, prefix=''):
     dest_reg_cr, src_reg_cr = False, False
     svp64_srcreg_byname = {}
     svp64_destreg_byname = {}
+    log ("decode_extra RM", rm)
     for i in range(4):
-        print (rm)
         rfield = rm[prefix+str(i)]
         if not rfield or rfield == '0':
             continue
-        print ("EXTRA field", i, rfield)
+        log ("EXTRA field", i, rfield)
         rfield = rfield.split(";") # s:RA;d:CR1 etc.
         for r in rfield:
             rtype = r[0]
@@ -129,7 +130,7 @@ class SVP64RM:
                 extra_index = None
                 if regfield == 'RA_OR_ZERO':
                     regfield = 'RA'
-                print (asmcode, regfield, fname, svp64_dest, svp64_src)
+                log (asmcode, regfield, fname, svp64_dest, svp64_src)
                 # find the reg in the SVP64 extra map
                 if (fname in ['out', 'out2'] and regfield in svp64_dest):
                     extra_index = svp64_dest[regfield]