X-Git-Url: https://git.libre-soc.org/?a=blobdiff_plain;f=src%2Fopenpower%2Fdecoder%2Fpower_svp64.py;h=ea7f465c9d4f299151e2785b80ab4665f2d87fe9;hb=dcf4c64a66d5ed33fb10bcfcf65017bef39a4d0f;hp=167053c9b13214e1fa1a2883a8213100ca321d52;hpb=28221555c092a1411ce417878f17d4b2598a5c16;p=openpower-isa.git

diff --git a/src/openpower/decoder/power_svp64.py b/src/openpower/decoder/power_svp64.py
index 167053c9..ea7f465c 100644
--- a/src/openpower/decoder/power_svp64.py
+++ b/src/openpower/decoder/power_svp64.py
@@ -2,7 +2,8 @@
 # Copyright (C) 2021 Luke Kenneth Casson Leighton <lkcl@lkcl.net>
 # Funded by NLnet http://nlnet.nl
 
-from soc.decoder.power_enums import get_csv, find_wiki_dir
+from openpower.decoder.power_enums import get_csv, find_wiki_dir
+from openpower.util import log
 import os
 
 # identifies register by type
@@ -15,6 +16,9 @@ def is_CR_5bit(regname):
 def is_GPR(regname):
     return regname in ['RA', 'RB', 'RC', 'RS', 'RT']
 
+def is_FPR(regname):
+    return regname in ['FRA', 'FRB', 'FRC', 'FRS', 'FRT']
+
 def get_regtype(regname):
     if is_CR_3bit(regname):
         return "CR_3bit"
@@ -22,6 +26,8 @@ def get_regtype(regname):
         return "CR_5bit"
     if is_GPR(regname):
         return "GPR"
+    if is_FPR(regname):
+        return "FPR"
 
 
 def decode_extra(rm, prefix=''):
@@ -32,12 +38,12 @@ def decode_extra(rm, prefix=''):
     dest_reg_cr, src_reg_cr = False, False
     svp64_srcreg_byname = {}
     svp64_destreg_byname = {}
+    log ("decode_extra RM", rm)
     for i in range(4):
-        print (rm)
         rfield = rm[prefix+str(i)]
         if not rfield or rfield == '0':
             continue
-        print ("EXTRA field", i, rfield)
+        log ("EXTRA field", i, rfield)
         rfield = rfield.split(";") # s:RA;d:CR1 etc.
         for r in rfield:
             rtype = r[0]
@@ -124,7 +130,7 @@ class SVP64RM:
                 extra_index = None
                 if regfield == 'RA_OR_ZERO':
                     regfield = 'RA'
-                print (asmcode, regfield, fname, svp64_dest, svp64_src)
+                log (asmcode, regfield, fname, svp64_dest, svp64_src)
                 # find the reg in the SVP64 extra map
                 if (fname in ['out', 'out2'] and regfield in svp64_dest):
                     extra_index = svp64_dest[regfield]