X-Git-Url: https://git.libre-soc.org/?a=blobdiff_plain;f=src%2Fopenpower%2Fdecoder%2Fpower_svp64_rm.py;h=81527ad5a84b285856a5a11237d443881b94c69d;hb=4e7ac668cb9b87062897299b71bab3e6dcae647c;hp=654b9b5bd7b0742b80cd765feb67bb38dc948b2e;hpb=7a15248b5b5d51da38c4ba76beeb0cfdf6404693;p=openpower-isa.git

diff --git a/src/openpower/decoder/power_svp64_rm.py b/src/openpower/decoder/power_svp64_rm.py
index 654b9b5b..81527ad5 100644
--- a/src/openpower/decoder/power_svp64_rm.py
+++ b/src/openpower/decoder/power_svp64_rm.py
@@ -107,6 +107,7 @@ class SVP64RMModeDecode(Elaboratable):
         self.bc_vlset = Signal(SVP64BCVLSETMode) # Branch-Conditional VLSET
         self.bc_step = Signal(SVP64BCStep)   # Branch-Conditional svstep mode
         self.bc_pred = Signal(SVP64BCPredMode) # BC predicate mode
+        self.bc_vsb = Signal()                 # BC VLSET-branch (like BO[1])
         self.bc_gate = Signal(SVP64BCGate)     # BC ALL or ANY gate
         self.bc_lru  = Signal()                # BC Link Register Update
 
@@ -141,21 +142,23 @@ class SVP64RMModeDecode(Elaboratable):
         with m.If(is_bc):
             # Branch-Conditional is completely different
             # svstep mode
-            with m.If(mode2[0]):
+            with m.If(mode[SVP64MODE.BC_SVSTEP]):
                 with m.If(self.rm_in.ewsrc[0]):
                     comb += self.bc_step.eq(SVP64BCStep.STEP_RC)
                 with m.Else():
                     comb += self.bc_step.eq(SVP64BCStep.STEP)
             # VLSET mode
-            with m.If(mode2[1]):
-                with m.If(self.rm_in.ewsrc[1]):
-                    comb += self.bc_step.eq(SVP64BCVLSETMode.VL_INCL)
+            with m.If(mode[SVP64MODE.BC_VLSET]):
+                with m.If(mode[SVP64MODE.BC_VLI]):
+                    comb += self.bc_vlset.eq(SVP64BCVLSETMode.VL_INCL)
                 with m.Else():
-                    comb += self.bc_step.eq(SVP64BCVLSETMode.VL_EXCL)
+                    comb += self.bc_vlset.eq(SVP64BCVLSETMode.VL_EXCL)
             # BC Mode ALL or ANY (Great-Big-AND-gate or Great-Big-OR-gate)
             comb += self.bc_gate.eq(self.rm_in.elwidth[0])
             # Link-Register Update
             comb += self.bc_lru.eq(self.rm_in.elwidth[1])
+            comb += self.bc_vsb.eq(self.rm_in.ewsrc[1])
+
         with m.Else():
             # combined arith / ldst decoding due to similarity
             with m.Switch(mode2):