X-Git-Url: https://git.libre-soc.org/?a=blobdiff_plain;f=src%2Fopenpower%2Ftest%2Falu%2Fsvp64_cases.py;h=638da111a93d2865d75e7de65fb52476d5ecf634;hb=5025354342d8e92f200b9c0c0a04f96a53d7f0e3;hp=7867ef153028655e88e5f48238c682bef1acd977;hpb=fe012bf7aa3717834b4cd506be4187aaf366f1b4;p=openpower-isa.git diff --git a/src/openpower/test/alu/svp64_cases.py b/src/openpower/test/alu/svp64_cases.py index 7867ef15..638da111 100644 --- a/src/openpower/test/alu/svp64_cases.py +++ b/src/openpower/test/alu/svp64_cases.py @@ -2,18 +2,110 @@ from openpower.test.common import (TestAccumulatorBase, skip_case) from openpower.endian import bigendian from openpower.simulator.program import Program from openpower.decoder.isa.caller import SVP64State, CRFields -from openpower.sv.trans.svp64 import SVP64Asm +from openpower.insndb.asm import SVP64Asm +from openpower.test.state import ExpectedState +from copy import deepcopy + +class SVP64ALUElwidthTestCase(TestAccumulatorBase): + + def case_1_sv_add_ew8(self): + """>>> lst = ['sv.add/w=8 *1, *5, *9'] + """ + isa = SVP64Asm(['sv.add/w=8 *1, *5, *9']) + lst = list(isa) + print("listing", lst) + + # initial values in GPR regfile + initial_regs = [0] * 32 + initial_regs[9] = 0x1220 + initial_regs[5] = 0x43ff + # SVSTATE (in this case, VL=2) + svstate = SVP64State() + svstate.vl = 2 # VL + svstate.maxvl = 2 # MAXVL + print("SVSTATE", bin(svstate.asint())) + + # expected: each 8-bit add is completely independent + gprs = deepcopy(initial_regs) + gprs[1] = 0x551f # 0x12+0x43 = 0x55, 0x20+0xff = 0x1f (8-bit) + e = ExpectedState(pc=8, int_regs=gprs) + + self.add_case(Program(lst, bigendian), initial_regs, + initial_svstate=svstate, expected=e) + + + def case_2_sv_add_sw8(self): + """>>> lst = ['sv.add/sw=8 *1, *5, *9'] + """ + isa = SVP64Asm(['sv.add/sw=8 *1, *5, *9']) + lst = list(isa) + print("listing", lst) + + # initial values in GPR regfile + initial_regs = [0] * 32 + initial_regs[9] = 0x1220 + initial_regs[5] = 0x43ff + # SVSTATE (in this case, VL=2) + svstate = SVP64State() + svstate.vl = 2 # VL + svstate.maxvl = 2 # MAXVL + print("SVSTATE", bin(svstate.asint())) + + # expected: each 8-bit add is completely independent + gprs = deepcopy(initial_regs) + gprs[1] = 0x11f # 0x20+0xff = 0x11f (64-bit) + gprs[2] = 0x55 # 0x12+0x43 = 0x55 (64-bit) + e = ExpectedState(pc=8, int_regs=gprs) + + self.add_case(Program(lst, bigendian), initial_regs, + initial_svstate=svstate, expected=e) + + + def case_2_sv_add_ew32(self): + """>>> lst = ['sv.add/w=32 *1, *5, *9'] + """ + isa = SVP64Asm(['sv.add/w=32 *1, *5, *9']) + lst = list(isa) + print("listing", lst) + + # initial values in GPR regfile + initial_regs = [0] * 32 + initial_regs[9] = 0x1000_1000_f000_1220 + initial_regs[10] = 0x2000_2000_8000_1111 + initial_regs[5] = 0x8000_43ff + initial_regs[6] = 0x9000_0000_0000_2223 + initial_regs[2] = 0x0000_0001_0000_0002 + # SVSTATE (in this case, VL=2) + svstate = SVP64State() + svstate.vl = 3 # VL + svstate.maxvl = 3 # MAXVL + print("SVSTATE", bin(svstate.asint())) + + # expected: each 32-bit add is completely independent + gprs = deepcopy(initial_regs) + mask = 0xffff_ffff + # GPR(1) gets overwritten completely, lo-32 element 0, hi-32 element 1 + gprs[1] = ((initial_regs[9]&mask) + (initial_regs[5]&mask)) & mask + gprs[1] += (((initial_regs[9]>>32) + (initial_regs[5]>>32)) & mask)<<32 + # GPR(2) is only overwritten in the lo-32 (element 2). hi-32 untouched + gprs[2] &= ~mask + gprs[2] += ((initial_regs[10]&mask) + (initial_regs[6]&mask)) & mask + e = ExpectedState(pc=8, int_regs=gprs) + + self.add_case(Program(lst, bigendian), initial_regs, + initial_svstate=svstate, expected=e) class SVP64ALUTestCase(TestAccumulatorBase): def case_1_sv_add(self): - """>>> lst = ['sv.add 1.v, 5.v, 9.v'] + """>>> lst = ['sv.add *1, *5, *9'] + adds: - 1 = 5 + 9 => 0x5555 = 0x4321 + 0x1234 - 2 = 6 + 10 => 0x3334 = 0x2223 + 0x1111 + * 1 = 5 + 9 => 0x5555 = 0x4321 + 0x1234 + * 2 = 6 + 10 => 0x3334 = 0x2223 + 0x1111 """ - isa = SVP64Asm(['sv.add 1.v, 5.v, 9.v']) + isa = SVP64Asm(['sv.add *1, *5, *9']) lst = list(isa) print("listing", lst) @@ -25,17 +117,18 @@ class SVP64ALUTestCase(TestAccumulatorBase): initial_regs[6] = 0x2223 # SVSTATE (in this case, VL=2) svstate = SVP64State() - svstate.vl[0:7] = 2 # VL - svstate.maxvl[0:7] = 2 # MAXVL - print("SVSTATE", bin(svstate.spr.asint())) + svstate.vl = 2 # VL + svstate.maxvl = 2 # MAXVL + print("SVSTATE", bin(svstate.asint())) self.add_case(Program(lst, bigendian), initial_regs, initial_svstate=svstate) def case_2_sv_add_scalar(self): """>>> lst = ['sv.add 1, 5, 9'] + adds: - 1 = 5 + 9 => 0x5555 = 0x4321 + 0x1234 + * 1 = 5 + 9 => 0x5555 = 0x4321 + 0x1234 """ isa = SVP64Asm(['sv.add 1, 5, 9']) lst = list(isa) @@ -47,17 +140,18 @@ class SVP64ALUTestCase(TestAccumulatorBase): initial_regs[5] = 0x4321 svstate = SVP64State() # SVSTATE (in this case, VL=1, so everything works as in v3.0B) - svstate.vl[0:7] = 1 # VL - svstate.maxvl[0:7] = 1 # MAXVL - print("SVSTATE", bin(svstate.spr.asint())) + svstate.vl = 1 # VL + svstate.maxvl = 1 # MAXVL + print("SVSTATE", bin(svstate.asint())) self.add_case(Program(lst, bigendian), initial_regs, initial_svstate=svstate) def case_3_sv_check_extra(self): - """>>> lst = ['sv.add 13.v, 10.v, 7.v'] + """>>> lst = ['sv.add *13, *10, *7'] + adds: - 13 = 10 + 7 => 0x4242 = 0x1230 + 0x3012 + * 13 = 10 + 7 => 0x4242 = 0x1230 + 0x3012 This case helps checking the encoding of the Extra field It was built so the v3.0b registers are: 3, 2, 1 @@ -65,7 +159,7 @@ class SVP64ALUTestCase(TestAccumulatorBase): The expected SVP64 register numbers are: 13, 10, 7 Any mistake in decoding will probably give a different answer """ - isa = SVP64Asm(['sv.add 13.v, 10.v, 7.v']) + isa = SVP64Asm(['sv.add *13, *10, *7']) lst = list(isa) print("listing", lst) @@ -75,20 +169,21 @@ class SVP64ALUTestCase(TestAccumulatorBase): initial_regs[10] = 0x1230 svstate = SVP64State() # SVSTATE (in this case, VL=1, so everything works as in v3.0B) - svstate.vl[0:7] = 1 # VL - svstate.maxvl[0:7] = 1 # MAXVL - print("SVSTATE", bin(svstate.spr.asint())) + svstate.vl = 1 # VL + svstate.maxvl = 1 # MAXVL + print("SVSTATE", bin(svstate.asint())) self.add_case(Program(lst, bigendian), initial_regs, initial_svstate=svstate) def case_4_sv_add_(self): - """>>> lst = ['sv.add. 1.v, 5.v, 9.v'] + """>>> lst = ['sv.add. *1, *5, *9'] + adds when Rc=1: TODO CRs higher up - 1 = 5 + 9 => 0 = -1+1 CR0=0b100 - 2 = 6 + 10 => 0x3334 = 0x2223+0x1111 CR1=0b010 + * 1 = 5 + 9 => 0 = -1+1 CR0=0b100 + * 2 = 6 + 10 => 0x3334 = 0x2223+0x1111 CR1=0b010 """ - isa = SVP64Asm(['sv.add. 1.v, 5.v, 9.v']) + isa = SVP64Asm(['sv.add. *1, *5, *9']) lst = list(isa) print("listing", lst) @@ -101,23 +196,24 @@ class SVP64ALUTestCase(TestAccumulatorBase): # SVSTATE (in this case, VL=2) svstate = SVP64State() - svstate.vl[0:7] = 2 # VL - svstate.maxvl[0:7] = 2 # MAXVL - print("SVSTATE", bin(svstate.spr.asint())) + svstate.vl = 2 # VL + svstate.maxvl = 2 # MAXVL + print("SVSTATE", bin(svstate.asint())) self.add_case(Program(lst, bigendian), initial_regs, initial_svstate=svstate) def case_5_sv_check_vl_0(self): """>>> lst = [ - 'sv.add 13.v, 10.v, 7.v', # skipped, because VL == 0 + 'sv.add *13, *10, *7', # skipped, because VL == 0 'add 1, 5, 9' ] + adds: - 1 = 5 + 9 => 0x5555 = 0x4321 + 0x1234 + * 1 = 5 + 9 => 0x5555 = 0x4321 + 0x1234 """ isa = SVP64Asm([ - 'sv.add 13.v, 10.v, 7.v', # skipped, because VL == 0 + 'sv.add *13, *10, *7', # skipped, because VL == 0 'add 1, 5, 9' ]) lst = list(isa) @@ -131,9 +227,9 @@ class SVP64ALUTestCase(TestAccumulatorBase): initial_regs[10] = 0x1230 svstate = SVP64State() # SVSTATE (in this case, VL=0, so vector instructions are skipped) - svstate.vl[0:7] = 0 # VL - svstate.maxvl[0:7] = 0 # MAXVL - print("SVSTATE", bin(svstate.spr.asint())) + svstate.vl = 0 # VL + svstate.maxvl = 0 # MAXVL + print("SVSTATE", bin(svstate.asint())) self.add_case(Program(lst, bigendian), initial_regs, initial_svstate=svstate) @@ -141,20 +237,21 @@ class SVP64ALUTestCase(TestAccumulatorBase): # checks that SRCSTEP was reset properly after an SV instruction def case_6_sv_add_multiple(self): """>>> lst = [ - 'sv.add 1.v, 5.v, 9.v', - 'sv.add 13.v, 10.v, 7.v' + 'sv.add *1, *5, *9', + 'sv.add *13, *10, *7' ] + adds: - 1 = 5 + 9 => 0x5555 = 0x4321 + 0x1234 - 2 = 6 + 10 => 0x3334 = 0x2223 + 0x1111 - 3 = 7 + 11 => 0x4242 = 0x3012 + 0x1230 - 13 = 10 + 7 => 0x2341 = 0x1111 + 0x1230 - 14 = 11 + 8 => 0x3012 = 0x3012 + 0x0000 - 15 = 12 + 9 => 0x1234 = 0x0000 + 0x1234 + * 1 = 5 + 9 => 0x5555 = 0x4321 + 0x1234 + * 2 = 6 + 10 => 0x3334 = 0x2223 + 0x1111 + * 3 = 7 + 11 => 0x4242 = 0x3012 + 0x1230 + * 13 = 10 + 7 => 0x2341 = 0x1111 + 0x1230 + * 14 = 11 + 8 => 0x3012 = 0x3012 + 0x0000 + * 15 = 12 + 9 => 0x1234 = 0x0000 + 0x1234 """ isa = SVP64Asm([ - 'sv.add 1.v, 5.v, 9.v', - 'sv.add 13.v, 10.v, 7.v' + 'sv.add *1, *5, *9', + 'sv.add *13, *10, *7' ]) lst = list(isa) print("listing", lst) @@ -169,20 +266,21 @@ class SVP64ALUTestCase(TestAccumulatorBase): initial_regs[7] = 0x1230 # SVSTATE (in this case, VL=3) svstate = SVP64State() - svstate.vl[0:7] = 3 # VL - svstate.maxvl[0:7] = 3 # MAXVL - print("SVSTATE", bin(svstate.spr.asint())) + svstate.vl = 3 # VL + svstate.maxvl = 3 # MAXVL + print("SVSTATE", bin(svstate.asint())) self.add_case(Program(lst, bigendian), initial_regs, initial_svstate=svstate) def case_7_sv_add_2(self): - """>>> lst = ['sv.add 1, 5.v, 9.v'] + """>>> lst = ['sv.add 1, *5, *9'] + adds: - 1 = 5 + 9 => 0x5555 = 0x4321 + 0x1234 + * 1 = 5 + 9 => 0x5555 = 0x4321 + 0x1234 """ # r1 is scalar so ENDS EARLY - isa = SVP64Asm(['sv.add 1, 5.v, 9.v']) + isa = SVP64Asm(['sv.add 1, *5, *9']) lst = list(isa) print("listing", lst) @@ -194,20 +292,20 @@ class SVP64ALUTestCase(TestAccumulatorBase): initial_regs[6] = 0x2223 # SVSTATE (in this case, VL=2) svstate = SVP64State() - svstate.vl[0:7] = 2 # VL - svstate.maxvl[0:7] = 2 # MAXVL - print("SVSTATE", bin(svstate.spr.asint())) + svstate.vl = 2 # VL + svstate.maxvl = 2 # MAXVL + print("SVSTATE", bin(svstate.asint())) self.add_case(Program(lst, bigendian), initial_regs, initial_svstate=svstate) def case_8_sv_add_3(self): - """>>> lst = ['sv.add 1.v, 5, 9.v'] + """>>> lst = ['sv.add *1, 5, *9'] adds: - 1 = 5 + 9 => 0x5555 = 0x4321+0x1234 - 2 = 5 + 10 => 0x5432 = 0x4321+0x1111 + * 1 = 5 + 9 => 0x5555 = 0x4321+0x1234 + * 2 = 5 + 10 => 0x5432 = 0x4321+0x1111 """ - isa = SVP64Asm(['sv.add 1.v, 5, 9.v']) + isa = SVP64Asm(['sv.add *1, 5, *9']) lst = list(isa) print("listing", lst) @@ -219,16 +317,16 @@ class SVP64ALUTestCase(TestAccumulatorBase): initial_regs[6] = 0x2223 # SVSTATE (in this case, VL=2) svstate = SVP64State() - svstate.vl[0:7] = 2 # VL - svstate.maxvl[0:7] = 2 # MAXVL - print("SVSTATE", bin(svstate.spr.asint())) + svstate.vl = 2 # VL + svstate.maxvl = 2 # MAXVL + print("SVSTATE", bin(svstate.asint())) self.add_case(Program(lst, bigendian), initial_regs, initial_svstate=svstate) def case_13_sv_predicated_add(self): """>>> lst = [ - 'sv.add/m=r30 1.v, 5.v, 9.v', - 'sv.add/m=~r30 13.v, 10.v, 7.v' + 'sv.add/m=r30 *1, *5, *9', + 'sv.add/m=~r30 *13, *10, *7' ] checks integer predication using mask-invertmask. @@ -237,18 +335,18 @@ class SVP64ALUTestCase(TestAccumulatorBase): mask was set up as part of a parallel If-Then-Else) first add: - 1 = 5 + 9 => 0x5555 = 0x4321 + 0x1234 - 2 = 0 (skipped) - 3 = 7 + 11 => 0x4242 = 0x3012 + 0x1230 + * 1 = 5 + 9 => 0x5555 = 0x4321 + 0x1234 + * 2 = 0 (skipped) + * 3 = 7 + 11 => 0x4242 = 0x3012 + 0x1230 second add: - 13 = 0 (skipped) - 14 = 11 + 8 => 0xB063 = 0x3012 + 0x8051 - 15 = 0 (skipped) + * 13 = 0 (skipped) + * 14 = 11 + 8 => 0xB063 = 0x3012 + 0x8051 + * 15 = 0 (skipped) """ isa = SVP64Asm([ - 'sv.add/m=r30 1.v, 5.v, 9.v', - 'sv.add/m=~r30 13.v, 10.v, 7.v' + 'sv.add/m=r30 *1, *5, *9', + 'sv.add/m=~r30 *13, *10, *7' ]) lst = list(isa) print("listing", lst) @@ -265,17 +363,17 @@ class SVP64ALUTestCase(TestAccumulatorBase): initial_regs[8] = 0x8051 # SVSTATE (in this case, VL=3) svstate = SVP64State() - svstate.vl[0:7] = 3 # VL - svstate.maxvl[0:7] = 3 # MAXVL - print("SVSTATE", bin(svstate.spr.asint())) + svstate.vl = 3 # VL + svstate.maxvl = 3 # MAXVL + print("SVSTATE", bin(svstate.asint())) self.add_case(Program(lst, bigendian), initial_regs, initial_svstate=svstate) def case_14_intpred_all_zeros_all_ones(self): """>>> lst = [ - 'sv.add/m=r30 1.v, 5.v, 9.v', - 'sv.add/m=~r30 13.v, 10.v, 7.v' + 'sv.add/m=r30 *1, *5, *9', + 'sv.add/m=~r30 *13, *10, *7' ] checks an instruction with no effect (all mask bits are zeros). @@ -284,18 +382,18 @@ class SVP64ALUTestCase(TestAccumulatorBase): Vector operations with a fully-zero mask. first add: - 1 = 0 (skipped) - 2 = 0 (skipped) - 3 = 0 (skipped) + * 1 = 0 (skipped) + * 2 = 0 (skipped) + * 3 = 0 (skipped) second add: - 13 = 10 + 7 => 0x2341 = 0x1111 + 0x1230 - 14 = 11 + 8 => 0xB063 = 0x3012 + 0x8051 - 15 = 12 + 9 => 0x7736 = 0x6502 + 0x1234 + * 13 = 10 + 7 => 0x2341 = 0x1111 + 0x1230 + * 14 = 11 + 8 => 0xB063 = 0x3012 + 0x8051 + * 15 = 12 + 9 => 0x7736 = 0x6502 + 0x1234 """ isa = SVP64Asm([ - 'sv.add/m=r30 1.v, 5.v, 9.v', - 'sv.add/m=~r30 13.v, 10.v, 7.v' + 'sv.add/m=r30 *1, *5, *9', + 'sv.add/m=~r30 *13, *10, *7' ]) lst = list(isa) print("listing", lst) @@ -313,25 +411,25 @@ class SVP64ALUTestCase(TestAccumulatorBase): initial_regs[8] = 0x8051 # SVSTATE (in this case, VL=3) svstate = SVP64State() - svstate.vl[0:7] = 3 # VL - svstate.maxvl[0:7] = 3 # MAXVL - print("SVSTATE", bin(svstate.spr.asint())) + svstate.vl = 3 # VL + svstate.maxvl = 3 # MAXVL + print("SVSTATE", bin(svstate.asint())) self.add_case(Program(lst, bigendian), initial_regs, initial_svstate=svstate) def case_18_sv_add_cr_pred(self): - """>>> lst = ['sv.add/m=ne 1.v, 5.v, 9.v'] + """>>> lst = ['sv.add/m=ne *1, *5, *9'] adds, CR predicated mask CR4.eq = 1, CR5.eq = 0, invert (ne) - 1 = 5 + 9 => not to be touched (skipped) - 2 = 6 + 10 => 0x3334 = 0x2223+0x1111 + * 1 = 5 + 9 => not to be touched (skipped) + * 2 = 6 + 10 => 0x3334 = 0x2223+0x1111 expected results: - r1 = 0xbeef skipped since CR4 is 1 and test is inverted - r2 = 0x3334 CR5 is 0, so this is used + * r1 = 0xbeef skipped since CR4 is 1 and test is inverted + * r2 = 0x3334 CR5 is 0, so this is used """ - isa = SVP64Asm(['sv.add/m=ne 1.v, 5.v, 9.v']) + isa = SVP64Asm(['sv.add/m=ne *1, *5, *9']) lst = list(isa) print("listing", lst) @@ -344,9 +442,9 @@ class SVP64ALUTestCase(TestAccumulatorBase): initial_regs[6] = 0x2223 # SVSTATE (in this case, VL=2) svstate = SVP64State() - svstate.vl[0:7] = 2 # VL - svstate.maxvl[0:7] = 2 # MAXVL - print("SVSTATE", bin(svstate.spr.asint())) + svstate.vl = 2 # VL + svstate.maxvl = 2 # MAXVL + print("SVSTATE", bin(svstate.asint())) # set up CR predicate - CR4.eq=1 and CR5.eq=0 cr = 0b0010 << ((7-4)*4) # CR4.eq (we hope)