X-Git-Url: https://git.libre-soc.org/?a=blobdiff_plain;f=src%2Fopenpower%2Ftest%2Frunner.py;h=4068d1ab10c117f348ff0dc8eca62ed7c276fd59;hb=e3b46c6ec7911d08b8b0c4cb3c286c3786dae2ef;hp=5282c1e69f46430b1a41bd464b5a5597fbd0b8c6;hpb=2266e253f673809ec0f322f0e03f038439d4da5d;p=openpower-isa.git

diff --git a/src/openpower/test/runner.py b/src/openpower/test/runner.py
index 5282c1e6..4068d1ab 100644
--- a/src/openpower/test/runner.py
+++ b/src/openpower/test/runner.py
@@ -48,8 +48,10 @@ class SimRunner(StateRunner):
         self.dut = dut
 
         self.mmu = pspec.mmu == True
+        fp_en = pspec.fp_en == True
         regreduce_en = pspec.regreduce_en == True
-        self.simdec2 = simdec2 = PowerDecode2(None, regreduce_en=regreduce_en)
+        self.simdec2 = simdec2 = PowerDecode2(
+            None, regreduce_en=regreduce_en, fp_en=fp_en)
         m.submodules.simdec2 = simdec2  # pain in the neck
 
     def prepare_for_test(self, test):
@@ -71,7 +73,8 @@ class SimRunner(StateRunner):
                   disassembly=insncode,
                   bigendian=bigendian,
                   initial_svstate=test.svstate,
-                  mmu=self.mmu)
+                  mmu=self.mmu,
+                  fpregfile=test.fpregs)
 
         # run the loop of the instructions on the current test
         index = sim.pc.CIA.value//4
@@ -127,7 +130,7 @@ class TestRunnerBase(FHDLTestCase):
 
     def __init__(self, tst_data, microwatt_mmu=False, rom=None,
                  svp64=True, run_hdl=None, run_sim=True,
-                 allow_overlap=False, inorder=False):
+                 allow_overlap=False, inorder=False, fp=False):
         super().__init__("run_all")
         self.test_data = tst_data
         self.microwatt_mmu = microwatt_mmu
@@ -137,6 +140,7 @@ class TestRunnerBase(FHDLTestCase):
         self.inorder = inorder
         self.run_hdl = run_hdl
         self.run_sim = run_sim
+        self.fp = fp
 
     def run_all(self):
         m = Module()
@@ -170,7 +174,8 @@ class TestRunnerBase(FHDLTestCase):
                      allow_overlap=self.allow_overlap,
                      inorder=self.inorder,
                      mmu=self.microwatt_mmu,
-                     reg_wid=64)
+                     reg_wid=64,
+                     fp_en=self.fp)
 
         ###### SETUP PHASE #######
         # Determine the simulations needed and add to state_list
@@ -254,7 +259,7 @@ class TestRunnerBase(FHDLTestCase):
                         kind=LogKind.InstrInOuts)
                     log("sprs", test.sprs, kind=LogKind.InstrInOuts)
                     log("cr", test.cr, kind=LogKind.InstrInOuts)
-                    log("mem", test.mem, kind=LogKind.InstrInOuts)
+                    log("mem", test.mem)
                     log("msr", test.msr, kind=LogKind.InstrInOuts)
 
                     def format_assembly(assembly):
@@ -529,7 +534,7 @@ class TestRunnerBase(FHDLTestCase):
 
         write_gtkw("%s.gtkw" % gtkname,
                    "%s.vcd" % gtkname,
-                   traces, styles, module='top.issuer')
+                   traces, styles, module='bench.top.issuer')
 
         # add run of instructions
         sim.add_sync_process(process)