X-Git-Url: https://git.libre-soc.org/?a=blobdiff_plain;f=src%2Fsim%2Fpseudo_inst.cc;h=8ffb13e3b33025653c3cf58f7a0b333c901a3271;hb=abd33d6fd26bb69d3bf53ceb6c2dc8f90d893e34;hp=2264958479b3ca72fc11a82fe1cead405c3a05e4;hpb=9eda6b1d88a4bdd466964065dd6009bdcedfcb92;p=gem5.git diff --git a/src/sim/pseudo_inst.cc b/src/sim/pseudo_inst.cc index 226495847..8ffb13e3b 100644 --- a/src/sim/pseudo_inst.cc +++ b/src/sim/pseudo_inst.cc @@ -1,5 +1,5 @@ /* - * Copyright (c) 2010 ARM Limited + * Copyright (c) 2010-2012, 2015, 2017 ARM Limited * All rights reserved * * The license below extends only to copyright in the software and shall @@ -11,6 +11,7 @@ * unmodified and in its entirety in all distributions of the software, * modified or unmodified, in source code or in binary form. * + * Copyright (c) 2011 Advanced Micro Devices, Inc. * Copyright (c) 2003-2006 The Regents of The University of Michigan * All rights reserved. * @@ -40,36 +41,44 @@ * Authors: Nathan Binkert */ +#include "sim/pseudo_inst.hh" + #include #include #include #include #include +#include +#include + +#include "arch/pseudo_inst.hh" +#include "arch/utility.hh" #include "arch/vtophys.hh" #include "base/debug.hh" -#include "config/full_system.hh" +#include "base/output.hh" #include "config/the_isa.hh" #include "cpu/base.hh" #include "cpu/quiesce_event.hh" #include "cpu/thread_context.hh" #include "debug/Loader.hh" +#include "debug/PseudoInst.hh" #include "debug/Quiesce.hh" #include "debug/WorkItems.hh" +#include "dev/net/dist_iface.hh" +#include "kern/kernel_stats.hh" #include "params/BaseCPU.hh" -#include "sim/pseudo_inst.hh" +#include "sim/full_system.hh" +#include "sim/initparam_keys.hh" +#include "sim/process.hh" #include "sim/serialize.hh" #include "sim/sim_events.hh" #include "sim/sim_exit.hh" #include "sim/stat_control.hh" #include "sim/stats.hh" #include "sim/system.hh" - -#if FULL_SYSTEM -#include "arch/kernel_stats.hh" #include "sim/vptr.hh" -#endif using namespace std; @@ -78,113 +87,213 @@ using namespace TheISA; namespace PseudoInst { -#if FULL_SYSTEM - -void -arm(ThreadContext *tc) +static inline void +panicFsOnlyPseudoInst(const char *name) { - if (tc->getKernelStats()) - tc->getKernelStats()->arm(); + panic("Pseudo inst \"%s\" is only available in Full System mode."); } -void -quiesce(ThreadContext *tc) +uint64_t +pseudoInst(ThreadContext *tc, uint8_t func, uint8_t subfunc) { - if (!tc->getCpuPtr()->params()->do_quiesce) - return; + uint64_t args[4]; + + DPRINTF(PseudoInst, "PseudoInst::pseudoInst(%i, %i)\n", func, subfunc); + + // We need to do this in a slightly convoluted way since + // getArgument() might have side-effects on arg_num. We could have + // used the Argument class, but due to the possible side effects + // from getArgument, it'd most likely break. + int arg_num(0); + for (int i = 0; i < sizeof(args) / sizeof(*args); ++i) { + args[arg_num] = getArgument(tc, arg_num, sizeof(uint64_t), false); + ++arg_num; + } - DPRINTF(Quiesce, "%s: quiesce()\n", tc->getCpuPtr()->name()); + switch (func) { + case M5OP_ARM: + arm(tc); + break; - tc->suspend(); - if (tc->getKernelStats()) - tc->getKernelStats()->quiesce(); -} + case M5OP_QUIESCE: + quiesce(tc); + break; -void -quiesceSkip(ThreadContext *tc) -{ - BaseCPU *cpu = tc->getCpuPtr(); + case M5OP_QUIESCE_NS: + quiesceNs(tc, args[0]); + break; - if (!cpu->params()->do_quiesce) - return; + case M5OP_QUIESCE_CYCLE: + quiesceCycles(tc, args[0]); + break; - EndQuiesceEvent *quiesceEvent = tc->getQuiesceEvent(); + case M5OP_QUIESCE_TIME: + return quiesceTime(tc); - Tick resume = curTick() + 1; + case M5OP_RPNS: + return rpns(tc); - cpu->reschedule(quiesceEvent, resume, true); + case M5OP_WAKE_CPU: + wakeCPU(tc, args[0]); + break; - DPRINTF(Quiesce, "%s: quiesceSkip() until %d\n", - cpu->name(), resume); + case M5OP_EXIT: + m5exit(tc, args[0]); + break; - tc->suspend(); - if (tc->getKernelStats()) - tc->getKernelStats()->quiesce(); -} + case M5OP_FAIL: + m5fail(tc, args[0], args[1]); + break; -void -quiesceNs(ThreadContext *tc, uint64_t ns) -{ - BaseCPU *cpu = tc->getCpuPtr(); + case M5OP_INIT_PARAM: + return initParam(tc, args[0], args[1]); - if (!cpu->params()->do_quiesce || ns == 0) - return; + case M5OP_LOAD_SYMBOL: + loadsymbol(tc); + break; - EndQuiesceEvent *quiesceEvent = tc->getQuiesceEvent(); + case M5OP_RESET_STATS: + resetstats(tc, args[0], args[1]); + break; - Tick resume = curTick() + SimClock::Int::ns * ns; + case M5OP_DUMP_STATS: + dumpstats(tc, args[0], args[1]); + break; - cpu->reschedule(quiesceEvent, resume, true); + case M5OP_DUMP_RESET_STATS: + dumpresetstats(tc, args[0], args[1]); + break; - DPRINTF(Quiesce, "%s: quiesceNs(%d) until %d\n", - cpu->name(), ns, resume); + case M5OP_CHECKPOINT: + m5checkpoint(tc, args[0], args[1]); + break; - tc->suspend(); - if (tc->getKernelStats()) - tc->getKernelStats()->quiesce(); + case M5OP_WRITE_FILE: + return writefile(tc, args[0], args[1], args[2], args[3]); + + case M5OP_READ_FILE: + return readfile(tc, args[0], args[1], args[2]); + + case M5OP_DEBUG_BREAK: + debugbreak(tc); + break; + + case M5OP_SWITCH_CPU: + switchcpu(tc); + break; + + case M5OP_ADD_SYMBOL: + addsymbol(tc, args[0], args[1]); + break; + + case M5OP_PANIC: + panic("M5 panic instruction called at %s\n", tc->pcState()); + + case M5OP_WORK_BEGIN: + workbegin(tc, args[0], args[1]); + break; + + case M5OP_WORK_END: + workend(tc, args[0], args[1]); + break; + + case M5OP_ANNOTATE: + case M5OP_RESERVED2: + case M5OP_RESERVED3: + case M5OP_RESERVED4: + case M5OP_RESERVED5: + warn("Unimplemented m5 op (0x%x)\n", func); + break; + + /* SE mode functions */ + case M5OP_SE_SYSCALL: + m5Syscall(tc); + break; + + case M5OP_SE_PAGE_FAULT: + m5PageFault(tc); + break; + + /* dist-gem5 functions */ + case M5OP_DIST_TOGGLE_SYNC: + togglesync(tc); + break; + + default: + warn("Unhandled m5 op: 0x%x\n", func); + break; + } + + return 0; } void -quiesceCycles(ThreadContext *tc, uint64_t cycles) +arm(ThreadContext *tc) { - BaseCPU *cpu = tc->getCpuPtr(); - - if (!cpu->params()->do_quiesce || cycles == 0) - return; + DPRINTF(PseudoInst, "PseudoInst::arm()\n"); + if (!FullSystem) + panicFsOnlyPseudoInst("arm"); - EndQuiesceEvent *quiesceEvent = tc->getQuiesceEvent(); + if (tc->getKernelStats()) + tc->getKernelStats()->arm(); +} - Tick resume = curTick() + cpu->ticks(cycles); +void +quiesce(ThreadContext *tc) +{ + DPRINTF(PseudoInst, "PseudoInst::quiesce()\n"); + tc->quiesce(); +} - cpu->reschedule(quiesceEvent, resume, true); +void +quiesceSkip(ThreadContext *tc) +{ + DPRINTF(PseudoInst, "PseudoInst::quiesceSkip()\n"); + tc->quiesceTick(tc->getCpuPtr()->nextCycle() + 1); +} - DPRINTF(Quiesce, "%s: quiesceCycles(%d) until %d\n", - cpu->name(), cycles, resume); +void +quiesceNs(ThreadContext *tc, uint64_t ns) +{ + DPRINTF(PseudoInst, "PseudoInst::quiesceNs(%i)\n", ns); + tc->quiesceTick(curTick() + SimClock::Int::ns * ns); +} - tc->suspend(); - if (tc->getKernelStats()) - tc->getKernelStats()->quiesce(); +void +quiesceCycles(ThreadContext *tc, uint64_t cycles) +{ + DPRINTF(PseudoInst, "PseudoInst::quiesceCycles(%i)\n", cycles); + tc->quiesceTick(tc->getCpuPtr()->clockEdge(Cycles(cycles))); } uint64_t quiesceTime(ThreadContext *tc) { + DPRINTF(PseudoInst, "PseudoInst::quiesceTime()\n"); + return (tc->readLastActivate() - tc->readLastSuspend()) / SimClock::Int::ns; } -#endif - uint64_t rpns(ThreadContext *tc) { + DPRINTF(PseudoInst, "PseudoInst::rpns()\n"); return curTick() / SimClock::Int::ns; } void wakeCPU(ThreadContext *tc, uint64_t cpuid) { + DPRINTF(PseudoInst, "PseudoInst::wakeCPU(%i)\n", cpuid); System *sys = tc->getSystemPtr(); + + if (sys->numContexts() <= cpuid) { + warn("PseudoInst::wakeCPU(%i), cpuid greater than number of contexts" + "(%i)\n",cpuid, sys->numContexts()); + return; + } + ThreadContext *other_tc = sys->threadContexts[cpuid]; if (other_tc->status() == ThreadContext::Suspended) other_tc->activate(); @@ -193,15 +302,28 @@ wakeCPU(ThreadContext *tc, uint64_t cpuid) void m5exit(ThreadContext *tc, Tick delay) { - Tick when = curTick() + delay * SimClock::Int::ns; - exitSimLoop("m5_exit instruction encountered", 0, when); + DPRINTF(PseudoInst, "PseudoInst::m5exit(%i)\n", delay); + if (DistIface::readyToExit(delay)) { + Tick when = curTick() + delay * SimClock::Int::ns; + exitSimLoop("m5_exit instruction encountered", 0, when, 0, true); + } } -#if FULL_SYSTEM +void +m5fail(ThreadContext *tc, Tick delay, uint64_t code) +{ + DPRINTF(PseudoInst, "PseudoInst::m5fail(%i, %i)\n", delay, code); + Tick when = curTick() + delay * SimClock::Int::ns; + exitSimLoop("m5_fail instruction encountered", code, when, 0, true); +} void loadsymbol(ThreadContext *tc) { + DPRINTF(PseudoInst, "PseudoInst::loadsymbol()\n"); + if (!FullSystem) + panicFsOnlyPseudoInst("loadsymbol"); + const string &filename = tc->getCpuPtr()->system->params()->symbolfile; if (filename.empty()) { return; @@ -250,6 +372,11 @@ loadsymbol(ThreadContext *tc) void addsymbol(ThreadContext *tc, Addr addr, Addr symbolAddr) { + DPRINTF(PseudoInst, "PseudoInst::addsymbol(0x%x, 0x%x)\n", + addr, symbolAddr); + if (!FullSystem) + panicFsOnlyPseudoInst("addSymbol"); + char symb[100]; CopyStringOut(tc, symb, symbolAddr, 100); std::string symbol(symb); @@ -261,17 +388,54 @@ addsymbol(ThreadContext *tc, Addr addr, Addr symbolAddr) } uint64_t -initParam(ThreadContext *tc) +initParam(ThreadContext *tc, uint64_t key_str1, uint64_t key_str2) { - return tc->getCpuPtr()->system->init_param; -} + DPRINTF(PseudoInst, "PseudoInst::initParam() key:%s%s\n", (char *)&key_str1, + (char *)&key_str2); + if (!FullSystem) { + panicFsOnlyPseudoInst("initParam"); + return 0; + } -#endif + // The key parameter string is passed in via two 64-bit registers. We copy + // out the characters from the 64-bit integer variables here and concatenate + // them in the key_str character buffer + const int len = 2 * sizeof(uint64_t) + 1; + char key_str[len]; + memset(key_str, '\0', len); + if (key_str1 == 0) { + assert(key_str2 == 0); + } else { + strncpy(key_str, (char *)&key_str1, sizeof(uint64_t)); + } + + if (strlen(key_str) == sizeof(uint64_t)) { + strncpy(key_str + sizeof(uint64_t), (char *)&key_str2, + sizeof(uint64_t)); + } else { + assert(key_str2 == 0); + } + + // Compare the key parameter with the known values to select the return + // value + uint64_t val; + if (strcmp(key_str, InitParamKey::DEFAULT) == 0) { + val = tc->getCpuPtr()->system->init_param; + } else if (strcmp(key_str, InitParamKey::DIST_RANK) == 0) { + val = DistIface::rankParam(); + } else if (strcmp(key_str, InitParamKey::DIST_SIZE) == 0) { + val = DistIface::sizeParam(); + } else { + panic("Unknown key for initparam pseudo instruction:\"%s\"", key_str); + } + return val; +} void resetstats(ThreadContext *tc, Tick delay, Tick period) { + DPRINTF(PseudoInst, "PseudoInst::resetstats(%i, %i)\n", delay, period); if (!tc->getCpuPtr()->params()->do_statistics_insts) return; @@ -285,6 +449,7 @@ resetstats(ThreadContext *tc, Tick delay, Tick period) void dumpstats(ThreadContext *tc, Tick delay, Tick period) { + DPRINTF(PseudoInst, "PseudoInst::dumpstats(%i, %i)\n", delay, period); if (!tc->getCpuPtr()->params()->do_statistics_insts) return; @@ -298,6 +463,7 @@ dumpstats(ThreadContext *tc, Tick delay, Tick period) void dumpresetstats(ThreadContext *tc, Tick delay, Tick period) { + DPRINTF(PseudoInst, "PseudoInst::dumpresetstats(%i, %i)\n", delay, period); if (!tc->getCpuPtr()->params()->do_statistics_insts) return; @@ -311,20 +477,27 @@ dumpresetstats(ThreadContext *tc, Tick delay, Tick period) void m5checkpoint(ThreadContext *tc, Tick delay, Tick period) { + DPRINTF(PseudoInst, "PseudoInst::m5checkpoint(%i, %i)\n", delay, period); if (!tc->getCpuPtr()->params()->do_checkpoint_insts) return; - Tick when = curTick() + delay * SimClock::Int::ns; - Tick repeat = period * SimClock::Int::ns; - - exitSimLoop("checkpoint", 0, when, repeat); + if (DistIface::readyToCkpt(delay, period)) { + Tick when = curTick() + delay * SimClock::Int::ns; + Tick repeat = period * SimClock::Int::ns; + exitSimLoop("checkpoint", 0, when, repeat); + } } -#if FULL_SYSTEM - uint64_t readfile(ThreadContext *tc, Addr vaddr, uint64_t len, uint64_t offset) { + DPRINTF(PseudoInst, "PseudoInst::readfile(0x%x, 0x%x, 0x%x)\n", + vaddr, len, offset); + if (!FullSystem) { + panicFsOnlyPseudoInst("readfile"); + return 0; + } + const string &file = tc->getSystemPtr()->params()->readfile; if (file.empty()) { return ULL(0); @@ -357,133 +530,188 @@ readfile(ThreadContext *tc, Addr vaddr, uint64_t len, uint64_t offset) return result; } -#endif +uint64_t +writefile(ThreadContext *tc, Addr vaddr, uint64_t len, uint64_t offset, + Addr filename_addr) +{ + DPRINTF(PseudoInst, "PseudoInst::writefile(0x%x, 0x%x, 0x%x, 0x%x)\n", + vaddr, len, offset, filename_addr); + + // copy out target filename + char fn[100]; + std::string filename; + CopyStringOut(tc, fn, filename_addr, 100); + filename = std::string(fn); + + OutputStream *out; + if (offset == 0) { + // create a new file (truncate) + out = simout.create(filename, true, true); + } else { + // do not truncate file if offset is non-zero + // (ios::in flag is required as well to keep the existing data + // intact, otherwise existing data will be zeroed out.) + out = simout.open(filename, ios::in | ios::out | ios::binary, true); + } + + ostream *os(out->stream()); + if (!os) + panic("could not open file %s\n", filename); + + // seek to offset + os->seekp(offset); + + // copy out data and write to file + char *buf = new char[len]; + CopyOut(tc, buf, vaddr, len); + os->write(buf, len); + if (os->fail() || os->bad()) + panic("Error while doing writefile!\n"); + + simout.close(out); + + delete [] buf; + + return len; +} void debugbreak(ThreadContext *tc) { + DPRINTF(PseudoInst, "PseudoInst::debugbreak()\n"); Debug::breakpoint(); } void switchcpu(ThreadContext *tc) { + DPRINTF(PseudoInst, "PseudoInst::switchcpu()\n"); exitSimLoop("switchcpu"); } +void +togglesync(ThreadContext *tc) +{ + DPRINTF(PseudoInst, "PseudoInst::togglesync()\n"); + DistIface::toggleSync(tc); +} + // -// This function is executed when annotated work items begin. Depending on +// This function is executed when annotated work items begin. Depending on // what the user specified at the command line, the simulation may exit and/or // take a checkpoint when a certain work item begins. // void workbegin(ThreadContext *tc, uint64_t workid, uint64_t threadid) { - tc->getCpuPtr()->workItemBegin(); + DPRINTF(PseudoInst, "PseudoInst::workbegin(%i, %i)\n", workid, threadid); System *sys = tc->getSystemPtr(); + const System::Params *params = sys->params(); - DPRINTF(WorkItems, "Work Begin workid: %d, threadid %d\n", workid, + if (params->exit_on_work_items) { + exitSimLoop("workbegin", static_cast(workid)); + return; + } + + DPRINTF(WorkItems, "Work Begin workid: %d, threadid %d\n", workid, threadid); + tc->getCpuPtr()->workItemBegin(); + sys->workItemBegin(threadid, workid); // // If specified, determine if this is the specific work item the user // identified // - if (sys->params()->work_item_id == -1 || - sys->params()->work_item_id == workid) { + if (params->work_item_id == -1 || params->work_item_id == workid) { uint64_t systemWorkBeginCount = sys->incWorkItemsBegin(); int cpuId = tc->getCpuPtr()->cpuId(); - if (sys->params()->work_cpus_ckpt_count != 0 && - sys->markWorkItem(cpuId) >= sys->params()->work_cpus_ckpt_count) { + if (params->work_cpus_ckpt_count != 0 && + sys->markWorkItem(cpuId) >= params->work_cpus_ckpt_count) { // // If active cpus equals checkpoint count, create checkpoint // - Event *event = new SimLoopExitEvent("checkpoint", 0); - mainEventQueue.schedule(event, curTick()); + exitSimLoop("checkpoint"); } - if (systemWorkBeginCount == sys->params()->work_begin_ckpt_count) { + if (systemWorkBeginCount == params->work_begin_ckpt_count) { // // Note: the string specified as the cause of the exit event must // exactly equal "checkpoint" inorder to create a checkpoint // - Event *event = new SimLoopExitEvent("checkpoint", 0); - mainEventQueue.schedule(event, curTick()); + exitSimLoop("checkpoint"); } - if (systemWorkBeginCount == sys->params()->work_begin_exit_count) { + if (systemWorkBeginCount == params->work_begin_exit_count) { // // If a certain number of work items started, exit simulation // - Event *event = new SimLoopExitEvent("work started count reach", 0); - mainEventQueue.schedule(event, curTick()); + exitSimLoop("work started count reach"); } - if (tc->getCpuPtr()->cpuId() == sys->params()->work_begin_cpu_id_exit) { + if (cpuId == params->work_begin_cpu_id_exit) { // - // If work started on the specific cpu id specified, exit simulation + // If work started on the cpu id specified, exit simulation // - Event *event = new SimLoopExitEvent("work started on specific cpu", - 0); - - mainEventQueue.schedule(event, curTick() + 1); + exitSimLoop("work started on specific cpu"); } } } // -// This function is executed when annotated work items end. Depending on +// This function is executed when annotated work items end. Depending on // what the user specified at the command line, the simulation may exit and/or // take a checkpoint when a certain work item ends. // void workend(ThreadContext *tc, uint64_t workid, uint64_t threadid) { - tc->getCpuPtr()->workItemEnd(); + DPRINTF(PseudoInst, "PseudoInst::workend(%i, %i)\n", workid, threadid); System *sys = tc->getSystemPtr(); + const System::Params *params = sys->params(); + + if (params->exit_on_work_items) { + exitSimLoop("workend", static_cast(workid)); + return; + } DPRINTF(WorkItems, "Work End workid: %d, threadid %d\n", workid, threadid); + tc->getCpuPtr()->workItemEnd(); + sys->workItemEnd(threadid, workid); // // If specified, determine if this is the specific work item the user // identified // - if (sys->params()->work_item_id == -1 || - sys->params()->work_item_id == workid) { + if (params->work_item_id == -1 || params->work_item_id == workid) { uint64_t systemWorkEndCount = sys->incWorkItemsEnd(); int cpuId = tc->getCpuPtr()->cpuId(); - if (sys->params()->work_cpus_ckpt_count != 0 && - sys->markWorkItem(cpuId) >= sys->params()->work_cpus_ckpt_count) { + if (params->work_cpus_ckpt_count != 0 && + sys->markWorkItem(cpuId) >= params->work_cpus_ckpt_count) { // // If active cpus equals checkpoint count, create checkpoint // - Event *event = new SimLoopExitEvent("checkpoint", 0); - mainEventQueue.schedule(event, curTick()); + exitSimLoop("checkpoint"); } - if (sys->params()->work_end_ckpt_count != 0 && - systemWorkEndCount == sys->params()->work_end_ckpt_count) { + if (params->work_end_ckpt_count != 0 && + systemWorkEndCount == params->work_end_ckpt_count) { // // If total work items completed equals checkpoint count, create // checkpoint // - Event *event = new SimLoopExitEvent("checkpoint", 0); - mainEventQueue.schedule(event, curTick()); + exitSimLoop("checkpoint"); } - if (sys->params()->work_end_exit_count != 0 && - systemWorkEndCount == sys->params()->work_end_exit_count) { + if (params->work_end_exit_count != 0 && + systemWorkEndCount == params->work_end_exit_count) { // // If total work items completed equals exit count, exit simulation // - Event *event = new SimLoopExitEvent("work items exit count reached", - 0); - - mainEventQueue.schedule(event, curTick()); + exitSimLoop("work items exit count reached"); } } }