X-Git-Url: https://git.libre-soc.org/?a=blobdiff_plain;f=src%2Fsoc%2Fdecoder%2Fisa%2Fcaller.py;h=736f7bb59ced1c88aef02586f2a9535b33209323;hb=aeeb3eea30c13aec160a733caa6d5bdf9fcc6c77;hp=874a06973f3666d63917ce2adcf4a11f4efc4690;hpb=c1c613a5a6688c450e0cae04ca193346815bb6fb;p=soc.git diff --git a/src/soc/decoder/isa/caller.py b/src/soc/decoder/isa/caller.py index 874a0697..736f7bb5 100644 --- a/src/soc/decoder/isa/caller.py +++ b/src/soc/decoder/isa/caller.py @@ -1,6 +1,21 @@ from functools import wraps from soc.decoder.orderedset import OrderedSet -from soc.decoder.selectable_int import SelectableInt, selectconcat +from soc.decoder.selectable_int import (FieldSelectableInt, SelectableInt, + selectconcat) +from collections import namedtuple +import math + +instruction_info = namedtuple('instruction_info', + 'func read_regs uninit_regs write_regs ' + \ + 'special_regs op_fields form asmregs') + +special_sprs = { + 'LR': 8, + 'CTR': 9, + 'TAR': 815, + 'XER': 0, + 'VRSAVE': 256} + def create_args(reglist, extra=None): args = OrderedSet() @@ -11,25 +26,62 @@ def create_args(reglist, extra=None): args = [extra] + args return args + class Mem: - def __init__(self): - self.mem = [] - for i in range(128): - self.mem.append(i) + def __init__(self, bytes_per_word=8): + self.mem = {} + self.bytes_per_word = bytes_per_word + self.word_log2 = math.ceil(math.log2(bytes_per_word)) + + def _get_shifter_mask(self, width, remainder): + shifter = ((self.bytes_per_word - width) - remainder) * \ + 8 # bits per byte + mask = (1 << (width * 8)) - 1 + return shifter, mask + + # TODO: Implement ld/st of lesser width + def ld(self, address, width=8): + remainder = address & (self.bytes_per_word - 1) + address = address >> self.word_log2 + assert remainder & (width - 1) == 0, "Unaligned access unsupported!" + if address in self.mem: + val = self.mem[address] + else: + val = 0 + + if width != self.bytes_per_word: + shifter, mask = self._get_shifter_mask(width, remainder) + val = val & (mask << shifter) + val >>= shifter + print("Read {:x} from addr {:x}".format(val, address)) + return val + + def st(self, address, value, width=8): + remainder = address & (self.bytes_per_word - 1) + address = address >> self.word_log2 + assert remainder & (width - 1) == 0, "Unaligned access unsupported!" + print("Writing {:x} to addr {:x}".format(value, address)) + if width != self.bytes_per_word: + if address in self.mem: + val = self.mem[address] + else: + val = 0 + shifter, mask = self._get_shifter_mask(width, remainder) + val &= ~(mask << shifter) + val |= value << shifter + self.mem[address] = val + else: + self.mem[address] = value def __call__(self, addr, sz): - res = [] - for s in range(sz): # TODO: big/little-end - res.append(SelectableInt(self.mem[addr.value + s], 8)) - print ("memread", addr, sz, res) - return selectconcat(*res) + val = self.ld(addr.value, sz) + print ("memread", addr, sz, val) + return SelectableInt(val, sz*8) def memassign(self, addr, sz, val): print ("memassign", addr, sz, val) - for s in range(sz): - byte = (val.value) >> (s*8) & 0xff # TODO: big/little-end - self.mem[addr.value + s] = byte + self.st(addr.value, val.value, sz) class GPR(dict): @@ -70,6 +122,44 @@ class GPR(dict): s = ' '.join(s) print("reg", "%2d" % i, s) +class PC: + def __init__(self, pc_init=0): + self.CIA = SelectableInt(pc_init, 64) + self.NIA = self.CIA + SelectableInt(4, 64) + + def update(self, namespace): + self.CIA = namespace['NIA'].narrow(64) + self.NIA = self.CIA + SelectableInt(4, 64) + namespace['CIA'] = self.CIA + namespace['NIA'] = self.NIA + + +class SPR(dict): + def __init__(self, dec2): + self.sd = dec2 + dict.__init__(self) + + def __getitem__(self, key): + # if key in special_sprs get the special spr, otherwise return key + if isinstance(key, SelectableInt): + key = key.value + key = special_sprs.get(key, key) + if key in self: + return dict.__getitem__(self, key) + else: + import pdb; pdb.set_trace() + return SelectableInt(0, 64) + + def __setitem__(self, key, value): + if isinstance(key, SelectableInt): + key = key.value + key = special_sprs.get(key, key) + dict.__setitem__(self, key, value) + + def __call__(self, ridx): + return self[ridx] + + class ISACaller: # decoder2 - an instance of power_decoder2 @@ -77,40 +167,115 @@ class ISACaller: def __init__(self, decoder2, regfile): self.gpr = GPR(decoder2, regfile) self.mem = Mem() + self.pc = PC() + self.spr = SPR(decoder2) + # TODO, needed here: + # FPR (same as GPR except for FP nums) + # 4.2.2 p124 FPSCR (definitely "separate" - not in SPR) + # note that mffs, mcrfs, mtfsf "manage" this FPSCR + # 2.3.1 CR (and sub-fields CR0..CR6 - CR0 SO comes from XER.SO) + # note that mfocrf, mfcr, mtcr, mtocrf, mcrxrx "manage" CRs + # 2.3.2 LR (actually SPR #8) + # 2.3.3 CTR (actually SPR #9) + # 2.3.4 TAR (actually SPR #815) + # 3.2.2 p45 XER (actually SPR #0) + # 3.2.3 p46 p232 VRSAVE (actually SPR #256) + + # create CR then allow portions of it to be "selectable" (below) + self._cr = SelectableInt(0, 64) # underlying reg + self.cr = FieldSelectableInt(self._cr, list(range(32,64))) + + # "undefined", just set to variable-bit-width int (use exts "max") + self.undefined = SelectableInt(0, 256) # TODO, not hard-code 256! + self.namespace = {'GPR': self.gpr, 'MEM': self.mem, - 'memassign': self.memassign + 'SPR': self.spr, + 'memassign': self.memassign, + 'NIA': self.pc.NIA, + 'CIA': self.pc.CIA, + 'CR': self.cr, + 'undefined': self.undefined, + 'mode_is_64bit': True, } + + # field-selectable versions of Condition Register TODO check bitranges? + self.crl = [] + for i in range(8): + bits = tuple(range((7-i)*4, (8-i)*4))# errr... maybe? + _cr = FieldSelectableInt(self.cr, bits) + self.crl.append(_cr) + self.namespace["CR%d" % i] = _cr + self.decoder = decoder2 def memassign(self, ea, sz, val): self.mem.memassign(ea, sz, val) - def prep_namespace(self): - si = yield self.decoder.SI - self.namespace['SI'] = SelectableInt(si, bits=16) + def prep_namespace(self, formname, op_fields): + # TODO: get field names from form in decoder*1* (not decoder2) + # decoder2 is hand-created, and decoder1.sigform is auto-generated + # from spec + # then "yield" fields only from op_fields rather than hard-coded + # list, here. + fields = self.decoder.sigforms[formname] + for name in op_fields: + if name == 'spr': + sig = getattr(fields, name.upper()) + else: + sig = getattr(fields, name) + val = yield sig + self.namespace[name] = SelectableInt(val, sig.width) def call(self, name): - yield from self.prep_namespace() + # TODO, asmregs is from the spec, e.g. add RT,RA,RB + # see http://bugs.libre-riscv.org/show_bug.cgi?id=282 + info = self.instrs[name] + yield from self.prep_namespace(info.form, info.op_fields) - function, read_regs, uninit_regs, write_regs = self.instrs[name] - input_names = create_args(read_regs | uninit_regs) + # preserve order of register names + input_names = create_args(list(info.read_regs) + list(info.uninit_regs)) print(input_names) + # main registers (RT, RA ...) inputs = [] for name in input_names: regnum = yield getattr(self.decoder, name) + regname = "_" + name + self.namespace[regname] = regnum print('reading reg %d' % regnum) inputs.append(self.gpr(regnum)) + + # "special" registers + for special in info.special_regs: + if special in special_sprs: + inputs.append(self.spr[special]) + else: + inputs.append(self.namespace[special]) + print(inputs) - results = function(self, *inputs) + results = info.func(self, *inputs) print(results) - output_names = create_args(write_regs) - for name, output in zip(output_names, results): - regnum = yield getattr(self.decoder, name) - print('writing reg %d' % regnum) - self.gpr[regnum] = output.narrow(64) + # any modified return results? + if info.write_regs: + output_names = create_args(info.write_regs) + for name, output in zip(output_names, results): + if name in info.special_regs: + print('writing special %s' % name, output) + if name in special_sprs: + self.spr[name] = output + else: + self.namespace[name].eq(output) + else: + regnum = yield getattr(self.decoder, name) + print('writing reg %d' % regnum) + if output.bits > 64: + output = SelectableInt(output.value, 64) + self.gpr[regnum] = output + + # update program counter + self.pc.update(self.namespace) def inject(): @@ -126,8 +291,8 @@ def inject(): context = args[0].namespace saved_values = func_globals.copy() # Shallow copy of dict. func_globals.update(context) - result = func(*args, **kwargs) + args[0].namespace = func_globals #exec (func.__code__, func_globals) #finally: