X-Git-Url: https://git.libre-soc.org/?a=blobdiff_plain;f=src%2Fsoc%2Fdecoder%2Fisa%2Ftest_caller.py;h=6863fff3d61f1bc0234f1be3cbbba35e78fc60e8;hb=5bb90038d6820e42f8dfbd9803294405f56db1cf;hp=a43f4a28405f19141cfea0aad40dc7bc86d8c966;hpb=8fdfdf62b1934fe8520b19751c5f83a509688792;p=soc.git

diff --git a/src/soc/decoder/isa/test_caller.py b/src/soc/decoder/isa/test_caller.py
index a43f4a28..6863fff3 100644
--- a/src/soc/decoder/isa/test_caller.py
+++ b/src/soc/decoder/isa/test_caller.py
@@ -16,7 +16,9 @@ class Register:
     def __init__(self, num):
         self.num = num
 
-def run_tst(generator, initial_regs, initial_sprs={}):
+def run_tst(generator, initial_regs, initial_sprs=None, svstate=0, mmu=False):
+    if initial_sprs is None:
+        initial_sprs = {}
     m = Module()
     comb = m.d.comb
     instruction = Signal(32)
@@ -30,8 +32,10 @@ def run_tst(generator, initial_regs, initial_sprs={}):
     m.submodules.pdecode2 = pdecode2 = PowerDecode2(pdecode)
     simulator = ISA(pdecode2, initial_regs, initial_sprs, 0,
                     initial_insns=gen, respect_pc=True,
+                    initial_svstate=svstate,
                     disassembly=insncode,
-                    bigendian=0)
+                    bigendian=0,
+                    mmu=mmu)
     comb += pdecode2.dec.raw_opcode_in.eq(instruction)
     sim = Simulator(m)
 
@@ -50,7 +54,7 @@ def run_tst(generator, initial_regs, initial_sprs={}):
             yield Settle()
 
             ins, code = instructions[index]
-            print("0x{:X}".format(ins & 0xffffffff))
+            print("    0x{:X}".format(ins & 0xffffffff))
             opname = code.split(' ')[0]
             print(code, opname)