X-Git-Url: https://git.libre-soc.org/?a=blobdiff_plain;f=src%2Fsoc%2Fdecoder%2Fisa%2Ftest_caller_radix.py;fp=src%2Fsoc%2Fdecoder%2Fisa%2Ftest_caller_radix.py;h=c8b2f66d518ae964590bb6f50d333099ef524e48;hb=e7101f130031c2e30977cda7a1cb9542b252ea7c;hp=40ab2b2a9cf8a7974e07c539cd84267dc90141ba;hpb=59a8fa1365c3f27aab4dbe9cbaeee416bc7a97f1;p=soc.git

diff --git a/src/soc/decoder/isa/test_caller_radix.py b/src/soc/decoder/isa/test_caller_radix.py
index 40ab2b2a..c8b2f66d 100644
--- a/src/soc/decoder/isa/test_caller_radix.py
+++ b/src/soc/decoder/isa/test_caller_radix.py
@@ -33,23 +33,30 @@ testmem = {
            0x40000000000300ad,
           }
 
-prtbl = 0x1000000
+prtbl = 0x1000000 # matches PROCESS_TABLE_3 above
 
 class DecoderTestCase(FHDLTestCase):
 
     def test_load(self):
         lst = [ "lwz 3, 0(1)"
                ]
-        with Program(lst, bigendian=False) as program:
-            initial_regs=[0] * 32
-            initial_regs[1] = 0x1000
-            initial_regs[2] = 0x1234
+        sprs = {'DSISR': SelectableInt(0, 64),
+                'DAR': SelectableInt(0, 64),
+                'PIDR': SelectableInt(0, 64),
+                'PRTBL': SelectableInt(prtbl, 64)
+        }
+
+        initial_regs=[0] * 32
+        initial_regs[1] = 0x1000
+        initial_regs[2] = 0x1234
 
-            initial_mem = deepcopy(testmem)
-            initial_mem[0x1000] = 0x1337 # data to be read
+        initial_mem = deepcopy(testmem)
+        initial_mem[0x1000] = 0x1337 # data to be read
 
+        with Program(lst, bigendian=False) as program:
             sim = self.run_tst_program(program, initial_regs=initial_regs,
-                                                initial_mem=initial_mem)
+                                                initial_mem=initial_mem,
+                                                initial_sprs=sprs)
             self.assertEqual(sim.gpr(3), SelectableInt(0x1337, 64))
 
     def test_load_store(self):
@@ -58,29 +65,32 @@ class DecoderTestCase(FHDLTestCase):
                "stw 2, 0(1)",
                "lwz 3, 0(1)"
                ]
+        # set up dummy minimal ISACaller
+        sprs = {'DSISR': SelectableInt(0, 64),
+                'DAR': SelectableInt(0, 64),
+                'PIDR': SelectableInt(0, 64),
+                'PRTBL': SelectableInt(prtbl, 64)
+        }
+
+        initial_regs=[0] * 32
+        initial_regs[1] = 0x1000
+        initial_regs[2] = 0x1234
+        initial_mem = deepcopy(testmem)
+
         with Program(lst, bigendian=False) as program:
-            initial_regs=[0] * 32
-            initial_regs[1] = 0x1000
-            initial_regs[2] = 0x1234
-            initial_mem = deepcopy(testmem)
             sim = self.run_tst_program(program, initial_regs=initial_regs,
-                                                initial_mem=initial_mem)
+                                                initial_mem=initial_mem,
+                                                initial_sprs=sprs)
             self.assertEqual(sim.gpr(3), SelectableInt(0x1234, 64))
 
-    def run_tst_program(self, prog, initial_regs=None, initial_mem=None):
+    def run_tst_program(self, prog, initial_regs=None, initial_mem=None,
+                                    initial_sprs=None):
         # DO NOT set complex arguments, it is a "singleton" pattern
         if initial_regs is None:
             initial_regs = [0] * 32
 
-        # set up dummy minimal ISACaller
-        spr = {'DSISR': SelectableInt(0, 64),
-               'DAR': SelectableInt(0, 64),
-               'PIDR': SelectableInt(0, 64),
-               'PRTBL': SelectableInt(prtbl, 64)
-        }
-
         simulator = run_tst(prog, initial_regs, mmu=True, mem=initial_mem,
-                    initial_sprs=spr)
+                    initial_sprs=initial_sprs)
         simulator.gpr.dump()
         return simulator