X-Git-Url: https://git.libre-soc.org/?a=blobdiff_plain;f=src%2Fsoc%2Fdecoder%2Fpower_decoder.py;h=2b01d4d437e6045983e832c987a30d8dc1329094;hb=d351455aa31a6b9383a3eee69d68eff3d40fe5a6;hp=36b57b07f39a8f0aacd7c7dfdd97411bdb9c49f3;hpb=0c8ffbb3d8580f04c21d6b522d8d1d5e670cb6f3;p=soc.git

diff --git a/src/soc/decoder/power_decoder.py b/src/soc/decoder/power_decoder.py
index 36b57b07..2b01d4d4 100644
--- a/src/soc/decoder/power_decoder.py
+++ b/src/soc/decoder/power_decoder.py
@@ -1,6 +1,6 @@
 """Cascading Power ISA Decoder
 
-License: LGPLv3
+License: LGPLv3+
 
 # Copyright (C) 2020 Luke Kenneth Casson Leighton <lkcl@lkcl.net>
 # Copyright (C) 2020 Michael Nolan <mtnolan2640@gmail.com>
@@ -92,13 +92,14 @@ from nmigen import Module, Elaboratable, Signal, Cat, Mux
 from nmigen.cli import rtlil
 from soc.decoder.power_enums import (Function, Form, MicrOp,
                                      In1Sel, In2Sel, In3Sel, OutSel,
-                                     RC, LdstLen, LDSTMode, CryIn, get_csv,
+                                     SVEtype, SVPtype, # Simple-V
+                                     RC, LdstLen, LDSTMode, CryIn,
                                      single_bit_flags, CRInSel,
                                      CROutSel, get_signal_name,
                                      default_values, insns, asmidx)
 from soc.decoder.power_fields import DecodeFields
 from soc.decoder.power_fieldsn import SigDecode, SignalBitRange
-
+from soc.decoder.power_svp64 import SVP64RM
 
 # key data structure in which the POWER decoder is specified,
 # in a hierarchical fashion
@@ -118,6 +119,8 @@ power_op_types = {'function_unit': Function,
                   'internal_op': MicrOp,
                   'form': Form,
                   'asmcode': 8,
+                  'SV_Etype': SVEtype,
+                  'SV_Ptype': SVPtype,
                   'in1_sel': In1Sel,
                   'in2_sel': In2Sel,
                   'in3_sel': In3Sel,
@@ -451,7 +454,7 @@ class TopPowerDecoder(PowerDecoder):
             setattr(self, fname, sig)
 
         # create signals for all field forms
-        self.form_names = forms = self.fields.instrs.keys()
+        forms = self.form_names
         self.sigforms = {}
         for form in forms:
             fields = self.fields.instrs[form]
@@ -468,6 +471,10 @@ class TopPowerDecoder(PowerDecoder):
 
         self.tree_analyse()
 
+    @property
+    def form_names(self):
+        return self.fields.instrs.keys()
+
     def elaborate(self, platform):
         m = PowerDecoder.elaborate(self, platform)
         comb = m.d.comb
@@ -509,6 +516,11 @@ def create_pdecode(name=None, col_subset=None, row_subset=None):
     subsetting of the PowerOp decoding is possible by setting col_subset
     """
 
+    # some alteration to the CSV files is required for SV so we use
+    # a class to do it
+    isa = SVP64RM()
+    get_csv = isa.get_svp64_csv
+
     # minor 19 has extra patterns
     m19 = []
     m19.append(Subdecoder(pattern=19, opcodes=get_csv("minor_19.csv"),