X-Git-Url: https://git.libre-soc.org/?a=blobdiff_plain;f=src%2Fsoc%2Fdecoder%2Fpower_pseudo.py;h=3e02cb78a37c313d42800a58eb410d57655d63b0;hb=16598f451a219b36f01ac8ddc11b6417422fc430;hp=188ef0c2da4dd75aff47140309d5a8c42772e9f3;hpb=4adfb9105786dcd64874eedd8b774912ee9cc5d0;p=soc.git

diff --git a/src/soc/decoder/power_pseudo.py b/src/soc/decoder/power_pseudo.py
index 188ef0c2..3e02cb78 100644
--- a/src/soc/decoder/power_pseudo.py
+++ b/src/soc/decoder/power_pseudo.py
@@ -139,13 +139,58 @@ do i = 0 to 7
     print(i)
 """
 
+testcond = """
+ctr_ok <- BO[2] | ((CTR[M:63] != 0) ^ BO[3])
+cond_ok <- BO[0] | ¬(CR[BI+32] ^  BO[1])
+"""
+
+lswx = """
+if RA = 0 then EA <- 0
+else           EA <- (RA)
+if NB = 0 then n <-  32
+else           n <-  NB
+r <- RT - 1
+i <- 32
+do while n > 0
+    if i = 32 then
+        r <- (r + 1) % 32
+        GPR(r) <- 0
+    GPR(r)[i:i+7] <- MEM(EA, 1)
+    i <- i + 8
+    if i = 64 then i <- 32
+    EA <- EA + 1
+    n <- n - 1
+"""
+
+_lswx = """
+GPR(r)[x] <- 1
+"""
+
+switchtest = """
+switch (n)
+    case(1): x <- 5
+    case(2): fallthrough
+    case(3):
+        x <- 3
+    case(4): fallthrough
+    default:
+        x <- 9
+"""
+
+hextest = """
+RT <- 0x0001_a000_0000_0000
+"""
+
+code = hextest
+#code = lswx
+#code = testcond
 #code = testdo
 #code = _bpermd
 #code = testmul
 #code = testgetzero
 #code = testcat
 #code = testgpr
-code = testmem
+#code = testmem
 #code = testgprslice
 #code = testreg
 #code = cnttzd
@@ -166,15 +211,19 @@ def tolist(num):
 def get_reg_hex(reg):
     return hex(reg.value)
 
-def convert_to_python(pcode):
 
-    gsc = GardenSnakeCompiler()
+def convert_to_python(pcode, form, incl_carry):
+
+    print("form", form)
+    gsc = GardenSnakeCompiler(form=form, incl_carry=incl_carry)
 
     tree = gsc.compile(pcode, mode="exec", filename="string")
     tree = ast.fix_missing_locations(tree)
     regsused = {'read_regs': gsc.parser.read_regs,
                 'write_regs': gsc.parser.write_regs,
-                'uninit_regs': gsc.parser.uninit_regs}
+                'uninit_regs': gsc.parser.uninit_regs,
+                'special_regs': gsc.parser.special_regs,
+                'op_fields': gsc.parser.op_fields}
     return astor.to_source(tree), regsused
 
 
@@ -207,12 +256,15 @@ def test():
         print("args", args)
         print("-->", " ".join(map(str, args)))
 
-    from soc.decoder.helpers import (EXTS64, EXTZ64, ROTL64, ROTL32, MASK,)
+    from soc.decoder.helpers import (EXTS64, EXTZ64, ROTL64, ROTL32, MASK,
+                                     trunc_div, trunc_rem)
 
     d = {}
     d["print"] = print_
     d["EXTS64"] = EXTS64
     d["EXTZ64"] = EXTZ64
+    d["trunc_div"] = trunc_div
+    d["trunc_rem"] = trunc_rem
     d["SelectableInt"] = SelectableInt
     d["concat"] = selectconcat
     d["GPR"] = gsc.gpr
@@ -256,8 +308,8 @@ def test():
             # read regs, drop them into dict for function
             for rname in gsc.parser.read_regs:
                 regidx = yield getattr(decode.sigforms['X'], rname)
-                d[rname] = gsc.gpr[regidx] # contents of regfile
-                d["_%s" % rname] = regidx # actual register value
+                d[rname] = gsc.gpr[regidx]  # contents of regfile
+                d["_%s" % rname] = regidx  # actual register value
                 print("read reg", rname, regidx, hex(d[rname].value))
 
             exec(compiled_code, d)  # code gets executed here in dict "d"
@@ -291,7 +343,8 @@ def test():
         for j in range(16):
             hexstr.append("%02x" % gsc.mem.mem[i+j])
         hexstr = ' '.join(hexstr)
-        print ("mem %4x" % i, hexstr)
+        print("mem %4x" % i, hexstr)
+
 
 if __name__ == '__main__':
     test()