X-Git-Url: https://git.libre-soc.org/?a=blobdiff_plain;f=src%2Fsoc%2Fdecoder%2Fpower_regspec_map.py;h=05ff4814e2504e3acbc5924b614031b460f8bd7c;hb=e653b5cb1e6e5a8c2070841a67f3c812d2a0f90c;hp=1e6cf3af2356ab7e6f290290823dac4a1cf2a93c;hpb=31f953f78f24b553a8deff212bcde9e31cf13c82;p=soc.git

diff --git a/src/soc/decoder/power_regspec_map.py b/src/soc/decoder/power_regspec_map.py
index 1e6cf3af..05ff4814 100644
--- a/src/soc/decoder/power_regspec_map.py
+++ b/src/soc/decoder/power_regspec_map.py
@@ -58,9 +58,8 @@ def regspec_decode_read(e, regfile, name):
 
     if regfile == 'CR':
         # CRRegs register numbering is *unary* encoded
-        # *sigh*.  numbering inverted on part-CRs.  because POWER.
-        if name == 'full_cr': # full CR
-            return e.do.read_cr_whole, 0b11111111
+        if name == 'full_cr': # full CR (from FXM field)
+            return e.do.read_cr_whole.ok, e.do.read_cr_whole.data
         if name == 'cr_a': # CR A
             return e.read_cr1.ok, 1<<(7-e.read_cr1.data)
         if name == 'cr_b': # CR B
@@ -78,19 +77,21 @@ def regspec_decode_read(e, regfile, name):
         if name == 'xer_so':
             # SO needs to be read for overflow *and* for creation
             # of CR0 and also for MFSPR
-            return ((e.do.oe.oe[0] & e.do.oe.oe_ok) | e.xer_in |
+            return ((e.do.oe.oe[0] & e.do.oe.ok) | (e.xer_in & SO == SO)|
                      (e.do.rc.rc & e.do.rc.ok)), SO
         if name == 'xer_ov':
-            return (e.do.oe.oe[0] & e.do.oe.oe_ok) | e.xer_in, OV
+            return ((e.do.oe.oe[0] & e.do.oe.ok) |
+                    (e.xer_in & CA == CA)), OV
         if name == 'xer_ca':
-            return (e.do.input_carry == CryIn.CA.value) | e.xer_in, CA
+            return ((e.do.input_carry == CryIn.CA.value) |
+                    (e.xer_in & OV == OV)), CA
 
     # STATE regfile
 
     if regfile == 'STATE':
         # STATE register numbering is *unary* encoded
         PC = 1<<StateRegs.PC
-        MSR = 1<<Stateegs.MSR
+        MSR = 1<<StateRegs.MSR
         if name in ['cia', 'nia']:
             return Const(1), PC # TODO: detect read-conditions
         if name == 'msr':
@@ -133,8 +134,8 @@ def regspec_decode_write(e, regfile, name):
     if regfile == 'CR':
         # CRRegs register numbering is *unary* encoded
         # *sigh*.  numbering inverted on part-CRs.  because POWER.
-        if name == 'full_cr': # full CR
-            return e.do.write_cr_whole, 0b11111111
+        if name == 'full_cr': # full CR (from FXM field)
+            return e.do.write_cr_whole.ok, e.do.write_cr_whole.data
         if name == 'cr_a': # CR A
             return e.write_cr, 1<<(7-e.write_cr.data)