X-Git-Url: https://git.libre-soc.org/?a=blobdiff_plain;f=src%2Fsoc%2Fdecoder%2Fpseudo%2Fpywriter.py;h=a9f58acd536f094c67f3ec6c7e67970ca3301cb3;hb=237d4f455ae825941b0542819c02fdc87585808a;hp=600c11233809b3e314cbe998fa4e616283319d45;hpb=57618dc33c2cc077e947f81a63927a1890e2cdeb;p=soc.git

diff --git a/src/soc/decoder/pseudo/pywriter.py b/src/soc/decoder/pseudo/pywriter.py
index 600c1123..a9f58acd 100644
--- a/src/soc/decoder/pseudo/pywriter.py
+++ b/src/soc/decoder/pseudo/pywriter.py
@@ -3,26 +3,23 @@
 import os
 from soc.decoder.pseudo.pagereader import ISA
 from soc.decoder.power_pseudo import convert_to_python
+from soc.decoder.orderedset import OrderedSet
+from soc.decoder.isa.caller import create_args
 
 def get_isasrc_dir():
     fdir = os.path.abspath(os.path.dirname(__file__))
     fdir = os.path.split(fdir)[0]
     return os.path.join(fdir, "isa")
 
-def create_args(reglist, extra=None):
-    args = set()
-    for reg in reglist:
-        args.add(reg)
-    args = list(args)
-    if extra:
-        args = [extra] + args
-    return ', '.join(args)
 
 header = """\
 # auto-generated by pywriter.py, do not edit or commit
 
-from soc.decoder.isa import ISACaller
+from soc.decoder.isa.caller import ISACaller, inject
 from soc.decoder.helpers import (EXTS64, EXTZ64, ROTL64, ROTL32, MASK,)
+from soc.decoder.selectable_int import SelectableInt
+from soc.decoder.selectable_int import selectconcat as concat
+from soc.decoder.orderedset import OrderedSet
 
 class %s(ISACaller):
 
@@ -47,11 +44,15 @@ class PyISAWriter(ISA):
                 print (pcode)
                 pycode, rused = convert_to_python(pcode)
                 # create list of arguments to call
-                regs = rused['read_regs'] + rused['uninit_regs']
-                args = create_args(regs, 'self')
+                regs = list(rused['read_regs']) + list(rused['uninit_regs'])
+                args = ', '.join(create_args(regs, 'self'))
                 # create list of arguments to return
-                retargs = create_args(rused['write_regs'])
-                f.write("    def %s(%s):\n" % (page.replace(".", "_"), args))
+                retargs = ', '.join(create_args(rused['write_regs']))
+                # write out function.  pre-pend "op_" because some instrs are
+                # also python keywords (cmp).  also replace "." with "_"
+                op_fname ="op_%s" % page.replace(".", "_")
+                f.write("    @inject(self.namespace)\n")
+                f.write("    def %s(%s):\n" % (op_fname, args))
                 pycode = pycode.split("\n")
                 pycode = '\n'.join(map(lambda x: "        %s" % x, pycode))
                 pycode = pycode.rstrip()
@@ -61,15 +62,19 @@ class PyISAWriter(ISA):
                 else:
                     f.write("\n")
                 # accumulate the instruction info
-                iinfo = "(%s, %s, %s, %s)" % \
-                            (page, rused['read_regs'],
+                iinfo = "(%s, %s,\n                %s, %s)" % \
+                            (op_fname, rused['read_regs'],
                             rused['uninit_regs'], rused['write_regs'])
-                iinf += "    instrs['%s'] = %s\n" % (pagename, iinfo)
+                iinf += "    instrs['%s'] = %s\n" % (page, iinfo)
             # write out initialisation of info, for ISACaller to use
             f.write("    instrs = {}\n")
             f.write(iinf)
 
 if __name__ == '__main__':
     isa = PyISAWriter()
+    isa.write_pysource('fixedlogical')
+    exit(0)
+    isa.write_pysource('fixedstore')
+    isa.write_pysource('fixedload')
     isa.write_pysource('comparefixed')
     isa.write_pysource('fixedarith')