X-Git-Url: https://git.libre-soc.org/?a=blobdiff_plain;f=src%2Fsoc%2Fexperiment%2Fcompldst_multi.py;h=ddbd0804ebb387e141f08551b5f343b0f7e2e5a1;hb=08ed759bb115235238babcb11c584424b237abc8;hp=f94252f41e4c19ae58ab3c8c08c44c8fd7eaa618;hpb=22134d3448e8dc2d4665a5c77dbf92b5bc7d9373;p=soc.git diff --git a/src/soc/experiment/compldst_multi.py b/src/soc/experiment/compldst_multi.py index f94252f4..ddbd0804 100644 --- a/src/soc/experiment/compldst_multi.py +++ b/src/soc/experiment/compldst_multi.py @@ -103,6 +103,7 @@ from openpower.decoder.power_enums import MicrOp, Function, LDSTMode from soc.fu.ldst.ldst_input_record import CompLDSTOpSubset from openpower.decoder.power_decoder2 import Data from openpower.consts import MSR +from openpower.power_enums import MSRSpec from soc.config.test.test_loadstore import TestMemPspec # for debugging dcbz @@ -294,6 +295,7 @@ class LDSTCompUnit(RegSpecAPI, Elaboratable): rda_any = Signal(reset_less=True) # any read for address ops rd_done = Signal(reset_less=True) # all *necessary* operands read wr_reset = Signal(reset_less=True) # final reset condition + canceln = Signal(reset_less=True) # cancel (active low) # LD and ALU out alu_o = Signal(self.data_wid, reset_less=True) @@ -367,7 +369,7 @@ class LDSTCompUnit(RegSpecAPI, Elaboratable): sync += opc_l.r.eq(reset_o) # XXX NOTE: INVERTED FROM book! # src operand latch - sync += src_l.s.eq(Repl(issue_i, self.n_src)) + sync += src_l.s.eq(Repl(issue_i, self.n_src) & ~self.rdmaskn) sync += src_l.r.eq(reset_r) #### sync += Display("reset_r = %i",reset_r) @@ -444,7 +446,7 @@ class LDSTCompUnit(RegSpecAPI, Elaboratable): # now do the ALU addr add: one cycle, and say "ready" (next cycle, too) comb += alu_o.eq(src1_or_z + src2_or_imm) # actual EA - m.d.sync += alu_ok.eq(alu_valid) # keep ack in sync with EA + m.d.sync += alu_ok.eq(alu_valid & canceln) # keep ack in sync with EA ############################ # Control Signal calculation @@ -457,13 +459,14 @@ class LDSTCompUnit(RegSpecAPI, Elaboratable): # 2nd operand only needed when immediate is not active slg = Cat(op_is_z, op_is_imm) #is this correct ? bro = Repl(self.busy_o, self.n_src) - comb += self.rd.rel_o.eq(src_l.q & bro & ~slg & ~self.rdmaskn) + comb += self.rd.rel_o.eq(src_l.q & bro & ~slg) # note when the address-related read "go" signals are active comb += rda_any.eq(self.rd.go_i[0] | self.rd.go_i[1]) # alu input valid when 1st and 2nd ops done (or imm not active) - comb += alu_valid.eq(busy_o & ~(self.rd.rel_o[0] | self.rd.rel_o[1])) + comb += alu_valid.eq(busy_o & ~(self.rd.rel_o[0] | self.rd.rel_o[1]) & + canceln) # 3rd operand only needed when operation is a store comb += self.rd.rel_o[2].eq(src_l.q[2] & busy_o & op_is_st) @@ -477,26 +480,25 @@ class LDSTCompUnit(RegSpecAPI, Elaboratable): # the write/store (etc) all must be cancelled if an exception occurs # note: cancel is active low, like shadown_i, # while exc_o.happpened is active high - cancel = Signal(reset_less=True) - comb += cancel.eq(~self.exc_o.happened & self.shadown_i) + comb += canceln.eq(~self.exc_o.happened & self.shadown_i) # store release when st ready *and* all operands read (and no shadow) # dcbz is special case of store -- TODO verify shadows comb += self.st.rel_o.eq(sto_l.q & busy_o & rd_done & op_is_st_or_dcbz & - cancel) + canceln) # request write of LD result. waits until shadow is dropped. comb += self.wr.rel_o[0].eq(rd_done & wri_l.q & busy_o & lod_l.qn & - op_is_ld & cancel) + op_is_ld & canceln) # request write of EA result only in update mode comb += self.wr.rel_o[1].eq(upd_l.q & busy_o & op_is_update & - alu_valid & cancel) + alu_valid & canceln) # provide "done" signal: select req_rel for non-LD/ST, adr_rel for LD/ST comb += wr_any.eq(self.st.go_i | p_st_go | self.wr.go_i[0] | self.wr.go_i[1]) - comb += wr_reset.eq(rst_l.q & busy_o & cancel & + comb += wr_reset.eq(rst_l.q & busy_o & canceln & ~(self.st.rel_o | self.wr.rel_o[0] | self.wr.rel_o[1]) & (lod_l.qn | op_is_st_or_dcbz) @@ -532,13 +534,15 @@ class LDSTCompUnit(RegSpecAPI, Elaboratable): # address: use sync to avoid long latency sync += pi.addr.data.eq(addr_r) # EA from adder with m.If(op_is_dcbz): - sync += Display("DCBZ: EA from adder %i",addr_r) + sync += Display("LDSTCompUnit.DCBZ: EA from adder %x", addr_r) sync += pi.addr.ok.eq(alu_ok & lsd_l.q) # "do address stuff" (once) comb += self.exc_o.eq(pi.exc_o) # exception occurred comb += addr_ok.eq(self.pi.addr_ok_o) # no exc, address fine # connect MSR.PR for priv/virt operation - comb += pi.msr_pr.eq(oper_r.msr[MSR.PR]) + comb += pi.priv_mode.eq(oper_r.msr[MSR.PR]) + comb += Display("LDSTCompUnit: oper_r.msr %x pi.msr_pr=%x", + oper_r.msr, oper_r.msr[MSR.PR]) # byte-reverse on LD revnorev = Signal(64, reset_less=True)